V4L/DVB (3532): Moved duplicated code of ALPS BSRU6 tuner to a standalone file.
Moved duplicated code of ALPS BSRU6 tuner to a standalone file. Modified av7110 and budget drivers to include the new file. Signed-off-by: Perceval Anichini <perceval.anichini@streamvision.fr> Signed-off-by: Oliver Endriss <o.endriss@gmx.de> Signed-off-by: Mauro Carvalho Chehab <mchehab@infradead.org>
This commit is contained in:
Perceval Anichini
Linus Torvalds
parent
ad5125913b
commit
265366e8fb
5 changed files with 145 additions and 414 deletions
140
drivers/media/dvb/frontends/bsru6.h
Normal file
140
drivers/media/dvb/frontends/bsru6.h
Normal file
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@ -0,0 +1,140 @@
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/*
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* bsru6.h - ALPS BSRU6 tuner support (moved from budget-ci.c)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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* Or, point your browser to http://www.gnu.org/copyleft/gpl.html
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*
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*
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* the project's page is at http://www.linuxtv.org
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*/
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#ifndef BSRU6_H
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#define BSRU6_H
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static u8 alps_bsru6_inittab[] = {
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0x01, 0x15,
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0x02, 0x00,
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0x03, 0x00,
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0x04, 0x7d, /* F22FR = 0x7d, F22 = f_VCO / 128 / 0x7d = 22 kHz */
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0x05, 0x35, /* I2CT = 0, SCLT = 1, SDAT = 1 */
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0x06, 0x40, /* DAC not used, set to high impendance mode */
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0x07, 0x00, /* DAC LSB */
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0x08, 0x40, /* DiSEqC off, LNB power on OP2/LOCK pin on */
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0x09, 0x00, /* FIFO */
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0x0c, 0x51, /* OP1 ctl = Normal, OP1 val = 1 (LNB Power ON) */
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0x0d, 0x82, /* DC offset compensation = ON, beta_agc1 = 2 */
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0x0e, 0x23, /* alpha_tmg = 2, beta_tmg = 3 */
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0x10, 0x3f, // AGC2 0x3d
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0x11, 0x84,
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0x12, 0xb9,
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0x15, 0xc9, // lock detector threshold
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0x16, 0x00,
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0x17, 0x00,
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0x18, 0x00,
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0x19, 0x00,
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0x1a, 0x00,
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0x1f, 0x50,
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0x20, 0x00,
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0x21, 0x00,
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0x22, 0x00,
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0x23, 0x00,
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0x28, 0x00, // out imp: normal out type: parallel FEC mode:0
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0x29, 0x1e, // 1/2 threshold
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0x2a, 0x14, // 2/3 threshold
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0x2b, 0x0f, // 3/4 threshold
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0x2c, 0x09, // 5/6 threshold
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0x2d, 0x05, // 7/8 threshold
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0x2e, 0x01,
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0x31, 0x1f, // test all FECs
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0x32, 0x19, // viterbi and synchro search
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0x33, 0xfc, // rs control
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0x34, 0x93, // error control
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0x0f, 0x52,
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0xff, 0xff
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};
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static int alps_bsru6_set_symbol_rate(struct dvb_frontend *fe, u32 srate, u32 ratio)
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{
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u8 aclk = 0;
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u8 bclk = 0;
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if (srate < 1500000) {
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aclk = 0xb7;
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bclk = 0x47;
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} else if (srate < 3000000) {
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aclk = 0xb7;
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bclk = 0x4b;
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} else if (srate < 7000000) {
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aclk = 0xb7;
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bclk = 0x4f;
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} else if (srate < 14000000) {
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aclk = 0xb7;
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bclk = 0x53;
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} else if (srate < 30000000) {
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aclk = 0xb6;
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bclk = 0x53;
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} else if (srate < 45000000) {
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aclk = 0xb4;
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bclk = 0x51;
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}
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stv0299_writereg(fe, 0x13, aclk);
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stv0299_writereg(fe, 0x14, bclk);
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stv0299_writereg(fe, 0x1f, (ratio >> 16) & 0xff);
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stv0299_writereg(fe, 0x20, (ratio >> 8) & 0xff);
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stv0299_writereg(fe, 0x21, ratio & 0xf0);
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return 0;
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}
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static int alps_bsru6_pll_set(struct dvb_frontend *fe, struct i2c_adapter *i2c, struct dvb_frontend_parameters *params)
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{
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u8 buf[4];
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u32 div;
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struct i2c_msg msg = { .addr = 0x61, .flags = 0, .buf = buf, .len = sizeof(buf) };
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if ((params->frequency < 950000) || (params->frequency > 2150000))
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return -EINVAL;
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div = (params->frequency + (125 - 1)) / 125; // round correctly
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buf[0] = (div >> 8) & 0x7f;
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buf[1] = div & 0xff;
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buf[2] = 0x80 | ((div & 0x18000) >> 10) | 4;
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buf[3] = 0xC4;
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if (params->frequency > 1530000)
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buf[3] = 0xc0;
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if (i2c_transfer(i2c, &msg, 1) != 1)
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return -EIO;
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return 0;
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}
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static struct stv0299_config alps_bsru6_config = {
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.demod_address = 0x68,
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.inittab = alps_bsru6_inittab,
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.mclk = 88000000UL,
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.invert = 1,
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.skip_reinit = 0,
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.lock_output = STV0229_LOCKOUTPUT_1,
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.volt13_op0_op1 = STV0299_VOLT13_OP1,
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.min_delay_ms = 100,
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.set_symbol_rate = alps_bsru6_set_symbol_rate,
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.pll_set = alps_bsru6_pll_set,
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};
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#endif
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@ -68,6 +68,7 @@
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#include "bsbe1.h"
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#include "lnbp21.h"
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#include "bsru6.h"
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#define TS_WIDTH 376
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#define TS_HEIGHT 512
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@ -1570,109 +1571,6 @@ static struct ves1x93_config alps_bsrv2_config = {
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.pll_set = alps_bsrv2_pll_set,
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};
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static u8 alps_bsru6_inittab[] = {
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0x01, 0x15,
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0x02, 0x30,
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0x03, 0x00,
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0x04, 0x7d, /* F22FR = 0x7d, F22 = f_VCO / 128 / 0x7d = 22 kHz */
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0x05, 0x35, /* I2CT = 0, SCLT = 1, SDAT = 1 */
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0x06, 0x40, /* DAC not used, set to high impendance mode */
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0x07, 0x00, /* DAC LSB */
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0x08, 0x40, /* DiSEqC off, LNB power on OP2/LOCK pin on */
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0x09, 0x00, /* FIFO */
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0x0c, 0x51, /* OP1 ctl = Normal, OP1 val = 1 (LNB Power ON) */
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0x0d, 0x82, /* DC offset compensation = ON, beta_agc1 = 2 */
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0x0e, 0x23, /* alpha_tmg = 2, beta_tmg = 3 */
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0x10, 0x3f, // AGC2 0x3d
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0x11, 0x84,
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0x12, 0xb9,
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0x15, 0xc9, // lock detector threshold
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0x16, 0x00,
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0x17, 0x00,
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0x18, 0x00,
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0x19, 0x00,
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0x1a, 0x00,
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0x1f, 0x50,
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0x20, 0x00,
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0x21, 0x00,
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0x22, 0x00,
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0x23, 0x00,
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0x28, 0x00, // out imp: normal out type: parallel FEC mode:0
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0x29, 0x1e, // 1/2 threshold
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0x2a, 0x14, // 2/3 threshold
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0x2b, 0x0f, // 3/4 threshold
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0x2c, 0x09, // 5/6 threshold
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0x2d, 0x05, // 7/8 threshold
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0x2e, 0x01,
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0x31, 0x1f, // test all FECs
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0x32, 0x19, // viterbi and synchro search
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0x33, 0xfc, // rs control
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0x34, 0x93, // error control
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0x0f, 0x52,
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0xff, 0xff
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};
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static int alps_bsru6_set_symbol_rate(struct dvb_frontend* fe, u32 srate, u32 ratio)
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{
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u8 aclk = 0;
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u8 bclk = 0;
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if (srate < 1500000) { aclk = 0xb7; bclk = 0x47; }
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else if (srate < 3000000) { aclk = 0xb7; bclk = 0x4b; }
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else if (srate < 7000000) { aclk = 0xb7; bclk = 0x4f; }
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else if (srate < 14000000) { aclk = 0xb7; bclk = 0x53; }
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else if (srate < 30000000) { aclk = 0xb6; bclk = 0x53; }
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else if (srate < 45000000) { aclk = 0xb4; bclk = 0x51; }
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stv0299_writereg(fe, 0x13, aclk);
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stv0299_writereg(fe, 0x14, bclk);
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stv0299_writereg(fe, 0x1f, (ratio >> 16) & 0xff);
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stv0299_writereg(fe, 0x20, (ratio >> 8) & 0xff);
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stv0299_writereg(fe, 0x21, (ratio ) & 0xf0);
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return 0;
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}
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static int alps_bsru6_pll_set(struct dvb_frontend* fe, struct i2c_adapter *i2c, struct dvb_frontend_parameters* params)
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{
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int ret;
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u8 data[4];
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u32 div;
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struct i2c_msg msg = { .addr = 0x61, .flags = 0, .buf = data, .len = sizeof(data) };
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if ((params->frequency < 950000) || (params->frequency > 2150000))
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return -EINVAL;
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div = (params->frequency + (125 - 1)) / 125; // round correctly
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data[0] = (div >> 8) & 0x7f;
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data[1] = div & 0xff;
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data[2] = 0x80 | ((div & 0x18000) >> 10) | 4;
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data[3] = 0xC4;
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if (params->frequency > 1530000) data[3] = 0xc0;
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ret = i2c_transfer(i2c, &msg, 1);
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if (ret != 1)
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return -EIO;
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return 0;
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}
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static struct stv0299_config alps_bsru6_config = {
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.demod_address = 0x68,
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.inittab = alps_bsru6_inittab,
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.mclk = 88000000UL,
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.invert = 1,
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.skip_reinit = 0,
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.lock_output = STV0229_LOCKOUTPUT_1,
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.volt13_op0_op1 = STV0299_VOLT13_OP1,
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.min_delay_ms = 100,
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.set_symbol_rate = alps_bsru6_set_symbol_rate,
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.pll_set = alps_bsru6_pll_set,
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};
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static int alps_tdbe2_pll_set(struct dvb_frontend* fe, struct dvb_frontend_parameters* params)
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{
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struct av7110* av7110 = fe->dvb->priv;
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@ -44,6 +44,7 @@
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#include "tda1004x.h"
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#include "lnbp21.h"
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#include "bsbe1.h"
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#include "bsru6.h"
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#define DEBIADDR_IR 0x1234
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#define DEBIADDR_CICONTROL 0x0000
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@ -476,123 +477,6 @@ static void budget_ci_irq(struct saa7146_dev *dev, u32 * isr)
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tasklet_schedule(&budget_ci->ciintf_irq_tasklet);
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}
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static u8 alps_bsru6_inittab[] = {
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0x01, 0x15,
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0x02, 0x00,
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0x03, 0x00,
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0x04, 0x7d, /* F22FR = 0x7d, F22 = f_VCO / 128 / 0x7d = 22 kHz */
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0x05, 0x35, /* I2CT = 0, SCLT = 1, SDAT = 1 */
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0x06, 0x40, /* DAC not used, set to high impendance mode */
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0x07, 0x00, /* DAC LSB */
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0x08, 0x40, /* DiSEqC off, LNB power on OP2/LOCK pin on */
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0x09, 0x00, /* FIFO */
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0x0c, 0x51, /* OP1 ctl = Normal, OP1 val = 1 (LNB Power ON) */
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0x0d, 0x82, /* DC offset compensation = ON, beta_agc1 = 2 */
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0x0e, 0x23, /* alpha_tmg = 2, beta_tmg = 3 */
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0x10, 0x3f, // AGC2 0x3d
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0x11, 0x84,
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0x12, 0xb9,
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0x15, 0xc9, // lock detector threshold
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0x16, 0x00,
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0x17, 0x00,
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0x18, 0x00,
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0x19, 0x00,
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0x1a, 0x00,
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0x1f, 0x50,
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0x20, 0x00,
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0x21, 0x00,
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0x22, 0x00,
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0x23, 0x00,
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0x28, 0x00, // out imp: normal out type: parallel FEC mode:0
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0x29, 0x1e, // 1/2 threshold
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0x2a, 0x14, // 2/3 threshold
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0x2b, 0x0f, // 3/4 threshold
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0x2c, 0x09, // 5/6 threshold
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0x2d, 0x05, // 7/8 threshold
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0x2e, 0x01,
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0x31, 0x1f, // test all FECs
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0x32, 0x19, // viterbi and synchro search
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0x33, 0xfc, // rs control
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0x34, 0x93, // error control
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0x0f, 0x52,
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0xff, 0xff
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};
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static int alps_bsru6_set_symbol_rate(struct dvb_frontend *fe, u32 srate, u32 ratio)
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{
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u8 aclk = 0;
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u8 bclk = 0;
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if (srate < 1500000) {
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aclk = 0xb7;
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bclk = 0x47;
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} else if (srate < 3000000) {
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aclk = 0xb7;
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bclk = 0x4b;
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} else if (srate < 7000000) {
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aclk = 0xb7;
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bclk = 0x4f;
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} else if (srate < 14000000) {
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aclk = 0xb7;
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bclk = 0x53;
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} else if (srate < 30000000) {
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aclk = 0xb6;
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bclk = 0x53;
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} else if (srate < 45000000) {
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aclk = 0xb4;
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bclk = 0x51;
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}
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stv0299_writereg(fe, 0x13, aclk);
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stv0299_writereg(fe, 0x14, bclk);
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stv0299_writereg(fe, 0x1f, (ratio >> 16) & 0xff);
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stv0299_writereg(fe, 0x20, (ratio >> 8) & 0xff);
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stv0299_writereg(fe, 0x21, (ratio) & 0xf0);
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return 0;
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}
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static int alps_bsru6_pll_set(struct dvb_frontend *fe, struct i2c_adapter *i2c, struct dvb_frontend_parameters *params)
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{
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u8 buf[4];
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u32 div;
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struct i2c_msg msg = {.addr = 0x61,.flags = 0,.buf = buf,.len = sizeof(buf) };
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if ((params->frequency < 950000) || (params->frequency > 2150000))
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return -EINVAL;
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div = (params->frequency + (125 - 1)) / 125; // round correctly
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buf[0] = (div >> 8) & 0x7f;
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buf[1] = div & 0xff;
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buf[2] = 0x80 | ((div & 0x18000) >> 10) | 4;
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buf[3] = 0xC4;
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if (params->frequency > 1530000)
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buf[3] = 0xc0;
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if (i2c_transfer(i2c, &msg, 1) != 1)
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return -EIO;
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return 0;
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}
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static struct stv0299_config alps_bsru6_config = {
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.demod_address = 0x68,
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.inittab = alps_bsru6_inittab,
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.mclk = 88000000UL,
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.invert = 1,
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.skip_reinit = 0,
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.lock_output = STV0229_LOCKOUTPUT_1,
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.volt13_op0_op1 = STV0299_VOLT13_OP1,
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.min_delay_ms = 100,
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.set_symbol_rate = alps_bsru6_set_symbol_rate,
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.pll_set = alps_bsru6_pll_set,
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};
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static u8 philips_su1278_tt_inittab[] = {
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0x01, 0x0f,
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0x02, 0x30,
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@ -37,6 +37,8 @@
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#include "ves1x93.h"
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#include "tda8083.h"
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#include "bsru6.h"
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#define budget_patch budget
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static struct saa7146_extension budget_extension;
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@ -290,103 +292,6 @@ static struct ves1x93_config alps_bsrv2_config = {
|
|||
.pll_set = alps_bsrv2_pll_set,
|
||||
};
|
||||
|
||||
static u8 alps_bsru6_inittab[] = {
|
||||
0x01, 0x15,
|
||||
0x02, 0x00,
|
||||
0x03, 0x00,
|
||||
0x04, 0x7d, /* F22FR = 0x7d, F22 = f_VCO / 128 / 0x7d = 22 kHz */
|
||||
0x05, 0x35, /* I2CT = 0, SCLT = 1, SDAT = 1 */
|
||||
0x06, 0x40, /* DAC not used, set to high impendance mode */
|
||||
0x07, 0x00, /* DAC LSB */
|
||||
0x08, 0x40, /* DiSEqC off, LNB power on OP2/LOCK pin on */
|
||||
0x09, 0x00, /* FIFO */
|
||||
0x0c, 0x51, /* OP1 ctl = Normal, OP1 val = 1 (LNB Power ON) */
|
||||
0x0d, 0x82, /* DC offset compensation = ON, beta_agc1 = 2 */
|
||||
0x0e, 0x23, /* alpha_tmg = 2, beta_tmg = 3 */
|
||||
0x10, 0x3f, // AGC2 0x3d
|
||||
0x11, 0x84,
|
||||
0x12, 0xb9,
|
||||
0x15, 0xc9, // lock detector threshold
|
||||
0x16, 0x00,
|
||||
0x17, 0x00,
|
||||
0x18, 0x00,
|
||||
0x19, 0x00,
|
||||
0x1a, 0x00,
|
||||
0x1f, 0x50,
|
||||
0x20, 0x00,
|
||||
0x21, 0x00,
|
||||
0x22, 0x00,
|
||||
0x23, 0x00,
|
||||
0x28, 0x00, // out imp: normal out type: parallel FEC mode:0
|
||||
0x29, 0x1e, // 1/2 threshold
|
||||
0x2a, 0x14, // 2/3 threshold
|
||||
0x2b, 0x0f, // 3/4 threshold
|
||||
0x2c, 0x09, // 5/6 threshold
|
||||
0x2d, 0x05, // 7/8 threshold
|
||||
0x2e, 0x01,
|
||||
0x31, 0x1f, // test all FECs
|
||||
0x32, 0x19, // viterbi and synchro search
|
||||
0x33, 0xfc, // rs control
|
||||
0x34, 0x93, // error control
|
||||
0x0f, 0x52,
|
||||
0xff, 0xff
|
||||
};
|
||||
|
||||
static int alps_bsru6_set_symbol_rate(struct dvb_frontend* fe, u32 srate, u32 ratio)
|
||||
{
|
||||
u8 aclk = 0;
|
||||
u8 bclk = 0;
|
||||
|
||||
if (srate < 1500000) { aclk = 0xb7; bclk = 0x47; }
|
||||
else if (srate < 3000000) { aclk = 0xb7; bclk = 0x4b; }
|
||||
else if (srate < 7000000) { aclk = 0xb7; bclk = 0x4f; }
|
||||
else if (srate < 14000000) { aclk = 0xb7; bclk = 0x53; }
|
||||
else if (srate < 30000000) { aclk = 0xb6; bclk = 0x53; }
|
||||
else if (srate < 45000000) { aclk = 0xb4; bclk = 0x51; }
|
||||
|
||||
stv0299_writereg (fe, 0x13, aclk);
|
||||
stv0299_writereg (fe, 0x14, bclk);
|
||||
stv0299_writereg (fe, 0x1f, (ratio >> 16) & 0xff);
|
||||
stv0299_writereg (fe, 0x20, (ratio >> 8) & 0xff);
|
||||
stv0299_writereg (fe, 0x21, (ratio ) & 0xf0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int alps_bsru6_pll_set(struct dvb_frontend* fe, struct i2c_adapter *i2c, struct dvb_frontend_parameters* params)
|
||||
{
|
||||
u8 data[4];
|
||||
u32 div;
|
||||
struct i2c_msg msg = { .addr = 0x61, .flags = 0, .buf = data, .len = sizeof(data) };
|
||||
|
||||
if ((params->frequency < 950000) || (params->frequency > 2150000)) return -EINVAL;
|
||||
|
||||
div = (params->frequency + (125 - 1)) / 125; // round correctly
|
||||
data[0] = (div >> 8) & 0x7f;
|
||||
data[1] = div & 0xff;
|
||||
data[2] = 0x80 | ((div & 0x18000) >> 10) | 4;
|
||||
data[3] = 0xC4;
|
||||
|
||||
if (params->frequency > 1530000) data[3] = 0xc0;
|
||||
|
||||
if (i2c_transfer(i2c, &msg, 1) != 1) return -EIO;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct stv0299_config alps_bsru6_config = {
|
||||
|
||||
.demod_address = 0x68,
|
||||
.inittab = alps_bsru6_inittab,
|
||||
.mclk = 88000000UL,
|
||||
.invert = 1,
|
||||
.skip_reinit = 0,
|
||||
.lock_output = STV0229_LOCKOUTPUT_1,
|
||||
.volt13_op0_op1 = STV0299_VOLT13_OP1,
|
||||
.min_delay_ms = 100,
|
||||
.set_symbol_rate = alps_bsru6_set_symbol_rate,
|
||||
.pll_set = alps_bsru6_pll_set,
|
||||
};
|
||||
|
||||
static int grundig_29504_451_pll_set(struct dvb_frontend* fe, struct dvb_frontend_parameters* params)
|
||||
{
|
||||
struct budget_patch* budget = (struct budget_patch*) fe->dvb->priv;
|
||||
|
|
|
|||
|
|
@ -42,6 +42,7 @@
|
|||
#include "tda8083.h"
|
||||
#include "s5h1420.h"
|
||||
#include "lnbp21.h"
|
||||
#include "bsru6.h"
|
||||
|
||||
static void Set22K (struct budget *budget, int state)
|
||||
{
|
||||
|
|
@ -220,103 +221,6 @@ static struct ves1x93_config alps_bsrv2_config =
|
|||
.pll_set = alps_bsrv2_pll_set,
|
||||
};
|
||||
|
||||
static u8 alps_bsru6_inittab[] = {
|
||||
0x01, 0x15,
|
||||
0x02, 0x00,
|
||||
0x03, 0x00,
|
||||
0x04, 0x7d, /* F22FR = 0x7d, F22 = f_VCO / 128 / 0x7d = 22 kHz */
|
||||
0x05, 0x35, /* I2CT = 0, SCLT = 1, SDAT = 1 */
|
||||
0x06, 0x40, /* DAC not used, set to high impendance mode */
|
||||
0x07, 0x00, /* DAC LSB */
|
||||
0x08, 0x40, /* DiSEqC off, LNB power on OP2/LOCK pin on */
|
||||
0x09, 0x00, /* FIFO */
|
||||
0x0c, 0x51, /* OP1 ctl = Normal, OP1 val = 1 (LNB Power ON) */
|
||||
0x0d, 0x82, /* DC offset compensation = ON, beta_agc1 = 2 */
|
||||
0x0e, 0x23, /* alpha_tmg = 2, beta_tmg = 3 */
|
||||
0x10, 0x3f, // AGC2 0x3d
|
||||
0x11, 0x84,
|
||||
0x12, 0xb9,
|
||||
0x15, 0xc9, // lock detector threshold
|
||||
0x16, 0x00,
|
||||
0x17, 0x00,
|
||||
0x18, 0x00,
|
||||
0x19, 0x00,
|
||||
0x1a, 0x00,
|
||||
0x1f, 0x50,
|
||||
0x20, 0x00,
|
||||
0x21, 0x00,
|
||||
0x22, 0x00,
|
||||
0x23, 0x00,
|
||||
0x28, 0x00, // out imp: normal out type: parallel FEC mode:0
|
||||
0x29, 0x1e, // 1/2 threshold
|
||||
0x2a, 0x14, // 2/3 threshold
|
||||
0x2b, 0x0f, // 3/4 threshold
|
||||
0x2c, 0x09, // 5/6 threshold
|
||||
0x2d, 0x05, // 7/8 threshold
|
||||
0x2e, 0x01,
|
||||
0x31, 0x1f, // test all FECs
|
||||
0x32, 0x19, // viterbi and synchro search
|
||||
0x33, 0xfc, // rs control
|
||||
0x34, 0x93, // error control
|
||||
0x0f, 0x52,
|
||||
0xff, 0xff
|
||||
};
|
||||
|
||||
static int alps_bsru6_set_symbol_rate(struct dvb_frontend* fe, u32 srate, u32 ratio)
|
||||
{
|
||||
u8 aclk = 0;
|
||||
u8 bclk = 0;
|
||||
|
||||
if (srate < 1500000) { aclk = 0xb7; bclk = 0x47; }
|
||||
else if (srate < 3000000) { aclk = 0xb7; bclk = 0x4b; }
|
||||
else if (srate < 7000000) { aclk = 0xb7; bclk = 0x4f; }
|
||||
else if (srate < 14000000) { aclk = 0xb7; bclk = 0x53; }
|
||||
else if (srate < 30000000) { aclk = 0xb6; bclk = 0x53; }
|
||||
else if (srate < 45000000) { aclk = 0xb4; bclk = 0x51; }
|
||||
|
||||
stv0299_writereg (fe, 0x13, aclk);
|
||||
stv0299_writereg (fe, 0x14, bclk);
|
||||
stv0299_writereg (fe, 0x1f, (ratio >> 16) & 0xff);
|
||||
stv0299_writereg (fe, 0x20, (ratio >> 8) & 0xff);
|
||||
stv0299_writereg (fe, 0x21, (ratio ) & 0xf0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int alps_bsru6_pll_set(struct dvb_frontend* fe, struct i2c_adapter *i2c, struct dvb_frontend_parameters* params)
|
||||
{
|
||||
u8 data[4];
|
||||
u32 div;
|
||||
struct i2c_msg msg = { .addr = 0x61, .flags = 0, .buf = data, .len = sizeof(data) };
|
||||
|
||||
if ((params->frequency < 950000) || (params->frequency > 2150000)) return -EINVAL;
|
||||
|
||||
div = (params->frequency + (125 - 1)) / 125; // round correctly
|
||||
data[0] = (div >> 8) & 0x7f;
|
||||
data[1] = div & 0xff;
|
||||
data[2] = 0x80 | ((div & 0x18000) >> 10) | 4;
|
||||
data[3] = 0xC4;
|
||||
|
||||
if (params->frequency > 1530000) data[3] = 0xc0;
|
||||
|
||||
if (i2c_transfer(i2c, &msg, 1) != 1) return -EIO;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct stv0299_config alps_bsru6_config = {
|
||||
|
||||
.demod_address = 0x68,
|
||||
.inittab = alps_bsru6_inittab,
|
||||
.mclk = 88000000UL,
|
||||
.invert = 1,
|
||||
.skip_reinit = 0,
|
||||
.lock_output = STV0229_LOCKOUTPUT_1,
|
||||
.volt13_op0_op1 = STV0299_VOLT13_OP1,
|
||||
.min_delay_ms = 100,
|
||||
.set_symbol_rate = alps_bsru6_set_symbol_rate,
|
||||
.pll_set = alps_bsru6_pll_set,
|
||||
};
|
||||
|
||||
static int alps_tdbe2_pll_set(struct dvb_frontend* fe, struct dvb_frontend_parameters* params)
|
||||
{
|
||||
struct budget* budget = (struct budget*) fe->dvb->priv;
|
||||
|
|
|
|||
Loading…
Reference in a new issue