hpt366: merge HPT37x speedproc handlers
Continue with the driver rewrite:
- move the interrupt twiddling code from the speedproc handlers into the
init_hwif_hpt366 which allows to merge the two HPT37x speedproc handlers
into one;
- get rid of in init_hpt366 which solely consists of the duplicate code, then
fold init_hpt37x() into init_chipset_hpt366();
- fix hpt3xx_tune_drive() to always set the PIO mode requested, not the best
possible one, change hpt366_config_drive_xfer_rate() accordingly, simplify
it a bit;
- group all the DMA related code together init_hwif_hpt366(), and generally
clean up and beautify it.
Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
This commit is contained in:
Sergei Shtylyov
Bartlomiej Zolnierkiewicz
parent
abc4ad4c6b
commit
26ccb802ee
1 changed files with 88 additions and 170 deletions
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@ -1,5 +1,5 @@
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/*
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* linux/drivers/ide/pci/hpt366.c Version 0.50 May 28, 2006
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* linux/drivers/ide/pci/hpt366.c Version 0.51 Jun 04, 2006
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*
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* Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
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* Portions Copyright (C) 2001 Sun Microsystems, Inc.
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@ -83,13 +83,16 @@
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* - cache the channel's MCRs' offset; only touch the relevant MCR when detecting
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* the cable type on HPT374's function 1
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* - rename all the register related variables consistently
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* - make HPT36x's speedproc handler look the same way as HPT37x ones; fix the
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* PIO timing register mask for HPT37x
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* - move the interrupt twiddling code from the speedproc handlers into the
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* init_hwif handler, also grouping all the DMA related code together there;
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* simplify the init_chipset handler
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* - merge two HPT37x speedproc handlers and fix the PIO timing register mask
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* there; make HPT36x speedproc handler look the same way as the HPT37x one
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* - fix the tuneproc handler to always set the PIO mode requested, not the
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* best possible one
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* <source@mvista.com>
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*
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*/
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#include <linux/types.h>
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#include <linux/module.h>
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#include <linux/kernel.h>
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@ -507,19 +510,9 @@ static int hpt36x_tune_chipset(ide_drive_t *drive, u8 xferspeed)
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struct hpt_info *info = ide_get_hwifdata (hwif);
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u8 speed = hpt3xx_ratefilter(drive, xferspeed);
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u8 itr_addr = drive->dn ? 0x44 : 0x40;
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u8 mcr_addr = hwif->select_data + 1;
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u8 mcr = 0;
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u32 new_itr, old_itr = 0;
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u32 itr_mask = (speed < XFER_MW_DMA_0) ? 0x30070000 : 0xc0000000;
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/*
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* Disable the "fast interrupt" prediction.
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*/
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pci_read_config_byte(dev, mcr_addr, &mcr);
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if (mcr & 0x80)
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pci_write_config_byte(dev, mcr_addr, mcr & ~0x80);
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new_itr = pci_bus_clock_list(speed, info->speed);
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u32 new_itr = pci_bus_clock_list(speed, info->speed);
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u32 old_itr = 0;
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/*
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* Disable on-chip PIO FIFO/buffer (and PIO MST mode as well)
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@ -534,38 +527,16 @@ static int hpt36x_tune_chipset(ide_drive_t *drive, u8 xferspeed)
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return ide_config_drive_speed(drive, speed);
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}
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static int hpt370_tune_chipset(ide_drive_t *drive, u8 xferspeed)
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static int hpt37x_tune_chipset(ide_drive_t *drive, u8 xferspeed)
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{
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ide_hwif_t *hwif = HWIF(drive);
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struct pci_dev *dev = hwif->pci_dev;
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struct hpt_info *info = ide_get_hwifdata (hwif);
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u8 speed = hpt3xx_ratefilter(drive, xferspeed);
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u8 mcr_addr = hwif->select_data + 1;
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u8 itr_addr = 0x40 + (drive->dn * 4);
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u8 new_mcr = 0, old_mcr = 0;
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u32 new_itr, old_itr = 0;
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u32 itr_mask = (speed < XFER_MW_DMA_0) ? 0x303c0000 : 0xc0000000;
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/*
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* Disable the "fast interrupt" prediction.
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* don't holdoff on interrupts. (== 0x01 despite what the docs say)
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*/
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pci_read_config_byte(dev, mcr_addr, &old_mcr);
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new_mcr = old_mcr;
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if (new_mcr & 0x02)
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new_mcr &= ~0x02;
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#ifdef HPT_DELAY_INTERRUPT
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if (new_mcr & 0x01)
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new_mcr &= ~0x01;
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#else
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if ((new_mcr & 0x01) == 0)
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new_mcr |= 0x01;
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#endif
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if (new_mcr != old_mcr)
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pci_write_config_byte(dev, mcr_addr, new_mcr);
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new_itr = pci_bus_clock_list(speed, info->speed);
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u32 new_itr = pci_bus_clock_list(speed, info->speed);
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u32 old_itr = 0;
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pci_read_config_dword(dev, itr_addr, &old_itr);
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new_itr = (new_itr & ~itr_mask) | (old_itr & itr_mask);
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@ -577,71 +548,34 @@ static int hpt370_tune_chipset(ide_drive_t *drive, u8 xferspeed)
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return ide_config_drive_speed(drive, speed);
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}
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static int hpt372_tune_chipset(ide_drive_t *drive, u8 xferspeed)
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static int hpt3xx_tune_chipset(ide_drive_t *drive, u8 speed)
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{
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ide_hwif_t *hwif = HWIF(drive);
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struct pci_dev *dev = hwif->pci_dev;
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struct hpt_info *info = ide_get_hwifdata (hwif);
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u8 speed = hpt3xx_ratefilter(drive, xferspeed);
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u8 mcr_addr = hwif->select_data + 1;
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u8 itr_addr = 0x40 + (drive->dn * 4);
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u8 mcr = 0;
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u32 new_itr, old_itr = 0;
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u32 itr_mask = (speed < XFER_MW_DMA_0) ? 0x303c0000 : 0xc0000000;
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/*
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* Disable the "fast interrupt" prediction.
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* don't holdoff on interrupts. (== 0x01 despite what the docs say)
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*/
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pci_read_config_byte (dev, mcr_addr, &mcr);
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pci_write_config_byte(dev, mcr_addr, (mcr & ~0x07));
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new_itr = pci_bus_clock_list(speed, info->speed);
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pci_read_config_dword(dev, itr_addr, &old_itr);
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new_itr = (new_itr & ~itr_mask) | (old_itr & itr_mask);
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if (speed < XFER_MW_DMA_0)
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new_itr &= ~0x80000000; /* Disable on-chip PIO FIFO/buffer */
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pci_write_config_dword(dev, itr_addr, new_itr);
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return ide_config_drive_speed(drive, speed);
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}
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static int hpt3xx_tune_chipset (ide_drive_t *drive, u8 speed)
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{
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ide_hwif_t *hwif = drive->hwif;
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struct hpt_info *info = ide_get_hwifdata(hwif);
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if (info->revision >= 8)
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return hpt372_tune_chipset(drive, speed); /* not a typo */
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else if (info->revision >= 5)
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return hpt372_tune_chipset(drive, speed);
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else if (info->revision >= 3)
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return hpt370_tune_chipset(drive, speed);
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if (info->revision >= 3)
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return hpt37x_tune_chipset(drive, speed);
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else /* hpt368: hpt_minimum_revision(dev, 2) */
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return hpt36x_tune_chipset(drive, speed);
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}
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static void hpt3xx_tune_drive (ide_drive_t *drive, u8 pio)
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static void hpt3xx_tune_drive(ide_drive_t *drive, u8 pio)
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{
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pio = ide_get_best_pio_mode(drive, 255, pio, NULL);
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(void) hpt3xx_tune_chipset(drive, (XFER_PIO_0 + pio));
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pio = ide_get_best_pio_mode(drive, pio, 4, NULL);
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(void) hpt3xx_tune_chipset (drive, XFER_PIO_0 + pio);
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}
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/*
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* This allows the configuration of ide_pci chipset registers
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* for cards that learn about the drive's UDMA, DMA, PIO capabilities
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* after the drive is reported by the OS. Initially for designed for
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* after the drive is reported by the OS. Initially designed for
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* HPT366 UDMA chipset by HighPoint|Triones Technologies, Inc.
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*
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* check_in_drive_lists(drive, bad_ata66_4)
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* check_in_drive_lists(drive, bad_ata66_3)
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* check_in_drive_lists(drive, bad_ata33)
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*
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*/
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static int config_chipset_for_dma (ide_drive_t *drive)
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static int config_chipset_for_dma(ide_drive_t *drive)
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{
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u8 speed = ide_dma_speed(drive, hpt3xx_ratemask(drive));
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ide_hwif_t *hwif = drive->hwif;
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ide_hwif_t *hwif = HWIF(drive);
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struct hpt_info *info = ide_get_hwifdata(hwif);
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if (!speed)
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@ -666,7 +600,7 @@ static int hpt3xx_quirkproc(ide_drive_t *drive)
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return 0;
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}
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static void hpt3xx_intrproc (ide_drive_t *drive)
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static void hpt3xx_intrproc(ide_drive_t *drive)
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{
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ide_hwif_t *hwif = HWIF(drive);
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@ -676,7 +610,7 @@ static void hpt3xx_intrproc (ide_drive_t *drive)
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hwif->OUTB(drive->ctl | 2, IDE_CONTROL_REG);
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}
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static void hpt3xx_maskproc (ide_drive_t *drive, int mask)
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static void hpt3xx_maskproc(ide_drive_t *drive, int mask)
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{
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ide_hwif_t *hwif = HWIF(drive);
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struct pci_dev *dev = hwif->pci_dev;
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@ -705,25 +639,22 @@ static void hpt3xx_maskproc (ide_drive_t *drive, int mask)
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IDE_CONTROL_REG);
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}
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static int hpt366_config_drive_xfer_rate (ide_drive_t *drive)
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static int hpt366_config_drive_xfer_rate(ide_drive_t *drive)
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{
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ide_hwif_t *hwif = drive->hwif;
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ide_hwif_t *hwif = HWIF(drive);
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struct hd_driveid *id = drive->id;
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drive->init_speed = 0;
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if ((id->capability & 1) && drive->autodma) {
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if (ide_use_dma(drive)) {
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if (config_chipset_for_dma(drive))
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if (ide_use_dma(drive) && config_chipset_for_dma(drive))
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return hwif->ide_dma_on(drive);
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}
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goto fast_ata_pio;
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} else if ((id->capability & 8) || (id->field_valid & 2)) {
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fast_ata_pio:
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hpt3xx_tune_drive(drive, 5);
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hpt3xx_tune_drive(drive, 255);
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return hwif->ide_dma_off_quietly(drive);
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}
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/* IORDY not supported */
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@ -1154,34 +1085,8 @@ init_hpt37X_done:
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udelay(100);
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}
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static int __devinit init_hpt37x(struct pci_dev *dev)
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{
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u8 scr1;
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pci_read_config_byte (dev, 0x5a, &scr1);
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/* interrupt force enable */
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pci_write_config_byte(dev, 0x5a, (scr1 & ~0x10));
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return 0;
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}
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static int __devinit init_hpt366(struct pci_dev *dev)
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{
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u8 mcr = 0;
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/*
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* Disable the "fast interrupt" prediction.
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*/
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pci_read_config_byte(dev, 0x51, &mcr);
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if (mcr & 0x80)
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pci_write_config_byte(dev, 0x51, mcr & ~0x80);
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return 0;
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}
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static unsigned int __devinit init_chipset_hpt366(struct pci_dev *dev, const char *name)
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{
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int ret = 0;
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/*
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* FIXME: Not portable. Also, why do we enable the ROM in the first place?
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* We don't seem to be using it.
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@ -1195,13 +1100,14 @@ static unsigned int __devinit init_chipset_hpt366(struct pci_dev *dev, const cha
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pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
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pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
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if (hpt_revision(dev) >= 3)
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ret = init_hpt37x(dev);
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else
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ret = init_hpt366(dev);
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if (hpt_revision(dev) >= 3) {
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u8 scr1 = 0;
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if (ret)
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return ret;
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/* Interrupt force enable. */
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pci_read_config_byte(dev, 0x5a, &scr1);
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if (scr1 & 0x10)
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pci_write_config_byte(dev, 0x5a, scr1 & ~0x10);
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}
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return dev->irq;
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}
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@ -1212,6 +1118,7 @@ static void __devinit init_hwif_hpt366(ide_hwif_t *hwif)
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struct hpt_info *info = ide_get_hwifdata(hwif);
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int serialize = HPT_SERIALIZE_IO;
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u8 scr1 = 0, ata66 = (hwif->channel) ? 0x01 : 0x02;
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u8 new_mcr, old_mcr = 0;
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/* Cache the channel's MISC. control registers' offset */
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hwif->select_data = hwif->channel ? 0x54 : 0x50;
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@ -1238,6 +1145,41 @@ static void __devinit init_hwif_hpt366(ide_hwif_t *hwif)
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hwif->rw_disk = &hpt3xxn_rw_disk;
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}
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/* Serialize access to this device if needed */
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if (serialize && hwif->mate)
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hwif->serialized = hwif->mate->serialized = 1;
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/*
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* Disable the "fast interrupt" prediction. Don't hold off
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* on interrupts. (== 0x01 despite what the docs say)
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*/
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pci_read_config_byte(dev, hwif->select_data + 1, &old_mcr);
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if (info->revision >= 5) /* HPT372 and newer */
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new_mcr = old_mcr & ~0x07;
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else if (info->revision >= 3) { /* HPT370 and HPT370A */
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new_mcr = old_mcr;
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new_mcr &= ~0x02;
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#ifdef HPT_DELAY_INTERRUPT
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new_mcr &= ~0x01;
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#else
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new_mcr |= 0x01;
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#endif
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} else /* HPT366 and HPT368 */
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new_mcr = old_mcr & ~0x80;
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if (new_mcr != old_mcr)
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pci_write_config_byte(dev, hwif->select_data + 1, new_mcr);
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if (!hwif->dma_base) {
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hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
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return;
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}
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hwif->ultra_mask = 0x7f;
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hwif->mwdma_mask = 0x07;
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/*
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* The HPT37x uses the CBLID pins as outputs for MA15/MA16
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* address lines to access an external EEPROM. To read valid
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@ -1272,33 +1214,12 @@ static void __devinit init_hwif_hpt366(ide_hwif_t *hwif)
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} else
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pci_read_config_byte (dev, 0x5a, &scr1);
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/* Serialize access to this device */
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if (serialize && hwif->mate)
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hwif->serialized = hwif->mate->serialized = 1;
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if (!hwif->udma_four)
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hwif->udma_four = (scr1 & ata66) ? 0 : 1;
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/*
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* Set up ioctl for power status.
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* NOTE: power affects both drives on each channel.
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*/
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hwif->busproc = &hpt3xx_busproc;
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if (!hwif->dma_base) {
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hwif->drives[0].autotune = 1;
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hwif->drives[1].autotune = 1;
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return;
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}
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hwif->ultra_mask = 0x7f;
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hwif->mwdma_mask = 0x07;
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if (!(hwif->udma_four))
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hwif->udma_four = ((scr1 & ata66) ? 0 : 1);
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hwif->ide_dma_check = &hpt366_config_drive_xfer_rate;
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if (info->revision >= 8) {
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hwif->ide_dma_test_irq = &hpt374_ide_dma_test_irq;
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hwif->ide_dma_end = &hpt374_ide_dma_end;
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} else if (info->revision >= 5) {
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if (info->revision >= 5) {
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hwif->ide_dma_test_irq = &hpt374_ide_dma_test_irq;
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hwif->ide_dma_end = &hpt374_ide_dma_end;
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} else if (info->revision >= 3) {
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@ -1306,15 +1227,12 @@ static void __devinit init_hwif_hpt366(ide_hwif_t *hwif)
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hwif->ide_dma_end = &hpt370_ide_dma_end;
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hwif->ide_dma_timeout = &hpt370_ide_dma_timeout;
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hwif->ide_dma_lostirq = &hpt370_ide_dma_lostirq;
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} else if (info->revision >= 2)
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hwif->ide_dma_lostirq = &hpt366_ide_dma_lostirq;
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else
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} else
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hwif->ide_dma_lostirq = &hpt366_ide_dma_lostirq;
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if (!noautodma)
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hwif->autodma = 1;
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hwif->drives[0].autodma = hwif->autodma;
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hwif->drives[1].autodma = hwif->autodma;
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hwif->drives[0].autodma = hwif->drives[1].autodma = hwif->autodma;
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}
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static void __devinit init_dma_hpt366(ide_hwif_t *hwif, unsigned long dmabase)
|
||||
|
|
@ -1334,7 +1252,7 @@ static void __devinit init_dma_hpt366(ide_hwif_t *hwif, unsigned long dmabase)
|
|||
return;
|
||||
}
|
||||
|
||||
dma_old = hwif->INB(dmabase+2);
|
||||
dma_old = hwif->INB(dmabase + 2);
|
||||
|
||||
local_irq_save(flags);
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue