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[ARM] 4764/1: [AT91] AT91CAP9 core support

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Add support for Atmel's AT91CAP9 Customizable Microcontroller family.
  <http://www.atmel.com/products/AT91CAP/Default.asp>

Signed-off-by: Stelian Pop <stelian@popies.net>
Signed-off-by: Andrew Victor <linux@maxim.org.za>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Andrew Victor 2008-01-24 15:10:39 +01:00 committed by Russell King
parent da7a42d60b
commit 2b3b3516b6
24 changed files with 1735 additions and 15 deletions
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4
arch/arm/Kconfig
View file

@ -180,8 +180,8 @@ config ARCH_AT91
bool "Atmel AT91"
select GENERIC_GPIO
help
This enables support for systems based on the Atmel AT91RM9200
and AT91SAM9xxx processors.
This enables support for systems based on the Atmel AT91RM9200,
AT91SAM9 and AT91CAP9 processors.
config ARCH_CLPS7500
bool "Cirrus CL-PS7500FE"

3
arch/arm/mach-at91/Kconfig
View file

@ -22,6 +22,9 @@ config ARCH_AT91SAM9263
config ARCH_AT91SAM9RL
bool "AT91SAM9RL"
config ARCH_AT91CAP9
bool "AT91CAP9"
config ARCH_AT91X40
bool "AT91x40"

1
arch/arm/mach-at91/Makefile
View file

@ -15,6 +15,7 @@ obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260.o at91sam926x_time.o at91sam9260_d
obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o
obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263.o at91sam926x_time.o at91sam9263_devices.o
obj-$(CONFIG_ARCH_AT91SAM9RL) += at91sam9rl.o at91sam926x_time.o at91sam9rl_devices.o
obj-$(CONFIG_ARCH_AT91CAP9) += at91cap9.o at91sam926x_time.o at91cap9_devices.o
obj-$(CONFIG_ARCH_AT91X40) += at91x40.o at91x40_time.o
# AT91RM9200 board-specific support

7
arch/arm/mach-at91/Makefile.boot
View file

@ -3,7 +3,12 @@
# PARAMS_PHYS must be within 4MB of ZRELADDR
# INITRD_PHYS must be in RAM
ifeq ($(CONFIG_ARCH_AT91CAP9),y)
zreladdr-y := 0x70008000
params_phys-y := 0x70000100
initrd_phys-y := 0x70410000
else
zreladdr-y := 0x20008000
params_phys-y := 0x20000100
initrd_phys-y := 0x20410000
endif

365
arch/arm/mach-at91/at91cap9.c Normal file
View file

@ -0,0 +1,365 @@
/*
* arch/arm/mach-at91/at91cap9.c
*
* Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com>
* Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com>
* Copyright (C) 2007 Atmel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
*/
#include <linux/module.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/arch/at91cap9.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/at91_rstc.h>
#include "generic.h"
#include "clock.h"
static struct map_desc at91cap9_io_desc[] __initdata = {
{
.virtual = AT91_VA_BASE_SYS,
.pfn = __phys_to_pfn(AT91_BASE_SYS),
.length = SZ_16K,
.type = MT_DEVICE,
}, {
.virtual = AT91_IO_VIRT_BASE - AT91CAP9_SRAM_SIZE,
.pfn = __phys_to_pfn(AT91CAP9_SRAM_BASE),
.length = AT91CAP9_SRAM_SIZE,
.type = MT_DEVICE,
},
};
/* --------------------------------------------------------------------
* Clocks
* -------------------------------------------------------------------- */
/*
* The peripheral clocks.
*/
static struct clk pioABCD_clk = {
.name = "pioABCD_clk",
.pmc_mask = 1 << AT91CAP9_ID_PIOABCD,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk mpb0_clk = {
.name = "mpb0_clk",
.pmc_mask = 1 << AT91CAP9_ID_MPB0,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk mpb1_clk = {
.name = "mpb1_clk",
.pmc_mask = 1 << AT91CAP9_ID_MPB1,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk mpb2_clk = {
.name = "mpb2_clk",
.pmc_mask = 1 << AT91CAP9_ID_MPB2,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk mpb3_clk = {
.name = "mpb3_clk",
.pmc_mask = 1 << AT91CAP9_ID_MPB3,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk mpb4_clk = {
.name = "mpb4_clk",
.pmc_mask = 1 << AT91CAP9_ID_MPB4,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk usart0_clk = {
.name = "usart0_clk",
.pmc_mask = 1 << AT91CAP9_ID_US0,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk usart1_clk = {
.name = "usart1_clk",
.pmc_mask = 1 << AT91CAP9_ID_US1,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk usart2_clk = {
.name = "usart2_clk",
.pmc_mask = 1 << AT91CAP9_ID_US2,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk mmc0_clk = {
.name = "mci0_clk",
.pmc_mask = 1 << AT91CAP9_ID_MCI0,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk mmc1_clk = {
.name = "mci1_clk",
.pmc_mask = 1 << AT91CAP9_ID_MCI1,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk can_clk = {
.name = "can_clk",
.pmc_mask = 1 << AT91CAP9_ID_CAN,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk twi_clk = {
.name = "twi_clk",
.pmc_mask = 1 << AT91CAP9_ID_TWI,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk spi0_clk = {
.name = "spi0_clk",
.pmc_mask = 1 << AT91CAP9_ID_SPI0,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk spi1_clk = {
.name = "spi1_clk",
.pmc_mask = 1 << AT91CAP9_ID_SPI1,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk ssc0_clk = {
.name = "ssc0_clk",
.pmc_mask = 1 << AT91CAP9_ID_SSC0,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk ssc1_clk = {
.name = "ssc1_clk",
.pmc_mask = 1 << AT91CAP9_ID_SSC1,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk ac97_clk = {
.name = "ac97_clk",
.pmc_mask = 1 << AT91CAP9_ID_AC97C,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk tcb_clk = {
.name = "tcb_clk",
.pmc_mask = 1 << AT91CAP9_ID_TCB,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk pwmc_clk = {
.name = "pwmc_clk",
.pmc_mask = 1 << AT91CAP9_ID_PWMC,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk macb_clk = {
.name = "macb_clk",
.pmc_mask = 1 << AT91CAP9_ID_EMAC,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk aestdes_clk = {
.name = "aestdes_clk",
.pmc_mask = 1 << AT91CAP9_ID_AESTDES,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk adc_clk = {
.name = "adc_clk",
.pmc_mask = 1 << AT91CAP9_ID_ADC,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk isi_clk = {
.name = "isi_clk",
.pmc_mask = 1 << AT91CAP9_ID_ISI,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk lcdc_clk = {
.name = "lcdc_clk",
.pmc_mask = 1 << AT91CAP9_ID_LCDC,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk dma_clk = {
.name = "dma_clk",
.pmc_mask = 1 << AT91CAP9_ID_DMA,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk udphs_clk = {
.name = "udphs_clk",
.pmc_mask = 1 << AT91CAP9_ID_UDPHS,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk ohci_clk = {
.name = "ohci_clk",
.pmc_mask = 1 << AT91CAP9_ID_UHP,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk *periph_clocks[] __initdata = {
&pioABCD_clk,
&mpb0_clk,
&mpb1_clk,
&mpb2_clk,
&mpb3_clk,
&mpb4_clk,
&usart0_clk,
&usart1_clk,
&usart2_clk,
&mmc0_clk,
&mmc1_clk,
&can_clk,
&twi_clk,
&spi0_clk,
&spi1_clk,
&ssc0_clk,
&ssc1_clk,
&ac97_clk,
&tcb_clk,
&pwmc_clk,
&macb_clk,
&aestdes_clk,
&adc_clk,
&isi_clk,
&lcdc_clk,
&dma_clk,
&udphs_clk,
&ohci_clk,
// irq0 .. irq1
};
/*
* The four programmable clocks.
* You must configure pin multiplexing to bring these signals out.
*/
static struct clk pck0 = {
.name = "pck0",
.pmc_mask = AT91_PMC_PCK0,
.type = CLK_TYPE_PROGRAMMABLE,
.id = 0,
};
static struct clk pck1 = {
.name = "pck1",
.pmc_mask = AT91_PMC_PCK1,
.type = CLK_TYPE_PROGRAMMABLE,
.id = 1,
};
static struct clk pck2 = {
.name = "pck2",
.pmc_mask = AT91_PMC_PCK2,
.type = CLK_TYPE_PROGRAMMABLE,
.id = 2,
};
static struct clk pck3 = {
.name = "pck3",
.pmc_mask = AT91_PMC_PCK3,
.type = CLK_TYPE_PROGRAMMABLE,
.id = 3,
};
static void __init at91cap9_register_clocks(void)
{
int i;
for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
clk_register(periph_clocks[i]);
clk_register(&pck0);
clk_register(&pck1);
clk_register(&pck2);
clk_register(&pck3);
}
/* --------------------------------------------------------------------
* GPIO
* -------------------------------------------------------------------- */
static struct at91_gpio_bank at91cap9_gpio[] = {
{
.id = AT91CAP9_ID_PIOABCD,
.offset = AT91_PIOA,
.clock = &pioABCD_clk,
}, {
.id = AT91CAP9_ID_PIOABCD,
.offset = AT91_PIOB,
.clock = &pioABCD_clk,
}, {
.id = AT91CAP9_ID_PIOABCD,
.offset = AT91_PIOC,
.clock = &pioABCD_clk,
}, {
.id = AT91CAP9_ID_PIOABCD,
.offset = AT91_PIOD,
.clock = &pioABCD_clk,
}
};
static void at91cap9_reset(void)
{
at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
}
/* --------------------------------------------------------------------
* AT91CAP9 processor initialization
* -------------------------------------------------------------------- */
void __init at91cap9_initialize(unsigned long main_clock)
{
/* Map peripherals */
iotable_init(at91cap9_io_desc, ARRAY_SIZE(at91cap9_io_desc));
at91_arch_reset = at91cap9_reset;
at91_extern_irq = (1 << AT91CAP9_ID_IRQ0) | (1 << AT91CAP9_ID_IRQ1);
/* Init clock subsystem */
at91_clock_init(main_clock);
/* Register the processor-specific clocks */
at91cap9_register_clocks();
/* Register GPIO subsystem */
at91_gpio_init(at91cap9_gpio, 4);
}
/* --------------------------------------------------------------------
* Interrupt initialization
* -------------------------------------------------------------------- */
/*
* The default interrupt priority levels (0 = lowest, 7 = highest).
*/
static unsigned int at91cap9_default_irq_priority[NR_AIC_IRQS] __initdata = {
7, /* Advanced Interrupt Controller (FIQ) */
7, /* System Peripherals */
1, /* Parallel IO Controller A, B, C and D */
0, /* MP Block Peripheral 0 */
0, /* MP Block Peripheral 1 */
0, /* MP Block Peripheral 2 */
0, /* MP Block Peripheral 3 */
0, /* MP Block Peripheral 4 */
5, /* USART 0 */
5, /* USART 1 */
5, /* USART 2 */
0, /* Multimedia Card Interface 0 */
0, /* Multimedia Card Interface 1 */
3, /* CAN */
6, /* Two-Wire Interface */
5, /* Serial Peripheral Interface 0 */
5, /* Serial Peripheral Interface 1 */
4, /* Serial Synchronous Controller 0 */
4, /* Serial Synchronous Controller 1 */
5, /* AC97 Controller */
0, /* Timer Counter 0, 1 and 2 */
0, /* Pulse Width Modulation Controller */
3, /* Ethernet */
0, /* Advanced Encryption Standard, Triple DES*/
0, /* Analog-to-Digital Converter */
0, /* Image Sensor Interface */
3, /* LCD Controller */
0, /* DMA Controller */
2, /* USB Device Port */
2, /* USB Host port */
0, /* Advanced Interrupt Controller (IRQ0) */
0, /* Advanced Interrupt Controller (IRQ1) */
};
void __init at91cap9_init_interrupts(unsigned int priority[NR_AIC_IRQS])
{
if (!priority)
priority = at91cap9_default_irq_priority;
/* Initialize the AIC interrupt controller */
at91_aic_init(priority);
/* Enable GPIO interrupts */
at91_gpio_irq_setup();
}

1066
arch/arm/mach-at91/at91cap9_devices.c Normal file
View file

File diff suppressed because it is too large Load diff

2
arch/arm/mach-at91/clock.c
View file

@ -574,6 +574,8 @@ int __init at91_clock_init(unsigned long main_clock)
} else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() || cpu_is_at91sam9263()) {
uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
udpck.pmc_mask = AT91SAM926x_PMC_UDP;
} else if (cpu_is_at91cap9()) {
uhpck.pmc_mask = AT91CAP9_PMC_UHP;
}
at91_sys_write(AT91_CKGR_PLLBR, 0);

2
arch/arm/mach-at91/generic.h
View file

@ -15,6 +15,7 @@ extern void __init at91sam9261_initialize(unsigned long main_clock);
extern void __init at91sam9263_initialize(unsigned long main_clock);
extern void __init at91sam9rl_initialize(unsigned long main_clock);
extern void __init at91x40_initialize(unsigned long main_clock);
extern void __init at91cap9_initialize(unsigned long main_clock);
/* Interrupts */
extern void __init at91rm9200_init_interrupts(unsigned int priority[]);
@ -23,6 +24,7 @@ extern void __init at91sam9261_init_interrupts(unsigned int priority[]);
extern void __init at91sam9263_init_interrupts(unsigned int priority[]);
extern void __init at91sam9rl_init_interrupts(unsigned int priority[]);
extern void __init at91x40_init_interrupts(unsigned int priority[]);
extern void __init at91cap9_init_interrupts(unsigned int priority[]);
extern void __init at91_aic_init(unsigned int priority[]);
/* Timer */

5
arch/arm/mach-at91/pm.c
View file

@ -80,6 +80,11 @@ static int at91_pm_verify_clocks(void)
pr_debug("AT91: PM - Suspend-to-RAM with USB still active\n");
return 0;
}
} else if (cpu_is_at91cap9()) {
if ((scsr & AT91CAP9_PMC_UHP) != 0) {
pr_debug("AT91: PM - Suspend-to-RAM with USB still active\n");
return 0;
}
}
#ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS

4
arch/arm/mm/Kconfig
View file

@ -171,8 +171,8 @@ config CPU_ARM925T
# ARM926T
config CPU_ARM926T
bool "Support ARM926T processor"
depends on ARCH_INTEGRATOR || ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || MACH_REALVIEW_EB || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || ARCH_NS9XXX || ARCH_DAVINCI
default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || ARCH_NS9XXX || ARCH_DAVINCI
depends on ARCH_INTEGRATOR || ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || MACH_REALVIEW_EB || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || ARCH_AT91CAP9 || ARCH_NS9XXX || ARCH_DAVINCI
default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || ARCH_AT91CAP9 || ARCH_NS9XXX || ARCH_DAVINCI
select CPU_32v5
select CPU_ABRT_EV5TJ
select CPU_CACHE_VIVT

2
drivers/net/Kconfig
View file

@ -212,7 +212,7 @@ config MII
config MACB
tristate "Atmel MACB support"
depends on AVR32 || ARCH_AT91SAM9260 || ARCH_AT91SAM9263
depends on AVR32 || ARCH_AT91SAM9260 || ARCH_AT91SAM9263 || ARCH_AT91CAP9
select PHYLIB
help
The Atmel MACB ethernet interface is found on many AT32 and AT91

2
drivers/usb/gadget/Kconfig
View file

@ -308,7 +308,7 @@ config USB_S3C2410_DEBUG
config USB_GADGET_AT91
boolean "AT91 USB Device Port"
depends on ARCH_AT91 && !ARCH_AT91SAM9RL
depends on ARCH_AT91 && !ARCH_AT91SAM9RL && !ARCH_AT91CAP9
select USB_GADGET_SELECTED
help
Many Atmel AT91 processors (such as the AT91RM2000) have a

2
drivers/video/Kconfig
View file

@ -889,7 +889,7 @@ config FB_S1D13XXX
config FB_ATMEL
tristate "AT91/AT32 LCD Controller support"
depends on FB && (ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || AVR32)
depends on FB && (ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || ARCH_AT91CAP9 || AVR32)
select FB_CFB_FILLRECT
select FB_CFB_COPYAREA
select FB_CFB_IMAGEBLIT

2
drivers/video/atmel_lcdfb.c
View file

@ -30,7 +30,7 @@
#define ATMEL_LCDC_CVAL_DEFAULT 0xc8
#define ATMEL_LCDC_DMA_BURST_LEN 8
#if defined(CONFIG_ARCH_AT91SAM9263)
#if defined(CONFIG_ARCH_AT91SAM9263) || defined(CONFIG_ARCH_AT91CAP9)
#define ATMEL_LCDC_FIFO_SIZE 2048
#else
#define ATMEL_LCDC_FIFO_SIZE 512

7
include/asm-arm/arch-at91/at91_pmc.h
View file

@ -25,6 +25,7 @@
#define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */
#define AT91RM9200_PMC_UHP (1 << 4) /* USB Host Port Clock [AT91RM9200 only] */
#define AT91SAM926x_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91SAM926x only] */
#define AT91CAP9_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91CAP9 only] */
#define AT91SAM926x_PMC_UDP (1 << 7) /* USB Devcice Port Clock [AT91SAM926x only] */
#define AT91_PMC_PCK0 (1 << 8) /* Programmable Clock 0 */
#define AT91_PMC_PCK1 (1 << 9) /* Programmable Clock 1 */
@ -37,7 +38,7 @@
#define AT91_PMC_PCDR (AT91_PMC + 0x14) /* Peripheral Clock Disable Register */
#define AT91_PMC_PCSR (AT91_PMC + 0x18) /* Peripheral Clock Status Register */
#define AT91_CKGR_UCKR (AT91_PMC + 0x1C) /* UTMI Clock Register [SAM9RL only] */
#define AT91_CKGR_UCKR (AT91_PMC + 0x1C) /* UTMI Clock Register [SAM9RL, CAP9] */
#define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register [not on SAM9RL] */
#define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */
@ -54,6 +55,10 @@
#define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */
#define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */
#define AT91_PMC_MUL (0x7ff << 16) /* PLL Multiplier */
#define AT91_PMC_USBDIV (3 << 28) /* USB Divisor (PLLB only) */
#define AT91_PMC_USBDIV_1 (0 << 28)
#define AT91_PMC_USBDIV_2 (1 << 28)
#define AT91_PMC_USBDIV_4 (2 << 28)
#define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */
#define AT91_PMC_MCKR (AT91_PMC + 0x30) /* Master Clock Register */

121
include/asm-arm/arch-at91/at91cap9.h Normal file
View file

@ -0,0 +1,121 @@
/*
* include/asm-arm/arch-at91/at91cap9.h
*
* Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com>
* Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com>
* Copyright (C) 2007 Atmel Corporation.
*
* Common definitions.
* Based on AT91CAP9 datasheet revision B (Preliminary).
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91CAP9_H
#define AT91CAP9_H
/*
* Peripheral identifiers/interrupts.
*/
#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
#define AT91_ID_SYS 1 /* System Peripherals */
#define AT91CAP9_ID_PIOABCD 2 /* Parallel IO Controller A, B, C and D */
#define AT91CAP9_ID_MPB0 3 /* MP Block Peripheral 0 */
#define AT91CAP9_ID_MPB1 4 /* MP Block Peripheral 1 */
#define AT91CAP9_ID_MPB2 5 /* MP Block Peripheral 2 */
#define AT91CAP9_ID_MPB3 6 /* MP Block Peripheral 3 */
#define AT91CAP9_ID_MPB4 7 /* MP Block Peripheral 4 */
#define AT91CAP9_ID_US0 8 /* USART 0 */
#define AT91CAP9_ID_US1 9 /* USART 1 */
#define AT91CAP9_ID_US2 10 /* USART 2 */
#define AT91CAP9_ID_MCI0 11 /* Multimedia Card Interface 0 */
#define AT91CAP9_ID_MCI1 12 /* Multimedia Card Interface 1 */
#define AT91CAP9_ID_CAN 13 /* CAN */
#define AT91CAP9_ID_TWI 14 /* Two-Wire Interface */
#define AT91CAP9_ID_SPI0 15 /* Serial Peripheral Interface 0 */
#define AT91CAP9_ID_SPI1 16 /* Serial Peripheral Interface 0 */
#define AT91CAP9_ID_SSC0 17 /* Serial Synchronous Controller 0 */
#define AT91CAP9_ID_SSC1 18 /* Serial Synchronous Controller 1 */
#define AT91CAP9_ID_AC97C 19 /* AC97 Controller */
#define AT91CAP9_ID_TCB 20 /* Timer Counter 0, 1 and 2 */
#define AT91CAP9_ID_PWMC 21 /* Pulse Width Modulation Controller */
#define AT91CAP9_ID_EMAC 22 /* Ethernet */
#define AT91CAP9_ID_AESTDES 23 /* Advanced Encryption Standard, Triple DES */
#define AT91CAP9_ID_ADC 24 /* Analog-to-Digital Converter */
#define AT91CAP9_ID_ISI 25 /* Image Sensor Interface */
#define AT91CAP9_ID_LCDC 26 /* LCD Controller */
#define AT91CAP9_ID_DMA 27 /* DMA Controller */
#define AT91CAP9_ID_UDPHS 28 /* USB High Speed Device Port */
#define AT91CAP9_ID_UHP 29 /* USB Host Port */
#define AT91CAP9_ID_IRQ0 30 /* Advanced Interrupt Controller (IRQ0) */
#define AT91CAP9_ID_IRQ1 31 /* Advanced Interrupt Controller (IRQ1) */
/*
* User Peripheral physical base addresses.
*/
#define AT91CAP9_BASE_UDPHS 0xfff78000
#define AT91CAP9_BASE_TCB0 0xfff7c000
#define AT91CAP9_BASE_TC0 0xfff7c000
#define AT91CAP9_BASE_TC1 0xfff7c040
#define AT91CAP9_BASE_TC2 0xfff7c080
#define AT91CAP9_BASE_MCI0 0xfff80000
#define AT91CAP9_BASE_MCI1 0xfff84000
#define AT91CAP9_BASE_TWI 0xfff88000
#define AT91CAP9_BASE_US0 0xfff8c000
#define AT91CAP9_BASE_US1 0xfff90000
#define AT91CAP9_BASE_US2 0xfff94000
#define AT91CAP9_BASE_SSC0 0xfff98000
#define AT91CAP9_BASE_SSC1 0xfff9c000
#define AT91CAP9_BASE_AC97C 0xfffa0000
#define AT91CAP9_BASE_SPI0 0xfffa4000
#define AT91CAP9_BASE_SPI1 0xfffa8000
#define AT91CAP9_BASE_CAN 0xfffac000
#define AT91CAP9_BASE_PWMC 0xfffb8000
#define AT91CAP9_BASE_EMAC 0xfffbc000
#define AT91CAP9_BASE_ADC 0xfffc0000
#define AT91CAP9_BASE_ISI 0xfffc4000
#define AT91_BASE_SYS 0xffffe200
/*
* System Peripherals (offset from AT91_BASE_SYS)
*/
#define AT91_ECC (0xffffe200 - AT91_BASE_SYS)
#define AT91_BCRAMC (0xffffe400 - AT91_BASE_SYS)
#define AT91_DDRSDRC (0xffffe600 - AT91_BASE_SYS)
#define AT91_SMC (0xffffe800 - AT91_BASE_SYS)
#define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS)
#define AT91_CCFG (0xffffeb10 - AT91_BASE_SYS)
#define AT91_DMA (0xffffec00 - AT91_BASE_SYS)
#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS)
#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
#define AT91_PIOA (0xfffff200 - AT91_BASE_SYS)
#define AT91_PIOB (0xfffff400 - AT91_BASE_SYS)
#define AT91_PIOC (0xfffff600 - AT91_BASE_SYS)
#define AT91_PIOD (0xfffff800 - AT91_BASE_SYS)
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
#define AT91_SHDC (0xfffffd10 - AT91_BASE_SYS)
#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS)
#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS)
/*
* Internal Memory.
*/
#define AT91CAP9_SRAM_BASE 0x00100000 /* Internal SRAM base address */
#define AT91CAP9_SRAM_SIZE (32 * SZ_1K) /* Internal SRAM size (32Kb) */
#define AT91CAP9_ROM_BASE 0x00400000 /* Internal ROM base address */
#define AT91CAP9_ROM_SIZE (32 * SZ_1K) /* Internal ROM size (32Kb) */
#define AT91CAP9_LCDC_BASE 0x00500000 /* LCD Controller */
#define AT91CAP9_UDPHS_BASE 0x00600000 /* USB High Speed Device Port */
#define AT91CAP9_UHP_BASE 0x00700000 /* USB Host controller */
#define CONFIG_DRAM_BASE AT91_CHIPSELECT_6
#endif

132
include/asm-arm/arch-at91/at91cap9_matrix.h Normal file
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@ -0,0 +1,132 @@
/*
* include/asm-arm/arch-at91/at91cap9_matrix.h
*
* Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com>
* Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com>
* Copyright (C) 2006 Atmel Corporation.
*
* Memory Controllers (MATRIX, EBI) - System peripherals registers.
* Based on AT91CAP9 datasheet revision B (Preliminary).
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91CAP9_MATRIX_H
#define AT91CAP9_MATRIX_H
#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */
#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */
#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */
#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */
#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */
#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */
#define AT91_MATRIX_MCFG6 (AT91_MATRIX + 0x18) /* Master Configuration Register 6 */
#define AT91_MATRIX_MCFG7 (AT91_MATRIX + 0x1C) /* Master Configuration Register 7 */
#define AT91_MATRIX_MCFG8 (AT91_MATRIX + 0x20) /* Master Configuration Register 8 */
#define AT91_MATRIX_MCFG9 (AT91_MATRIX + 0x24) /* Master Configuration Register 9 */
#define AT91_MATRIX_MCFG10 (AT91_MATRIX + 0x28) /* Master Configuration Register 10 */
#define AT91_MATRIX_MCFG11 (AT91_MATRIX + 0x2C) /* Master Configuration Register 11 */
#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
#define AT91_MATRIX_ULBT_FOUR (2 << 0)
#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */
#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */
#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */
#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */
#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */
#define AT91_MATRIX_SCFG5 (AT91_MATRIX + 0x54) /* Slave Configuration Register 5 */
#define AT91_MATRIX_SCFG6 (AT91_MATRIX + 0x58) /* Slave Configuration Register 6 */
#define AT91_MATRIX_SCFG7 (AT91_MATRIX + 0x5C) /* Slave Configuration Register 7 */
#define AT91_MATRIX_SCFG8 (AT91_MATRIX + 0x60) /* Slave Configuration Register 8 */
#define AT91_MATRIX_SCFG9 (AT91_MATRIX + 0x64) /* Slave Configuration Register 9 */
#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
#define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */
#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */
#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */
#define AT91_MATRIX_PRBS0 (AT91_MATRIX + 0x84) /* Priority Register B for Slave 0 */
#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */
#define AT91_MATRIX_PRBS1 (AT91_MATRIX + 0x8C) /* Priority Register B for Slave 1 */
#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */
#define AT91_MATRIX_PRBS2 (AT91_MATRIX + 0x94) /* Priority Register B for Slave 2 */
#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */
#define AT91_MATRIX_PRBS3 (AT91_MATRIX + 0x9C) /* Priority Register B for Slave 3 */
#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */
#define AT91_MATRIX_PRBS4 (AT91_MATRIX + 0xA4) /* Priority Register B for Slave 4 */
#define AT91_MATRIX_PRAS5 (AT91_MATRIX + 0xA8) /* Priority Register A for Slave 5 */
#define AT91_MATRIX_PRBS5 (AT91_MATRIX + 0xAC) /* Priority Register B for Slave 5 */
#define AT91_MATRIX_PRAS6 (AT91_MATRIX + 0xB0) /* Priority Register A for Slave 6 */
#define AT91_MATRIX_PRBS6 (AT91_MATRIX + 0xB4) /* Priority Register B for Slave 6 */
#define AT91_MATRIX_PRAS7 (AT91_MATRIX + 0xB8) /* Priority Register A for Slave 7 */
#define AT91_MATRIX_PRBS7 (AT91_MATRIX + 0xBC) /* Priority Register B for Slave 7 */
#define AT91_MATRIX_PRAS8 (AT91_MATRIX + 0xC0) /* Priority Register A for Slave 8 */
#define AT91_MATRIX_PRBS8 (AT91_MATRIX + 0xC4) /* Priority Register B for Slave 8 */
#define AT91_MATRIX_PRAS9 (AT91_MATRIX + 0xC8) /* Priority Register A for Slave 9 */
#define AT91_MATRIX_PRBS9 (AT91_MATRIX + 0xCC) /* Priority Register B for Slave 9 */
#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */
#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
#define AT91_MATRIX_M6PR (3 << 24) /* Master 6 Priority */
#define AT91_MATRIX_M7PR (3 << 28) /* Master 7 Priority */
#define AT91_MATRIX_M8PR (3 << 0) /* Master 8 Priority (in Register B) */
#define AT91_MATRIX_M9PR (3 << 4) /* Master 9 Priority (in Register B) */
#define AT91_MATRIX_M10PR (3 << 8) /* Master 10 Priority (in Register B) */
#define AT91_MATRIX_M11PR (3 << 12) /* Master 11 Priority (in Register B) */
#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */
#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
#define AT91_MATRIX_RCB2 (1 << 2)
#define AT91_MATRIX_RCB3 (1 << 3)
#define AT91_MATRIX_RCB4 (1 << 4)
#define AT91_MATRIX_RCB5 (1 << 5)
#define AT91_MATRIX_RCB6 (1 << 6)
#define AT91_MATRIX_RCB7 (1 << 7)
#define AT91_MATRIX_RCB8 (1 << 8)
#define AT91_MATRIX_RCB9 (1 << 9)
#define AT91_MATRIX_RCB10 (1 << 10)
#define AT91_MATRIX_RCB11 (1 << 11)
#define AT91_MPBS0_SFR (AT91_MATRIX + 0x114) /* MPBlock Slave 0 Special Function Register */
#define AT91_MPBS1_SFR (AT91_MATRIX + 0x11C) /* MPBlock Slave 1 Special Function Register */
#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x120) /* EBI Chip Select Assignment Register */
#define AT91_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */
#define AT91_MATRIX_EBI_CS1A_SMC (0 << 1)
#define AT91_MATRIX_EBI_CS1A_BCRAMC (1 << 1)
#define AT91_MATRIX_EBI_CS3A (1 << 3) /* Chip Select 3 Assignment */
#define AT91_MATRIX_EBI_CS3A_SMC (0 << 3)
#define AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA (1 << 3)
#define AT91_MATRIX_EBI_CS4A (1 << 4) /* Chip Select 4 Assignment */
#define AT91_MATRIX_EBI_CS4A_SMC (0 << 4)
#define AT91_MATRIX_EBI_CS4A_SMC_CF1 (1 << 4)
#define AT91_MATRIX_EBI_CS5A (1 << 5) /* Chip Select 5 Assignment */
#define AT91_MATRIX_EBI_CS5A_SMC (0 << 5)
#define AT91_MATRIX_EBI_CS5A_SMC_CF2 (1 << 5)
#define AT91_MATRIX_EBI_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
#define AT91_MATRIX_EBI_DQSPDC (1 << 9) /* Data Qualifier Strobe Pull-Down Configuration */
#define AT91_MATRIX_EBI_VDDIOMSEL (1 << 16) /* Memory voltage selection */
#define AT91_MATRIX_EBI_VDDIOMSEL_1_8V (0 << 16)
#define AT91_MATRIX_EBI_VDDIOMSEL_3_3V (1 << 16)
#define AT91_MPBS2_SFR (AT91_MATRIX + 0x12C) /* MPBlock Slave 2 Special Function Register */
#define AT91_MPBS3_SFR (AT91_MATRIX + 0x130) /* MPBlock Slave 3 Special Function Register */
#define AT91_APB_SFR (AT91_MATRIX + 0x134) /* APB Bridge Special Function Register */
#endif

2
include/asm-arm/arch-at91/at91sam9263_matrix.h
View file

@ -44,7 +44,7 @@
#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
#define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */
#define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */
#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */
#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)

2
include/asm-arm/arch-at91/at91sam9rl_matrix.h
View file

@ -38,7 +38,7 @@
#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
#define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */
#define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */
#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */
#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)

2
include/asm-arm/arch-at91/board.h
View file

@ -72,7 +72,7 @@ struct at91_eth_data {
};
extern void __init at91_add_device_eth(struct at91_eth_data *data);
#if defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9263)
#if defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9263) || defined(CONFIG_ARCH_AT91CAP9)
#define eth_platform_data at91_eth_data
#endif

9
include/asm-arm/arch-at91/cpu.h
View file

@ -21,13 +21,13 @@
#define ARCH_ID_AT91SAM9260 0x019803a0
#define ARCH_ID_AT91SAM9261 0x019703a0
#define ARCH_ID_AT91SAM9263 0x019607a0
#define ARCH_ID_AT91SAM9RL64 0x019b03a0
#define ARCH_ID_AT91CAP9 0x039A03A0
#define ARCH_ID_AT91SAM9XE128 0x329973a0
#define ARCH_ID_AT91SAM9XE256 0x329a93a0
#define ARCH_ID_AT91SAM9XE512 0x329aa3a0
#define ARCH_ID_AT91SAM9RL64 0x019b03a0
#define ARCH_ID_AT91M40800 0x14080044
#define ARCH_ID_AT91R40807 0x44080746
#define ARCH_ID_AT91M40807 0x14080745
@ -81,6 +81,11 @@ static inline unsigned long at91_arch_identify(void)
#define cpu_is_at91sam9rl() (0)
#endif
#ifdef CONFIG_ARCH_AT91CAP9
#define cpu_is_at91cap9() (at91_cpu_identify() == ARCH_ID_AT91CAP9)
#else
#define cpu_is_at91cap9() (0)
#endif
/*
* Since this is ARM, we will never run on any AVR32 CPU. But these

2
include/asm-arm/arch-at91/hardware.h
View file

@ -26,6 +26,8 @@
#include <asm/arch/at91sam9263.h>
#elif defined(CONFIG_ARCH_AT91SAM9RL)
#include <asm/arch/at91sam9rl.h>
#elif defined(CONFIG_ARCH_AT91CAP9)
#include <asm/arch/at91cap9.h>
#elif defined(CONFIG_ARCH_AT91X40)
#include <asm/arch/at91x40.h>
#else

5
include/asm-arm/arch-at91/timex.h
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@ -42,6 +42,11 @@
#define AT91SAM9_MASTER_CLOCK 100000000
#define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16)
#elif defined(CONFIG_ARCH_AT91CAP9)
#define AT91CAP9_MASTER_CLOCK 100000000
#define CLOCK_TICK_RATE (AT91CAP9_MASTER_CLOCK/16)
#elif defined(CONFIG_ARCH_AT91X40)
#define AT91X40_MASTER_CLOCK 40000000

1
include/asm-avr32/arch-at32ap/cpu.h
View file

@ -30,5 +30,6 @@
#define cpu_is_at91sam9261() (0)
#define cpu_is_at91sam9263() (0)
#define cpu_is_at91sam9rl() (0)
#define cpu_is_at91cap9() (0)
#endif /* __ASM_ARCH_CPU_H */