amd64_edac: add memory scrubber interface
Borislav: - fix/cleanup comments - fix function return value patterns - cleanup debug calls Reviewed-by: Mauro Carvalho Chehab <mchehab@redhat.com> Signed-off-by: Doug Thompson <dougthompson@xmission.com> Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
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drivers/edac/amd64_edac.c
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drivers/edac/amd64_edac.c
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#include "amd64_edac.h"
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static struct edac_pci_ctl_info *amd64_ctl_pci;
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static int report_gart_errors;
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module_param(report_gart_errors, int, 0644);
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/*
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* Set by command line parameter. If BIOS has enabled the ECC, this override is
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* cleared to prevent re-enabling the hardware by this driver.
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*/
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static int ecc_enable_override;
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module_param(ecc_enable_override, int, 0644);
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/* Lookup table for all possible MC control instances */
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struct amd64_pvt;
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static struct mem_ctl_info *mci_lookup[MAX_NUMNODES];
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static struct amd64_pvt *pvt_lookup[MAX_NUMNODES];
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/*
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* Memory scrubber control interface. For K8, memory scrubbing is handled by
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* hardware and can involve L2 cache, dcache as well as the main memory. With
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* F10, this is extended to L3 cache scrubbing on CPU models sporting that
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* functionality.
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*
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* This causes the "units" for the scrubbing speed to vary from 64 byte blocks
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* (dram) over to cache lines. This is nasty, so we will use bandwidth in
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* bytes/sec for the setting.
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*
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* Currently, we only do dram scrubbing. If the scrubbing is done in software on
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* other archs, we might not have access to the caches directly.
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*/
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/*
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* scan the scrub rate mapping table for a close or matching bandwidth value to
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* issue. If requested is too big, then use last maximum value found.
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*/
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static int amd64_search_set_scrub_rate(struct pci_dev *ctl, u32 new_bw,
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u32 min_scrubrate)
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{
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u32 scrubval;
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int i;
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/*
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* map the configured rate (new_bw) to a value specific to the AMD64
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* memory controller and apply to register. Search for the first
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* bandwidth entry that is greater or equal than the setting requested
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* and program that. If at last entry, turn off DRAM scrubbing.
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*/
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for (i = 0; i < ARRAY_SIZE(scrubrates); i++) {
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/*
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* skip scrub rates which aren't recommended
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* (see F10 BKDG, F3x58)
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*/
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if (scrubrates[i].scrubval < min_scrubrate)
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continue;
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if (scrubrates[i].bandwidth <= new_bw)
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break;
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/*
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* if no suitable bandwidth found, turn off DRAM scrubbing
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* entirely by falling back to the last element in the
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* scrubrates array.
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*/
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}
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scrubval = scrubrates[i].scrubval;
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if (scrubval)
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edac_printk(KERN_DEBUG, EDAC_MC,
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"Setting scrub rate bandwidth: %u\n",
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scrubrates[i].bandwidth);
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else
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edac_printk(KERN_DEBUG, EDAC_MC, "Turning scrubbing off.\n");
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pci_write_bits32(ctl, K8_SCRCTRL, scrubval, 0x001F);
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return 0;
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}
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static int amd64_set_scrub_rate(struct mem_ctl_info *mci, u32 *bandwidth)
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{
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struct amd64_pvt *pvt = mci->pvt_info;
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u32 min_scrubrate = 0x0;
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switch (boot_cpu_data.x86) {
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case 0xf:
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min_scrubrate = K8_MIN_SCRUB_RATE_BITS;
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break;
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case 0x10:
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min_scrubrate = F10_MIN_SCRUB_RATE_BITS;
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break;
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case 0x11:
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min_scrubrate = F11_MIN_SCRUB_RATE_BITS;
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break;
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default:
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amd64_printk(KERN_ERR, "Unsupported family!\n");
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break;
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}
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return amd64_search_set_scrub_rate(pvt->misc_f3_ctl, *bandwidth,
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min_scrubrate);
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}
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static int amd64_get_scrub_rate(struct mem_ctl_info *mci, u32 *bw)
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{
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struct amd64_pvt *pvt = mci->pvt_info;
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u32 scrubval = 0;
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int status = -1, i, ret = 0;
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ret = pci_read_config_dword(pvt->misc_f3_ctl, K8_SCRCTRL, &scrubval);
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if (ret)
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debugf0("Reading K8_SCRCTRL failed\n");
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scrubval = scrubval & 0x001F;
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edac_printk(KERN_DEBUG, EDAC_MC,
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"pci-read, sdram scrub control value: %d \n", scrubval);
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for (i = 0; ARRAY_SIZE(scrubrates); i++) {
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if (scrubrates[i].scrubval == scrubval) {
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*bw = scrubrates[i].bandwidth;
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status = 0;
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break;
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}
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}
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return status;
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}
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