amd64_edac: add helper to dump relevant registers
Borislav: - cleanup/fix comments - fix function return value patterns - cleanup dbg calls Reviewed-by: Mauro Carvalho Chehab <mchehab@redhat.com> Signed-off-by: Doug Thompson <dougthompson@xmission.com> Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
This commit is contained in:
Doug Thompson
Borislav Petkov
parent
93c2df58b5
commit
2da11654ea
1 changed files with 142 additions and 0 deletions
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@ -729,3 +729,145 @@ static int sys_addr_to_csrow(struct mem_ctl_info *mci, u64 sys_addr)
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return csrow;
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}
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static int get_channel_from_ecc_syndrome(unsigned short syndrome);
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static void amd64_cpu_display_info(struct amd64_pvt *pvt)
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{
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if (boot_cpu_data.x86 == 0x11)
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edac_printk(KERN_DEBUG, EDAC_MC, "F11h CPU detected\n");
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else if (boot_cpu_data.x86 == 0x10)
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edac_printk(KERN_DEBUG, EDAC_MC, "F10h CPU detected\n");
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else if (boot_cpu_data.x86 == 0xf)
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edac_printk(KERN_DEBUG, EDAC_MC, "%s detected\n",
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(pvt->ext_model >= OPTERON_CPU_REV_F) ?
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"Rev F or later" : "Rev E or earlier");
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else
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/* we'll hardly ever ever get here */
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edac_printk(KERN_ERR, EDAC_MC, "Unknown cpu!\n");
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}
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/*
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* Determine if the DIMMs have ECC enabled. ECC is enabled ONLY if all the DIMMs
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* are ECC capable.
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*/
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static enum edac_type amd64_determine_edac_cap(struct amd64_pvt *pvt)
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{
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int bit;
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enum dev_type edac_cap = EDAC_NONE;
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bit = (boot_cpu_data.x86 > 0xf || pvt->ext_model >= OPTERON_CPU_REV_F)
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? 19
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: 17;
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if (pvt->dclr0 >> BIT(bit))
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edac_cap = EDAC_FLAG_SECDED;
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return edac_cap;
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}
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static void f10_debug_display_dimm_sizes(int ctrl, struct amd64_pvt *pvt,
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int ganged);
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/* Display and decode various NB registers for debug purposes. */
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static void amd64_dump_misc_regs(struct amd64_pvt *pvt)
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{
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int ganged;
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debugf1(" nbcap:0x%8.08x DctDualCap=%s DualNode=%s 8-Node=%s\n",
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pvt->nbcap,
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(pvt->nbcap & K8_NBCAP_DCT_DUAL) ? "True" : "False",
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(pvt->nbcap & K8_NBCAP_DUAL_NODE) ? "True" : "False",
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(pvt->nbcap & K8_NBCAP_8_NODE) ? "True" : "False");
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debugf1(" ECC Capable=%s ChipKill Capable=%s\n",
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(pvt->nbcap & K8_NBCAP_SECDED) ? "True" : "False",
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(pvt->nbcap & K8_NBCAP_CHIPKILL) ? "True" : "False");
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debugf1(" DramCfg0-low=0x%08x DIMM-ECC=%s Parity=%s Width=%s\n",
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pvt->dclr0,
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(pvt->dclr0 & BIT(19)) ? "Enabled" : "Disabled",
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(pvt->dclr0 & BIT(8)) ? "Enabled" : "Disabled",
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(pvt->dclr0 & BIT(11)) ? "128b" : "64b");
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debugf1(" DIMM x4 Present: L0=%s L1=%s L2=%s L3=%s DIMM Type=%s\n",
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(pvt->dclr0 & BIT(12)) ? "Y" : "N",
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(pvt->dclr0 & BIT(13)) ? "Y" : "N",
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(pvt->dclr0 & BIT(14)) ? "Y" : "N",
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(pvt->dclr0 & BIT(15)) ? "Y" : "N",
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(pvt->dclr0 & BIT(16)) ? "UN-Buffered" : "Buffered");
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debugf1(" online-spare: 0x%8.08x\n", pvt->online_spare);
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if (boot_cpu_data.x86 == 0xf) {
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debugf1(" dhar: 0x%8.08x Base=0x%08x Offset=0x%08x\n",
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pvt->dhar, dhar_base(pvt->dhar),
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k8_dhar_offset(pvt->dhar));
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debugf1(" DramHoleValid=%s\n",
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(pvt->dhar & DHAR_VALID) ? "True" : "False");
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debugf1(" dbam-dkt: 0x%8.08x\n", pvt->dbam0);
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/* everything below this point is Fam10h and above */
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return;
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} else {
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debugf1(" dhar: 0x%8.08x Base=0x%08x Offset=0x%08x\n",
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pvt->dhar, dhar_base(pvt->dhar),
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f10_dhar_offset(pvt->dhar));
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debugf1(" DramMemHoistValid=%s DramHoleValid=%s\n",
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(pvt->dhar & F10_DRAM_MEM_HOIST_VALID) ?
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"True" : "False",
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(pvt->dhar & DHAR_VALID) ?
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"True" : "False");
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}
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/* Only if NOT ganged does dcl1 have valid info */
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if (!dct_ganging_enabled(pvt)) {
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debugf1(" DramCfg1-low=0x%08x DIMM-ECC=%s Parity=%s "
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"Width=%s\n", pvt->dclr1,
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(pvt->dclr1 & BIT(19)) ? "Enabled" : "Disabled",
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(pvt->dclr1 & BIT(8)) ? "Enabled" : "Disabled",
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(pvt->dclr1 & BIT(11)) ? "128b" : "64b");
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debugf1(" DIMM x4 Present: L0=%s L1=%s L2=%s L3=%s "
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"DIMM Type=%s\n",
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(pvt->dclr1 & BIT(12)) ? "Y" : "N",
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(pvt->dclr1 & BIT(13)) ? "Y" : "N",
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(pvt->dclr1 & BIT(14)) ? "Y" : "N",
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(pvt->dclr1 & BIT(15)) ? "Y" : "N",
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(pvt->dclr1 & BIT(16)) ? "UN-Buffered" : "Buffered");
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}
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/*
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* Determine if ganged and then dump memory sizes for first controller,
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* and if NOT ganged dump info for 2nd controller.
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*/
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ganged = dct_ganging_enabled(pvt);
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f10_debug_display_dimm_sizes(0, pvt, ganged);
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if (!ganged)
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f10_debug_display_dimm_sizes(1, pvt, ganged);
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}
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/* Read in both of DBAM registers */
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static void amd64_read_dbam_reg(struct amd64_pvt *pvt)
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{
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int err = 0;
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unsigned int reg;
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reg = DBAM0;
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err = pci_read_config_dword(pvt->dram_f2_ctl, reg, &pvt->dbam0);
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if (err)
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goto err_reg;
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if (boot_cpu_data.x86 >= 0x10) {
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reg = DBAM1;
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err = pci_read_config_dword(pvt->dram_f2_ctl, reg, &pvt->dbam1);
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if (err)
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goto err_reg;
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}
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err_reg:
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debugf0("Error reading F2x%03x.\n", reg);
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}
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