irqchip: Add NXP INTMUX interrupt multiplexer support
The Interrupt Multiplexer (INTMUX) expands the number of peripherals that can interrupt the core: * The INTMUX has 8 channels that are assigned to 8 NVIC interrupt slots. * Each INTMUX channel can receive up to 32 interrupt sources and has 1 interrupt output. * The INTMUX routes the interrupt sources to the interrupt outputs. Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20200117060653.27485-3-qiangqing.zhang@nxp.com
This commit is contained in:
Joakim Zhang
Marc Zyngier
parent
618ea6275b
commit
2fbb13961e
3 changed files with 316 additions and 0 deletions
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@ -457,6 +457,12 @@ config IMX_IRQSTEER
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help
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Support for the i.MX IRQSTEER interrupt multiplexer/remapper.
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config IMX_INTMUX
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def_bool y if ARCH_MXC
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select IRQ_DOMAIN
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help
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Support for the i.MX INTMUX interrupt multiplexer.
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config LS1X_IRQ
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bool "Loongson-1 Interrupt Controller"
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depends on MACH_LOONGSON32
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@ -100,6 +100,7 @@ obj-$(CONFIG_CSKY_MPINTC) += irq-csky-mpintc.o
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obj-$(CONFIG_CSKY_APB_INTC) += irq-csky-apb-intc.o
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obj-$(CONFIG_SIFIVE_PLIC) += irq-sifive-plic.o
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obj-$(CONFIG_IMX_IRQSTEER) += irq-imx-irqsteer.o
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obj-$(CONFIG_IMX_INTMUX) += irq-imx-intmux.o
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obj-$(CONFIG_MADERA_IRQ) += irq-madera.o
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obj-$(CONFIG_LS1X_IRQ) += irq-ls1x.o
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obj-$(CONFIG_TI_SCI_INTR_IRQCHIP) += irq-ti-sci-intr.o
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309
drivers/irqchip/irq-imx-intmux.c
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309
drivers/irqchip/irq-imx-intmux.c
Normal file
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@ -0,0 +1,309 @@
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// SPDX-License-Identifier: GPL-2.0
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// Copyright 2017 NXP
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/* INTMUX Block Diagram
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*
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* ________________
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* interrupt source # 0 +---->| |
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* | | |
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* interrupt source # 1 +++-->| |
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* ... | | | channel # 0 |--------->interrupt out # 0
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* ... | | | |
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* ... | | | |
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* interrupt source # X-1 +++-->|________________|
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* | | |
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* | | |
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* | | | ________________
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* +---->| |
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* | | | | |
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* | +-->| |
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* | | | | channel # 1 |--------->interrupt out # 1
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* | | +>| |
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* | | | | |
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* | | | |________________|
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* | | |
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* | | |
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* | | | ...
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* | | | ...
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* | | |
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* | | | ________________
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* +---->| |
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* | | | |
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* +-->| |
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* | | channel # N |--------->interrupt out # N
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* +>| |
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* | |
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* |________________|
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*
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*
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* N: Interrupt Channel Instance Number (N=7)
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* X: Interrupt Source Number for each channel (X=32)
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*
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* The INTMUX interrupt multiplexer has 8 channels, each channel receives 32
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* interrupt sources and generates 1 interrupt output.
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*
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*/
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#include <linux/clk.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/irqdomain.h>
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#include <linux/kernel.h>
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#include <linux/of_irq.h>
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#include <linux/of_platform.h>
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#include <linux/spinlock.h>
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#define CHANIER(n) (0x10 + (0x40 * n))
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#define CHANIPR(n) (0x20 + (0x40 * n))
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#define CHAN_MAX_NUM 0x8
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struct intmux_irqchip_data {
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int chanidx;
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int irq;
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struct irq_domain *domain;
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};
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struct intmux_data {
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raw_spinlock_t lock;
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void __iomem *regs;
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struct clk *ipg_clk;
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int channum;
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struct intmux_irqchip_data irqchip_data[];
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};
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static void imx_intmux_irq_mask(struct irq_data *d)
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{
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struct intmux_irqchip_data *irqchip_data = d->chip_data;
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int idx = irqchip_data->chanidx;
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struct intmux_data *data = container_of(irqchip_data, struct intmux_data,
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irqchip_data[idx]);
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unsigned long flags;
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void __iomem *reg;
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u32 val;
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raw_spin_lock_irqsave(&data->lock, flags);
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reg = data->regs + CHANIER(idx);
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val = readl_relaxed(reg);
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/* disable the interrupt source of this channel */
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val &= ~BIT(d->hwirq);
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writel_relaxed(val, reg);
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raw_spin_unlock_irqrestore(&data->lock, flags);
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}
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static void imx_intmux_irq_unmask(struct irq_data *d)
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{
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struct intmux_irqchip_data *irqchip_data = d->chip_data;
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int idx = irqchip_data->chanidx;
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struct intmux_data *data = container_of(irqchip_data, struct intmux_data,
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irqchip_data[idx]);
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unsigned long flags;
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void __iomem *reg;
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u32 val;
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raw_spin_lock_irqsave(&data->lock, flags);
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reg = data->regs + CHANIER(idx);
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val = readl_relaxed(reg);
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/* enable the interrupt source of this channel */
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val |= BIT(d->hwirq);
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writel_relaxed(val, reg);
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raw_spin_unlock_irqrestore(&data->lock, flags);
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}
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static struct irq_chip imx_intmux_irq_chip = {
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.name = "intmux",
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.irq_mask = imx_intmux_irq_mask,
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.irq_unmask = imx_intmux_irq_unmask,
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};
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static int imx_intmux_irq_map(struct irq_domain *h, unsigned int irq,
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irq_hw_number_t hwirq)
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{
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irq_set_chip_data(irq, h->host_data);
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irq_set_chip_and_handler(irq, &imx_intmux_irq_chip, handle_level_irq);
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return 0;
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}
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static int imx_intmux_irq_xlate(struct irq_domain *d, struct device_node *node,
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const u32 *intspec, unsigned int intsize,
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unsigned long *out_hwirq, unsigned int *out_type)
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{
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struct intmux_irqchip_data *irqchip_data = d->host_data;
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int idx = irqchip_data->chanidx;
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struct intmux_data *data = container_of(irqchip_data, struct intmux_data,
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irqchip_data[idx]);
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/*
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* two cells needed in interrupt specifier:
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* the 1st cell: hw interrupt number
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* the 2nd cell: channel index
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*/
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if (WARN_ON(intsize != 2))
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return -EINVAL;
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if (WARN_ON(intspec[1] >= data->channum))
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return -EINVAL;
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*out_hwirq = intspec[0];
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*out_type = IRQ_TYPE_LEVEL_HIGH;
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return 0;
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}
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static int imx_intmux_irq_select(struct irq_domain *d, struct irq_fwspec *fwspec,
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enum irq_domain_bus_token bus_token)
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{
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struct intmux_irqchip_data *irqchip_data = d->host_data;
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/* Not for us */
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if (fwspec->fwnode != d->fwnode)
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return false;
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return irqchip_data->chanidx == fwspec->param[1];
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}
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static const struct irq_domain_ops imx_intmux_domain_ops = {
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.map = imx_intmux_irq_map,
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.xlate = imx_intmux_irq_xlate,
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.select = imx_intmux_irq_select,
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};
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static void imx_intmux_irq_handler(struct irq_desc *desc)
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{
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struct intmux_irqchip_data *irqchip_data = irq_desc_get_handler_data(desc);
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int idx = irqchip_data->chanidx;
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struct intmux_data *data = container_of(irqchip_data, struct intmux_data,
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irqchip_data[idx]);
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unsigned long irqstat;
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int pos, virq;
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chained_irq_enter(irq_desc_get_chip(desc), desc);
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/* read the interrupt source pending status of this channel */
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irqstat = readl_relaxed(data->regs + CHANIPR(idx));
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for_each_set_bit(pos, &irqstat, 32) {
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virq = irq_find_mapping(irqchip_data->domain, pos);
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if (virq)
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generic_handle_irq(virq);
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}
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chained_irq_exit(irq_desc_get_chip(desc), desc);
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}
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static int imx_intmux_probe(struct platform_device *pdev)
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{
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struct device_node *np = pdev->dev.of_node;
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struct irq_domain *domain;
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struct intmux_data *data;
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int channum;
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int i, ret;
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channum = platform_irq_count(pdev);
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if (channum == -EPROBE_DEFER) {
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return -EPROBE_DEFER;
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} else if (channum > CHAN_MAX_NUM) {
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dev_err(&pdev->dev, "supports up to %d multiplex channels\n",
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CHAN_MAX_NUM);
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return -EINVAL;
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}
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data = devm_kzalloc(&pdev->dev, sizeof(*data) +
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channum * sizeof(data->irqchip_data[0]), GFP_KERNEL);
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if (!data)
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return -ENOMEM;
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data->regs = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(data->regs)) {
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dev_err(&pdev->dev, "failed to initialize reg\n");
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return PTR_ERR(data->regs);
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}
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data->ipg_clk = devm_clk_get(&pdev->dev, "ipg");
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if (IS_ERR(data->ipg_clk)) {
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ret = PTR_ERR(data->ipg_clk);
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if (ret != -EPROBE_DEFER)
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dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret);
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return ret;
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}
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data->channum = channum;
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raw_spin_lock_init(&data->lock);
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ret = clk_prepare_enable(data->ipg_clk);
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if (ret) {
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dev_err(&pdev->dev, "failed to enable ipg clk: %d\n", ret);
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return ret;
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}
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for (i = 0; i < channum; i++) {
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data->irqchip_data[i].chanidx = i;
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data->irqchip_data[i].irq = irq_of_parse_and_map(np, i);
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if (data->irqchip_data[i].irq <= 0) {
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ret = -EINVAL;
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dev_err(&pdev->dev, "failed to get irq\n");
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goto out;
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}
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domain = irq_domain_add_linear(np, 32, &imx_intmux_domain_ops,
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&data->irqchip_data[i]);
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if (!domain) {
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ret = -ENOMEM;
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dev_err(&pdev->dev, "failed to create IRQ domain\n");
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goto out;
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}
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data->irqchip_data[i].domain = domain;
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/* disable all interrupt sources of this channel firstly */
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writel_relaxed(0, data->regs + CHANIER(i));
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irq_set_chained_handler_and_data(data->irqchip_data[i].irq,
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imx_intmux_irq_handler,
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&data->irqchip_data[i]);
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}
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platform_set_drvdata(pdev, data);
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return 0;
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out:
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clk_disable_unprepare(data->ipg_clk);
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return ret;
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}
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static int imx_intmux_remove(struct platform_device *pdev)
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{
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struct intmux_data *data = platform_get_drvdata(pdev);
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int i;
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for (i = 0; i < data->channum; i++) {
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/* disable all interrupt sources of this channel */
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writel_relaxed(0, data->regs + CHANIER(i));
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irq_set_chained_handler_and_data(data->irqchip_data[i].irq,
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NULL, NULL);
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irq_domain_remove(data->irqchip_data[i].domain);
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}
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clk_disable_unprepare(data->ipg_clk);
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return 0;
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}
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static const struct of_device_id imx_intmux_id[] = {
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{ .compatible = "fsl,imx-intmux", },
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{ /* sentinel */ },
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};
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static struct platform_driver imx_intmux_driver = {
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.driver = {
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.name = "imx-intmux",
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.of_match_table = imx_intmux_id,
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},
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.probe = imx_intmux_probe,
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.remove = imx_intmux_remove,
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};
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builtin_platform_driver(imx_intmux_driver);
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