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Merge branch 'x86-platform-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Browse source 
Pull x86 core platform updates from Ingo Molnar:
 "The main changes are:

   - Intel Atom platform updates.  (Andy Shevchenko)

   - modularity fixlets.  (Paul Gortmaker)

   - x86 platform clockevents driver updates for lguest, uv and Xen.
     (Viresh Kumar)

   - Microsoft Hyper-V TSC fixlet.  (Vitaly Kuznetsov)"

* 'x86-platform-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86/platform: Make atom/pmc_atom.c explicitly non-modular
  x86/hyperv: Mark the Hyper-V TSC as unstable
  x86/xen/time: Migrate to new set-state interface
  x86/uv/time: Migrate to new set-state interface
  x86/lguest/timer: Migrate to new set-state interface
  x86/pci/intel_mid_pci: Use proper constants for irq polarity
  x86/pci/intel_mid_pci: Make intel_mid_pci_ops static
  x86/pci/intel_mid_pci: Propagate actual return code
  x86/pci/intel_mid_pci: Work around for IRQ0 assignment
  x86/platform/iosf_mbi: Add Intel Tangier PCI id
  x86/platform/iosf_mbi: Source cleanup
  x86/platform/iosf_mbi: Remove NULL pointer checks for pci_dev_put()
  x86/platform/iosf_mbi: Check return value of debugfs_create properly
  x86/platform/iosf_mbi: Move to dedicated folder
  x86/platform/intel/pmc_atom: Move the PMC-Atom code to arch/x86/platform/atom
  x86/platform/intel/pmc_atom: Add Cherrytrail PMC interface
  x86/platform/intel/pmc_atom: Supply register mappings via PMC object
  x86/platform/intel/pmc_atom: Print index of device in loop
  x86/platform/intel/pmc_atom: Export accessors to PMC registers
This commit is contained in:
Linus Torvalds 2015-09-01 10:33:31 -07:00
commit 361f7d1757
13 changed files with 337 additions and 237 deletions
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8
arch/x86/include/asm/iosf_mbi.h
View file

@ -52,20 +52,20 @@
/* Quark available units */
#define QRK_MBI_UNIT_HBA 0x00
#define QRK_MBI_UNIT_HB 0x03
#define QRK_MBI_UNIT_HB 0x03
#define QRK_MBI_UNIT_RMU 0x04
#define QRK_MBI_UNIT_MM 0x05
#define QRK_MBI_UNIT_MM 0x05
#define QRK_MBI_UNIT_MMESRAM 0x05
#define QRK_MBI_UNIT_SOC 0x31
/* Quark read/write opcodes */
#define QRK_MBI_HBA_READ 0x10
#define QRK_MBI_HBA_WRITE 0x11
#define QRK_MBI_HB_READ 0x10
#define QRK_MBI_HB_READ 0x10
#define QRK_MBI_HB_WRITE 0x11
#define QRK_MBI_RMU_READ 0x10
#define QRK_MBI_RMU_WRITE 0x11
#define QRK_MBI_MM_READ 0x10
#define QRK_MBI_MM_READ 0x10
#define QRK_MBI_MM_WRITE 0x11
#define QRK_MBI_MMESRAM_READ 0x12
#define QRK_MBI_MMESRAM_WRITE 0x13

29
arch/x86/include/asm/pmc_atom.h
View file

@ -18,6 +18,8 @@
/* ValleyView Power Control Unit PCI Device ID */
#define PCI_DEVICE_ID_VLV_PMC 0x0F1C
/* CherryTrail Power Control Unit PCI Device ID */
#define PCI_DEVICE_ID_CHT_PMC 0x229C
/* PMC Memory mapped IO registers */
#define PMC_BASE_ADDR_OFFSET 0x44
@ -29,6 +31,10 @@
#define PMC_FUNC_DIS 0x34
#define PMC_FUNC_DIS_2 0x38
/* CHT specific bits in FUNC_DIS2 register */
#define BIT_FD_GMM BIT(3)
#define BIT_FD_ISH BIT(4)
/* S0ix wake event control */
#define PMC_S0IX_WAKE_EN 0x3C
@ -75,6 +81,21 @@
#define PMC_PSS_BIT_USB BIT(16)
#define PMC_PSS_BIT_USB_SUS BIT(17)
/* CHT specific bits in PSS register */
#define PMC_PSS_BIT_CHT_UFS BIT(7)
#define PMC_PSS_BIT_CHT_UXD BIT(11)
#define PMC_PSS_BIT_CHT_UXD_FD BIT(12)
#define PMC_PSS_BIT_CHT_UX_ENG BIT(15)
#define PMC_PSS_BIT_CHT_USB_SUS BIT(16)
#define PMC_PSS_BIT_CHT_GMM BIT(17)
#define PMC_PSS_BIT_CHT_ISH BIT(18)
#define PMC_PSS_BIT_CHT_DFX_MASTER BIT(26)
#define PMC_PSS_BIT_CHT_DFX_CLUSTER1 BIT(27)
#define PMC_PSS_BIT_CHT_DFX_CLUSTER2 BIT(28)
#define PMC_PSS_BIT_CHT_DFX_CLUSTER3 BIT(29)
#define PMC_PSS_BIT_CHT_DFX_CLUSTER4 BIT(30)
#define PMC_PSS_BIT_CHT_DFX_CLUSTER5 BIT(31)
/* These registers reflect D3 status of functions */
#define PMC_D3_STS_0 0xA0
@ -117,6 +138,10 @@
#define BIT_USH_SS_PHY BIT(2)
#define BIT_DFX BIT(3)
/* CHT specific bits in PMC_D3_STS_1 register */
#define BIT_STS_GMM BIT(1)
#define BIT_STS_ISH BIT(2)
/* PMC I/O Registers */
#define ACPI_BASE_ADDR_OFFSET 0x40
#define ACPI_BASE_ADDR_MASK 0xFFFFFE00
@ -126,4 +151,8 @@
#define SLEEP_TYPE_MASK 0xFFFFECFF
#define SLEEP_TYPE_S5 0x1C00
#define SLEEP_ENABLE 0x2000
extern int pmc_atom_read(int offset, u32 *value);
extern int pmc_atom_write(int offset, u32 value);
#endif /* PMC_ATOM_H */

2
arch/x86/kernel/Makefile
View file

@ -109,8 +109,6 @@ obj-$(CONFIG_EFI) += sysfb_efi.o
obj-$(CONFIG_PERF_EVENTS) += perf_regs.o
obj-$(CONFIG_TRACING) += tracepoint.o
obj-$(CONFIG_IOSF_MBI) += iosf_mbi.o
obj-$(CONFIG_PMC_ATOM) += pmc_atom.o
###
# 64 bit specific files

1
arch/x86/kernel/cpu/mshyperv.c
View file

@ -188,6 +188,7 @@ static void __init ms_hyperv_init_platform(void)
machine_ops.shutdown = hv_machine_shutdown;
machine_ops.crash_shutdown = hv_machine_crash_shutdown;
mark_tsc_unstable("running on Hyper-V");
}
const __refconst struct hypervisor_x86 x86_hyper_ms_hyperv = {

22
arch/x86/lguest/boot.c
View file

@ -985,23 +985,11 @@ static int lguest_clockevent_set_next_event(unsigned long delta,
return 0;
}
static void lguest_clockevent_set_mode(enum clock_event_mode mode,
struct clock_event_device *evt)
static int lguest_clockevent_shutdown(struct clock_event_device *evt)
{
switch (mode) {
case CLOCK_EVT_MODE_UNUSED:
case CLOCK_EVT_MODE_SHUTDOWN:
/* A 0 argument shuts the clock down. */
hcall(LHCALL_SET_CLOCKEVENT, 0, 0, 0, 0);
break;
case CLOCK_EVT_MODE_ONESHOT:
/* This is what we expect. */
break;
case CLOCK_EVT_MODE_PERIODIC:
BUG();
case CLOCK_EVT_MODE_RESUME:
break;
}
/* A 0 argument shuts the clock down. */
hcall(LHCALL_SET_CLOCKEVENT, 0, 0, 0, 0);
return 0;
}
/* This describes our primitive timer chip. */
@ -1009,7 +997,7 @@ static struct clock_event_device lguest_clockevent = {
.name = "lguest",
.features = CLOCK_EVT_FEAT_ONESHOT,
.set_next_event = lguest_clockevent_set_next_event,
.set_mode = lguest_clockevent_set_mode,
.set_state_shutdown = lguest_clockevent_shutdown,
.rating = INT_MAX,
.mult = 1,
.shift = 0,

36
arch/x86/pci/intel_mid_pci.c
View file

@ -35,6 +35,9 @@
#define PCIE_CAP_OFFSET 0x100
/* Quirks for the listed devices */
#define PCI_DEVICE_ID_INTEL_MRFL_MMC 0x1190
/* Fixed BAR fields */
#define PCIE_VNDR_CAP_ID_FIXED_BAR 0x00 /* Fixed BAR (TBD) */
#define PCI_FIXED_BAR_0_SIZE 0x04
@ -210,22 +213,41 @@ static int intel_mid_pci_irq_enable(struct pci_dev *dev)
{
struct irq_alloc_info info;
int polarity;
int ret;
if (pci_has_managed_irq(dev))
return 0;
if (intel_mid_identify_cpu() == INTEL_MID_CPU_CHIP_TANGIER)
polarity = 0; /* active high */
else
polarity = 1; /* active low */
switch (intel_mid_identify_cpu()) {
case INTEL_MID_CPU_CHIP_TANGIER:
polarity = IOAPIC_POL_HIGH;
/* Special treatment for IRQ0 */
if (dev->irq == 0) {
/*
* TNG has IRQ0 assigned to eMMC controller. But there
* are also other devices with bogus PCI configuration
* that have IRQ0 assigned. This check ensures that
* eMMC gets it.
*/
if (dev->device != PCI_DEVICE_ID_INTEL_MRFL_MMC)
return -EBUSY;
}
break;
default:
polarity = IOAPIC_POL_LOW;
break;
}
ioapic_set_alloc_attr(&info, dev_to_node(&dev->dev), 1, polarity);
/*
* MRST only have IOAPIC, the PCI irq lines are 1:1 mapped to
* IOAPIC RTE entries, so we just enable RTE for the device.
*/
if (mp_map_gsi_to_irq(dev->irq, IOAPIC_MAP_ALLOC, &info) < 0)
return -EBUSY;
ret = mp_map_gsi_to_irq(dev->irq, IOAPIC_MAP_ALLOC, &info);
if (ret < 0)
return ret;
dev->irq_managed = 1;
@ -244,7 +266,7 @@ static void intel_mid_pci_irq_disable(struct pci_dev *dev)
}
}
struct pci_ops intel_mid_pci_ops = {
static struct pci_ops intel_mid_pci_ops = {
.read = pci_read,
.write = pci_write,
};

1
arch/x86/platform/Makefile
View file

@ -5,6 +5,7 @@ obj-y += efi/
obj-y += geode/
obj-y += goldfish/
obj-y += iris/
obj-y += intel/
obj-y += intel-mid/
obj-y += intel-quark/
obj-y += olpc/

3
arch/x86/platform/atom/Makefile
View file

@ -1 +1,2 @@
obj-$(CONFIG_PUNIT_ATOM_DEBUG) += punit_atom_debug.o
obj-$(CONFIG_PMC_ATOM) += pmc_atom.o
obj-$(CONFIG_PUNIT_ATOM_DEBUG) += punit_atom_debug.o

327
arch/x86/kernel/pmc_atom.c → arch/x86/platform/atom/pmc_atom.c
View file

@ -15,7 +15,6 @@
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/module.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/device.h>
@ -25,80 +24,149 @@
#include <asm/pmc_atom.h>
struct pmc_dev {
u32 base_addr;
void __iomem *regmap;
#ifdef CONFIG_DEBUG_FS
struct dentry *dbgfs_dir;
#endif /* CONFIG_DEBUG_FS */
};
static struct pmc_dev pmc_device;
static u32 acpi_base_addr;
struct pmc_bit_map {
const char *name;
u32 bit_mask;
};
static const struct pmc_bit_map dev_map[] = {
{"0 - LPSS1_F0_DMA", BIT_LPSS1_F0_DMA},
{"1 - LPSS1_F1_PWM1", BIT_LPSS1_F1_PWM1},
{"2 - LPSS1_F2_PWM2", BIT_LPSS1_F2_PWM2},
{"3 - LPSS1_F3_HSUART1", BIT_LPSS1_F3_HSUART1},
{"4 - LPSS1_F4_HSUART2", BIT_LPSS1_F4_HSUART2},
{"5 - LPSS1_F5_SPI", BIT_LPSS1_F5_SPI},
{"6 - LPSS1_F6_Reserved", BIT_LPSS1_F6_XXX},
{"7 - LPSS1_F7_Reserved", BIT_LPSS1_F7_XXX},
{"8 - SCC_EMMC", BIT_SCC_EMMC},
{"9 - SCC_SDIO", BIT_SCC_SDIO},
{"10 - SCC_SDCARD", BIT_SCC_SDCARD},
{"11 - SCC_MIPI", BIT_SCC_MIPI},
{"12 - HDA", BIT_HDA},
{"13 - LPE", BIT_LPE},
{"14 - OTG", BIT_OTG},
{"15 - USH", BIT_USH},
{"16 - GBE", BIT_GBE},
{"17 - SATA", BIT_SATA},
{"18 - USB_EHCI", BIT_USB_EHCI},
{"19 - SEC", BIT_SEC},
{"20 - PCIE_PORT0", BIT_PCIE_PORT0},
{"21 - PCIE_PORT1", BIT_PCIE_PORT1},
{"22 - PCIE_PORT2", BIT_PCIE_PORT2},
{"23 - PCIE_PORT3", BIT_PCIE_PORT3},
{"24 - LPSS2_F0_DMA", BIT_LPSS2_F0_DMA},
{"25 - LPSS2_F1_I2C1", BIT_LPSS2_F1_I2C1},
{"26 - LPSS2_F2_I2C2", BIT_LPSS2_F2_I2C2},
{"27 - LPSS2_F3_I2C3", BIT_LPSS2_F3_I2C3},
{"28 - LPSS2_F3_I2C4", BIT_LPSS2_F4_I2C4},
{"29 - LPSS2_F5_I2C5", BIT_LPSS2_F5_I2C5},
{"30 - LPSS2_F6_I2C6", BIT_LPSS2_F6_I2C6},
{"31 - LPSS2_F7_I2C7", BIT_LPSS2_F7_I2C7},
{"32 - SMB", BIT_SMB},
{"33 - OTG_SS_PHY", BIT_OTG_SS_PHY},
{"34 - USH_SS_PHY", BIT_USH_SS_PHY},
{"35 - DFX", BIT_DFX},
struct pmc_reg_map {
const struct pmc_bit_map *d3_sts_0;
const struct pmc_bit_map *d3_sts_1;
const struct pmc_bit_map *func_dis;
const struct pmc_bit_map *func_dis_2;
const struct pmc_bit_map *pss;
};
static const struct pmc_bit_map pss_map[] = {
{"0 - GBE", PMC_PSS_BIT_GBE},
{"1 - SATA", PMC_PSS_BIT_SATA},
{"2 - HDA", PMC_PSS_BIT_HDA},
{"3 - SEC", PMC_PSS_BIT_SEC},
{"4 - PCIE", PMC_PSS_BIT_PCIE},
{"5 - LPSS", PMC_PSS_BIT_LPSS},
{"6 - LPE", PMC_PSS_BIT_LPE},
{"7 - DFX", PMC_PSS_BIT_DFX},
{"8 - USH_CTRL", PMC_PSS_BIT_USH_CTRL},
{"9 - USH_SUS", PMC_PSS_BIT_USH_SUS},
{"10 - USH_VCCS", PMC_PSS_BIT_USH_VCCS},
{"11 - USH_VCCA", PMC_PSS_BIT_USH_VCCA},
{"12 - OTG_CTRL", PMC_PSS_BIT_OTG_CTRL},
{"13 - OTG_VCCS", PMC_PSS_BIT_OTG_VCCS},
{"14 - OTG_VCCA_CLK", PMC_PSS_BIT_OTG_VCCA_CLK},
{"15 - OTG_VCCA", PMC_PSS_BIT_OTG_VCCA},
{"16 - USB", PMC_PSS_BIT_USB},
{"17 - USB_SUS", PMC_PSS_BIT_USB_SUS},
struct pmc_dev {
u32 base_addr;
void __iomem *regmap;
const struct pmc_reg_map *map;
#ifdef CONFIG_DEBUG_FS
struct dentry *dbgfs_dir;
#endif /* CONFIG_DEBUG_FS */
bool init;
};
static struct pmc_dev pmc_device;
static u32 acpi_base_addr;
static const struct pmc_bit_map d3_sts_0_map[] = {
{"LPSS1_F0_DMA", BIT_LPSS1_F0_DMA},
{"LPSS1_F1_PWM1", BIT_LPSS1_F1_PWM1},
{"LPSS1_F2_PWM2", BIT_LPSS1_F2_PWM2},
{"LPSS1_F3_HSUART1", BIT_LPSS1_F3_HSUART1},
{"LPSS1_F4_HSUART2", BIT_LPSS1_F4_HSUART2},
{"LPSS1_F5_SPI", BIT_LPSS1_F5_SPI},
{"LPSS1_F6_Reserved", BIT_LPSS1_F6_XXX},
{"LPSS1_F7_Reserved", BIT_LPSS1_F7_XXX},
{"SCC_EMMC", BIT_SCC_EMMC},
{"SCC_SDIO", BIT_SCC_SDIO},
{"SCC_SDCARD", BIT_SCC_SDCARD},
{"SCC_MIPI", BIT_SCC_MIPI},
{"HDA", BIT_HDA},
{"LPE", BIT_LPE},
{"OTG", BIT_OTG},
{"USH", BIT_USH},
{"GBE", BIT_GBE},
{"SATA", BIT_SATA},
{"USB_EHCI", BIT_USB_EHCI},
{"SEC", BIT_SEC},
{"PCIE_PORT0", BIT_PCIE_PORT0},
{"PCIE_PORT1", BIT_PCIE_PORT1},
{"PCIE_PORT2", BIT_PCIE_PORT2},
{"PCIE_PORT3", BIT_PCIE_PORT3},
{"LPSS2_F0_DMA", BIT_LPSS2_F0_DMA},
{"LPSS2_F1_I2C1", BIT_LPSS2_F1_I2C1},
{"LPSS2_F2_I2C2", BIT_LPSS2_F2_I2C2},
{"LPSS2_F3_I2C3", BIT_LPSS2_F3_I2C3},
{"LPSS2_F3_I2C4", BIT_LPSS2_F4_I2C4},
{"LPSS2_F5_I2C5", BIT_LPSS2_F5_I2C5},
{"LPSS2_F6_I2C6", BIT_LPSS2_F6_I2C6},
{"LPSS2_F7_I2C7", BIT_LPSS2_F7_I2C7},
{},
};
static struct pmc_bit_map byt_d3_sts_1_map[] = {
{"SMB", BIT_SMB},
{"OTG_SS_PHY", BIT_OTG_SS_PHY},
{"USH_SS_PHY", BIT_USH_SS_PHY},
{"DFX", BIT_DFX},
{},
};
static struct pmc_bit_map cht_d3_sts_1_map[] = {
{"SMB", BIT_SMB},
{"GMM", BIT_STS_GMM},
{"ISH", BIT_STS_ISH},
{},
};
static struct pmc_bit_map cht_func_dis_2_map[] = {
{"SMB", BIT_SMB},
{"GMM", BIT_FD_GMM},
{"ISH", BIT_FD_ISH},
{},
};
static const struct pmc_bit_map byt_pss_map[] = {
{"GBE", PMC_PSS_BIT_GBE},
{"SATA", PMC_PSS_BIT_SATA},
{"HDA", PMC_PSS_BIT_HDA},
{"SEC", PMC_PSS_BIT_SEC},
{"PCIE", PMC_PSS_BIT_PCIE},
{"LPSS", PMC_PSS_BIT_LPSS},
{"LPE", PMC_PSS_BIT_LPE},
{"DFX", PMC_PSS_BIT_DFX},
{"USH_CTRL", PMC_PSS_BIT_USH_CTRL},
{"USH_SUS", PMC_PSS_BIT_USH_SUS},
{"USH_VCCS", PMC_PSS_BIT_USH_VCCS},
{"USH_VCCA", PMC_PSS_BIT_USH_VCCA},
{"OTG_CTRL", PMC_PSS_BIT_OTG_CTRL},
{"OTG_VCCS", PMC_PSS_BIT_OTG_VCCS},
{"OTG_VCCA_CLK", PMC_PSS_BIT_OTG_VCCA_CLK},
{"OTG_VCCA", PMC_PSS_BIT_OTG_VCCA},
{"USB", PMC_PSS_BIT_USB},
{"USB_SUS", PMC_PSS_BIT_USB_SUS},
{},
};
static const struct pmc_bit_map cht_pss_map[] = {
{"SATA", PMC_PSS_BIT_SATA},
{"HDA", PMC_PSS_BIT_HDA},
{"SEC", PMC_PSS_BIT_SEC},
{"PCIE", PMC_PSS_BIT_PCIE},
{"LPSS", PMC_PSS_BIT_LPSS},
{"LPE", PMC_PSS_BIT_LPE},
{"UFS", PMC_PSS_BIT_CHT_UFS},
{"UXD", PMC_PSS_BIT_CHT_UXD},
{"UXD_FD", PMC_PSS_BIT_CHT_UXD_FD},
{"UX_ENG", PMC_PSS_BIT_CHT_UX_ENG},
{"USB_SUS", PMC_PSS_BIT_CHT_USB_SUS},
{"GMM", PMC_PSS_BIT_CHT_GMM},
{"ISH", PMC_PSS_BIT_CHT_ISH},
{"DFX_MASTER", PMC_PSS_BIT_CHT_DFX_MASTER},
{"DFX_CLUSTER1", PMC_PSS_BIT_CHT_DFX_CLUSTER1},
{"DFX_CLUSTER2", PMC_PSS_BIT_CHT_DFX_CLUSTER2},
{"DFX_CLUSTER3", PMC_PSS_BIT_CHT_DFX_CLUSTER3},
{"DFX_CLUSTER4", PMC_PSS_BIT_CHT_DFX_CLUSTER4},
{"DFX_CLUSTER5", PMC_PSS_BIT_CHT_DFX_CLUSTER5},
{},
};
static const struct pmc_reg_map byt_reg_map = {
.d3_sts_0 = d3_sts_0_map,
.d3_sts_1 = byt_d3_sts_1_map,
.func_dis = d3_sts_0_map,
.func_dis_2 = byt_d3_sts_1_map,
.pss = byt_pss_map,
};
static const struct pmc_reg_map cht_reg_map = {
.d3_sts_0 = d3_sts_0_map,
.d3_sts_1 = cht_d3_sts_1_map,
.func_dis = d3_sts_0_map,
.func_dis_2 = cht_func_dis_2_map,
.pss = cht_pss_map,
};
static inline u32 pmc_reg_read(struct pmc_dev *pmc, int reg_offset)
@ -111,6 +179,30 @@ static inline void pmc_reg_write(struct pmc_dev *pmc, int reg_offset, u32 val)
writel(val, pmc->regmap + reg_offset);
}
int pmc_atom_read(int offset, u32 *value)
{
struct pmc_dev *pmc = &pmc_device;
if (!pmc->init)
return -ENODEV;
*value = pmc_reg_read(pmc, offset);
return 0;
}
EXPORT_SYMBOL_GPL(pmc_atom_read);
int pmc_atom_write(int offset, u32 value)
{
struct pmc_dev *pmc = &pmc_device;
if (!pmc->init)
return -ENODEV;
pmc_reg_write(pmc, offset, value);
return 0;
}
EXPORT_SYMBOL_GPL(pmc_atom_write);
static void pmc_power_off(void)
{
u16 pm1_cnt_port;
@ -142,37 +234,39 @@ static void pmc_hw_reg_setup(struct pmc_dev *pmc)
}
#ifdef CONFIG_DEBUG_FS
static void pmc_dev_state_print(struct seq_file *s, int reg_index,
u32 sts, const struct pmc_bit_map *sts_map,
u32 fd, const struct pmc_bit_map *fd_map)
{
int offset = PMC_REG_BIT_WIDTH * reg_index;
int index;
for (index = 0; sts_map[index].name; index++) {
seq_printf(s, "Dev: %-2d - %-32s\tState: %s [%s]\n",
offset + index, sts_map[index].name,
fd_map[index].bit_mask & fd ? "Disabled" : "Enabled ",
sts_map[index].bit_mask & sts ? "D3" : "D0");
}
}
static int pmc_dev_state_show(struct seq_file *s, void *unused)
{
struct pmc_dev *pmc = s->private;
u32 func_dis, func_dis_2, func_dis_index;
u32 d3_sts_0, d3_sts_1, d3_sts_index;
int dev_num, dev_index, reg_index;
const struct pmc_reg_map *m = pmc->map;
u32 func_dis, func_dis_2;
u32 d3_sts_0, d3_sts_1;
func_dis = pmc_reg_read(pmc, PMC_FUNC_DIS);
func_dis_2 = pmc_reg_read(pmc, PMC_FUNC_DIS_2);
d3_sts_0 = pmc_reg_read(pmc, PMC_D3_STS_0);
d3_sts_1 = pmc_reg_read(pmc, PMC_D3_STS_1);
dev_num = ARRAY_SIZE(dev_map);
/* Low part */
pmc_dev_state_print(s, 0, d3_sts_0, m->d3_sts_0, func_dis, m->func_dis);
for (dev_index = 0; dev_index < dev_num; dev_index++) {
reg_index = dev_index / PMC_REG_BIT_WIDTH;
if (reg_index) {
func_dis_index = func_dis_2;
d3_sts_index = d3_sts_1;
} else {
func_dis_index = func_dis;
d3_sts_index = d3_sts_0;
}
/* High part */
pmc_dev_state_print(s, 1, d3_sts_1, m->d3_sts_1, func_dis_2, m->func_dis_2);
seq_printf(s, "Dev: %-32s\tState: %s [%s]\n",
dev_map[dev_index].name,
dev_map[dev_index].bit_mask & func_dis_index ?
"Disabled" : "Enabled ",
dev_map[dev_index].bit_mask & d3_sts_index ?
"D3" : "D0");
}
return 0;
}
@ -191,13 +285,14 @@ static const struct file_operations pmc_dev_state_ops = {
static int pmc_pss_state_show(struct seq_file *s, void *unused)
{
struct pmc_dev *pmc = s->private;
const struct pmc_bit_map *map = pmc->map->pss;
u32 pss = pmc_reg_read(pmc, PMC_PSS);
int pss_index;
int index;
for (pss_index = 0; pss_index < ARRAY_SIZE(pss_map); pss_index++) {
seq_printf(s, "Island: %-32s\tState: %s\n",
pss_map[pss_index].name,
pss_map[pss_index].bit_mask & pss ? "Off" : "On");
for (index = 0; map[index].name; index++) {
seq_printf(s, "Island: %-2d - %-32s\tState: %s\n",
index, map[index].name,
map[index].bit_mask & pss ? "Off" : "On");
}
return 0;
}
@ -250,7 +345,7 @@ static void pmc_dbgfs_unregister(struct pmc_dev *pmc)
debugfs_remove_recursive(pmc->dbgfs_dir);
}
static int pmc_dbgfs_register(struct pmc_dev *pmc, struct pci_dev *pdev)
static int pmc_dbgfs_register(struct pmc_dev *pmc)
{
struct dentry *dir, *f;
@ -262,24 +357,18 @@ static int pmc_dbgfs_register(struct pmc_dev *pmc, struct pci_dev *pdev)
f = debugfs_create_file("dev_state", S_IFREG | S_IRUGO,
dir, pmc, &pmc_dev_state_ops);
if (!f) {
dev_err(&pdev->dev, "dev_state register failed\n");
if (!f)
goto err;
}
f = debugfs_create_file("pss_state", S_IFREG | S_IRUGO,
dir, pmc, &pmc_pss_state_ops);
if (!f) {
dev_err(&pdev->dev, "pss_state register failed\n");
if (!f)
goto err;
}
f = debugfs_create_file("sleep_state", S_IFREG | S_IRUGO,
dir, pmc, &pmc_sleep_tmr_ops);
if (!f) {
dev_err(&pdev->dev, "sleep_state register failed\n");
if (!f)
goto err;
}
return 0;
err:
@ -287,15 +376,16 @@ err:
return -ENODEV;
}
#else
static int pmc_dbgfs_register(struct pmc_dev *pmc, struct pci_dev *pdev)
static int pmc_dbgfs_register(struct pmc_dev *pmc)
{
return 0;
}
#endif /* CONFIG_DEBUG_FS */
static int pmc_setup_dev(struct pci_dev *pdev)
static int pmc_setup_dev(struct pci_dev *pdev, const struct pci_device_id *ent)
{
struct pmc_dev *pmc = &pmc_device;
const struct pmc_reg_map *map = (struct pmc_reg_map *)ent->driver_data;
int ret;
/* Obtain ACPI base address */
@ -315,32 +405,30 @@ static int pmc_setup_dev(struct pci_dev *pdev)
return -ENOMEM;
}
pmc->map = map;
/* PMC hardware registers setup */
pmc_hw_reg_setup(pmc);
ret = pmc_dbgfs_register(pmc, pdev);
if (ret) {
iounmap(pmc->regmap);
}
ret = pmc_dbgfs_register(pmc);
if (ret)
dev_warn(&pdev->dev, "debugfs register failed\n");
pmc->init = true;
return ret;
}
/*
* Data for PCI driver interface
*
* This data only exists for exporting the supported
* PCI ids via MODULE_DEVICE_TABLE. We do not actually
* register a pci_driver, because lpc_ich will register
* a driver on the same PCI id.
* used by pci_match_id() call below.
*/
static const struct pci_device_id pmc_pci_ids[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_VLV_PMC) },
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_VLV_PMC), (kernel_ulong_t)&byt_reg_map },
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_CHT_PMC), (kernel_ulong_t)&cht_reg_map },
{ 0, },
};
MODULE_DEVICE_TABLE(pci, pmc_pci_ids);
static int __init pmc_atom_init(void)
{
struct pci_dev *pdev = NULL;
@ -357,15 +445,16 @@ static int __init pmc_atom_init(void)
for_each_pci_dev(pdev) {
ent = pci_match_id(pmc_pci_ids, pdev);
if (ent)
return pmc_setup_dev(pdev);
return pmc_setup_dev(pdev, ent);
}
/* Device not found. */
return -ENODEV;
}
module_init(pmc_atom_init);
/* no module_exit, this driver shouldn't be unloaded */
device_initcall(pmc_atom_init);
/*
MODULE_AUTHOR("Aubrey Li <aubrey.li@linux.intel.com>");
MODULE_DESCRIPTION("Intel Atom SOC Power Management Controller Interface");
MODULE_LICENSE("GPL v2");
*/

1
arch/x86/platform/intel/Makefile Normal file
View file

@ -0,0 +1 @@
obj-$(CONFIG_IOSF_MBI) += iosf_mbi.o

27
arch/x86/kernel/iosf_mbi.c → arch/x86/platform/intel/iosf_mbi.c
View file

@ -30,7 +30,9 @@
#define PCI_DEVICE_ID_BAYTRAIL 0x0F00
#define PCI_DEVICE_ID_BRASWELL 0x2280
#define PCI_DEVICE_ID_QUARK_X1000 0x0958
#define PCI_DEVICE_ID_TANGIER 0x1170
static struct pci_dev *mbi_pdev;
static DEFINE_SPINLOCK(iosf_mbi_lock);
static inline u32 iosf_mbi_form_mcr(u8 op, u8 port, u8 offset)
@ -38,8 +40,6 @@ static inline u32 iosf_mbi_form_mcr(u8 op, u8 port, u8 offset)
return (op << 24) | (port << 16) | (offset << 8) | MBI_ENABLE;
}
static struct pci_dev *mbi_pdev; /* one mbi device */
static int iosf_mbi_pci_read_mdr(u32 mcrx, u32 mcr, u32 *mdr)
{
int result;
@ -104,7 +104,7 @@ int iosf_mbi_read(u8 port, u8 opcode, u32 offset, u32 *mdr)
unsigned long flags;
int ret;
/*Access to the GFX unit is handled by GPU code */
/* Access to the GFX unit is handled by GPU code */
if (port == BT_MBI_UNIT_GFX) {
WARN_ON(1);
return -EPERM;
@ -127,7 +127,7 @@ int iosf_mbi_write(u8 port, u8 opcode, u32 offset, u32 mdr)
unsigned long flags;
int ret;
/*Access to the GFX unit is handled by GPU code */
/* Access to the GFX unit is handled by GPU code */
if (port == BT_MBI_UNIT_GFX) {
WARN_ON(1);
return -EPERM;
@ -151,7 +151,7 @@ int iosf_mbi_modify(u8 port, u8 opcode, u32 offset, u32 mdr, u32 mask)
unsigned long flags;
int ret;
/*Access to the GFX unit is handled by GPU code */
/* Access to the GFX unit is handled by GPU code */
if (port == BT_MBI_UNIT_GFX) {
WARN_ON(1);
return -EPERM;
@ -240,17 +240,17 @@ static void iosf_sideband_debug_init(void)
/* mdr */
d = debugfs_create_x32("mdr", 0660, iosf_dbg, &dbg_mdr);
if (IS_ERR_OR_NULL(d))
if (!d)
goto cleanup;
/* mcrx */
debugfs_create_x32("mcrx", 0660, iosf_dbg, &dbg_mcrx);
if (IS_ERR_OR_NULL(d))
d = debugfs_create_x32("mcrx", 0660, iosf_dbg, &dbg_mcrx);
if (!d)
goto cleanup;
/* mcr - initiates mailbox tranaction */
debugfs_create_file("mcr", 0660, iosf_dbg, &dbg_mcr, &iosf_mcr_fops);
if (IS_ERR_OR_NULL(d))
d = debugfs_create_file("mcr", 0660, iosf_dbg, &dbg_mcr, &iosf_mcr_fops);
if (!d)
goto cleanup;
return;
@ -292,6 +292,7 @@ static const struct pci_device_id iosf_mbi_pci_ids[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_BAYTRAIL) },
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_BRASWELL) },
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_QUARK_X1000) },
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_TANGIER) },
{ 0, },
};
MODULE_DEVICE_TABLE(pci, iosf_mbi_pci_ids);
@ -314,10 +315,8 @@ static void __exit iosf_mbi_exit(void)
iosf_debugfs_remove();
pci_unregister_driver(&iosf_mbi_pci_driver);
if (mbi_pdev) {
pci_dev_put(mbi_pdev);
mbi_pdev = NULL;
}
pci_dev_put(mbi_pdev);
mbi_pdev = NULL;
}
module_init(iosf_mbi_init);

37
arch/x86/platform/uv/uv_time.c
View file

@ -32,8 +32,7 @@
static cycle_t uv_read_rtc(struct clocksource *cs);
static int uv_rtc_next_event(unsigned long, struct clock_event_device *);
static void uv_rtc_timer_setup(enum clock_event_mode,
struct clock_event_device *);
static int uv_rtc_shutdown(struct clock_event_device *evt);
static struct clocksource clocksource_uv = {
.name = RTC_NAME,
@ -44,14 +43,14 @@ static struct clocksource clocksource_uv = {
};
static struct clock_event_device clock_event_device_uv = {
.name = RTC_NAME,
.features = CLOCK_EVT_FEAT_ONESHOT,
.shift = 20,
.rating = 400,
.irq = -1,
.set_next_event = uv_rtc_next_event,
.set_mode = uv_rtc_timer_setup,
.event_handler = NULL,
.name = RTC_NAME,
.features = CLOCK_EVT_FEAT_ONESHOT,
.shift = 20,
.rating = 400,
.irq = -1,
.set_next_event = uv_rtc_next_event,
.set_state_shutdown = uv_rtc_shutdown,
.event_handler = NULL,
};
static DEFINE_PER_CPU(struct clock_event_device, cpu_ced);
@ -321,24 +320,14 @@ static int uv_rtc_next_event(unsigned long delta,
}
/*
* Setup the RTC timer in oneshot mode
* Shutdown the RTC timer
*/
static void uv_rtc_timer_setup(enum clock_event_mode mode,
struct clock_event_device *evt)
static int uv_rtc_shutdown(struct clock_event_device *evt)
{
int ced_cpu = cpumask_first(evt->cpumask);
switch (mode) {
case CLOCK_EVT_MODE_PERIODIC:
case CLOCK_EVT_MODE_ONESHOT:
case CLOCK_EVT_MODE_RESUME:
/* Nothing to do here yet */
break;
case CLOCK_EVT_MODE_UNUSED:
case CLOCK_EVT_MODE_SHUTDOWN:
uv_rtc_unset_timer(ced_cpu, 1);
break;
}
uv_rtc_unset_timer(ced_cpu, 1);
return 0;
}
static void uv_rtc_interrupt(void)

80
arch/x86/xen/time.c
View file

@ -274,30 +274,18 @@ static s64 get_abs_timeout(unsigned long delta)
return xen_clocksource_read() + delta;
}
static void xen_timerop_set_mode(enum clock_event_mode mode,
struct clock_event_device *evt)
static int xen_timerop_shutdown(struct clock_event_device *evt)
{
switch (mode) {
case CLOCK_EVT_MODE_PERIODIC:
/* unsupported */
WARN_ON(1);
break;
/* cancel timeout */
HYPERVISOR_set_timer_op(0);
case CLOCK_EVT_MODE_ONESHOT:
case CLOCK_EVT_MODE_RESUME:
break;
case CLOCK_EVT_MODE_UNUSED:
case CLOCK_EVT_MODE_SHUTDOWN:
HYPERVISOR_set_timer_op(0); /* cancel timeout */
break;
}
return 0;
}
static int xen_timerop_set_next_event(unsigned long delta,
struct clock_event_device *evt)
{
WARN_ON(evt->mode != CLOCK_EVT_MODE_ONESHOT);
WARN_ON(!clockevent_state_oneshot(evt));
if (HYPERVISOR_set_timer_op(get_abs_timeout(delta)) < 0)
BUG();
@ -310,46 +298,39 @@ static int xen_timerop_set_next_event(unsigned long delta,
}
static const struct clock_event_device xen_timerop_clockevent = {
.name = "xen",
.features = CLOCK_EVT_FEAT_ONESHOT,
.name = "xen",
.features = CLOCK_EVT_FEAT_ONESHOT,
.max_delta_ns = 0xffffffff,
.min_delta_ns = TIMER_SLOP,
.max_delta_ns = 0xffffffff,
.min_delta_ns = TIMER_SLOP,
.mult = 1,
.shift = 0,
.rating = 500,
.mult = 1,
.shift = 0,
.rating = 500,
.set_mode = xen_timerop_set_mode,
.set_next_event = xen_timerop_set_next_event,
.set_state_shutdown = xen_timerop_shutdown,
.set_next_event = xen_timerop_set_next_event,
};
static void xen_vcpuop_set_mode(enum clock_event_mode mode,
struct clock_event_device *evt)
static int xen_vcpuop_shutdown(struct clock_event_device *evt)
{
int cpu = smp_processor_id();
switch (mode) {
case CLOCK_EVT_MODE_PERIODIC:
WARN_ON(1); /* unsupported */
break;
if (HYPERVISOR_vcpu_op(VCPUOP_stop_singleshot_timer, cpu, NULL) ||
HYPERVISOR_vcpu_op(VCPUOP_stop_periodic_timer, cpu, NULL))
BUG();
case CLOCK_EVT_MODE_ONESHOT:
if (HYPERVISOR_vcpu_op(VCPUOP_stop_periodic_timer, cpu, NULL))
BUG();
break;
return 0;
}
case CLOCK_EVT_MODE_UNUSED:
case CLOCK_EVT_MODE_SHUTDOWN:
if (HYPERVISOR_vcpu_op(VCPUOP_stop_singleshot_timer, cpu, NULL) ||
HYPERVISOR_vcpu_op(VCPUOP_stop_periodic_timer, cpu, NULL))
BUG();
break;
case CLOCK_EVT_MODE_RESUME:
break;
}
static int xen_vcpuop_set_oneshot(struct clock_event_device *evt)
{
int cpu = smp_processor_id();
if (HYPERVISOR_vcpu_op(VCPUOP_stop_periodic_timer, cpu, NULL))
BUG();
return 0;
}
static int xen_vcpuop_set_next_event(unsigned long delta,
@ -359,7 +340,7 @@ static int xen_vcpuop_set_next_event(unsigned long delta,
struct vcpu_set_singleshot_timer single;
int ret;
WARN_ON(evt->mode != CLOCK_EVT_MODE_ONESHOT);
WARN_ON(!clockevent_state_oneshot(evt));
single.timeout_abs_ns = get_abs_timeout(delta);
single.flags = VCPU_SSHOTTMR_future;
@ -382,7 +363,8 @@ static const struct clock_event_device xen_vcpuop_clockevent = {
.shift = 0,
.rating = 500,
.set_mode = xen_vcpuop_set_mode,
.set_state_shutdown = xen_vcpuop_shutdown,
.set_state_oneshot = xen_vcpuop_set_oneshot,
.set_next_event = xen_vcpuop_set_next_event,
};