m68knommu: make 523x QSPI platform addressing consistent
If we make all QSPI (SPI protocol) addressing consistent across all ColdFire family members then we will be able to remove the duplicated plaform data and code and use a single setup for all. So modify the ColdFire 523x QSPI addressing so that: . base addresses are absolute (not relative to MBAR peripheral register) . use a common name for IRQs used . move chip select definitions (CS) to appropriate header Signed-off-by: Greg Ungerer <gerg@uclinux.org>
This commit is contained in:
parent
a4e2e2ac08
commit
36d175a4b2
3 changed files with 18 additions and 10 deletions
|
@ -51,6 +51,8 @@
|
|||
#define MCF_IRQ_FECTX0 (MCFINT_VECBASE + MCFINT_FECTX0)
|
||||
#define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0)
|
||||
|
||||
#define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI)
|
||||
|
||||
/*
|
||||
* SDRAM configuration registers.
|
||||
*/
|
||||
|
@ -82,6 +84,17 @@
|
|||
#define MCFFEC_BASE0 (MCF_IPSBAR + 0x1000)
|
||||
#define MCFFEC_SIZE0 0x800
|
||||
|
||||
/*
|
||||
* QSPI module.
|
||||
*/
|
||||
#define MCFQSPI_BASE (MCF_IPSBAR + 0x340)
|
||||
#define MCFQSPI_SIZE 0x40
|
||||
|
||||
#define MCFQSPI_CS0 91
|
||||
#define MCFQSPI_CS1 92
|
||||
#define MCFQSPI_CS2 103
|
||||
#define MCFQSPI_CS3 99
|
||||
|
||||
/*
|
||||
* GPIO module.
|
||||
*/
|
||||
|
|
|
@ -21,7 +21,7 @@
|
|||
#ifndef mcfqspi_h
|
||||
#define mcfqspi_h
|
||||
|
||||
#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x)
|
||||
#if defined(CONFIG_M527x) || defined(CONFIG_M528x)
|
||||
#define MCFQSPI_IOBASE (MCF_IPSBAR + 0x340)
|
||||
#elif defined(CONFIG_M5249)
|
||||
#define MCFQSPI_IOBASE (MCF_MBAR + 0x300)
|
||||
|
|
|
@ -29,22 +29,17 @@
|
|||
#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
|
||||
static struct resource m523x_qspi_resources[] = {
|
||||
{
|
||||
.start = MCFQSPI_IOBASE,
|
||||
.end = MCFQSPI_IOBASE + MCFQSPI_IOSIZE - 1,
|
||||
.start = MCFQSPI_BASE,
|
||||
.end = MCFQSPI_BASE + MCFQSPI_SIZE - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
{
|
||||
.start = MCFINT_VECBASE + MCFINT_QSPI,
|
||||
.end = MCFINT_VECBASE + MCFINT_QSPI,
|
||||
.start = MCF_IRQ_QSPI,
|
||||
.end = MCF_IRQ_QSPI,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
#define MCFQSPI_CS0 91
|
||||
#define MCFQSPI_CS1 92
|
||||
#define MCFQSPI_CS2 103
|
||||
#define MCFQSPI_CS3 99
|
||||
|
||||
static int m523x_cs_setup(struct mcfqspi_cs_control *cs_control)
|
||||
{
|
||||
int status;
|
||||
|
|
Loading…
Reference in a new issue