ASoC: arizona: Use async writes
Where possible write to the device asynchronously, allowing better performance when used with a bus like SPI which supports this by minimising the need to context switch back to the driver to get the next bit of data. Signed-off-by: Mark Brown <broonie@linaro.org> Tested-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com> Reviewed-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com>
This commit is contained in:
Mark Brown
parent
d733dc0828
commit
3c43c69537
1 changed files with 89 additions and 74 deletions
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@ -93,7 +93,7 @@ static int arizona_spk_ev(struct snd_soc_dapm_widget *w,
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switch (event) {
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case SND_SOC_DAPM_PRE_PMU:
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if (!priv->spk_ena && manual_ena) {
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snd_soc_write(codec, 0x4f5, 0x25a);
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regmap_write_async(arizona->regmap, 0x4f5, 0x25a);
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priv->spk_ena_pending = true;
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}
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break;
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@ -105,12 +105,13 @@ static int arizona_spk_ev(struct snd_soc_dapm_widget *w,
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return -EBUSY;
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}
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snd_soc_update_bits(codec, ARIZONA_OUTPUT_ENABLES_1,
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1 << w->shift, 1 << w->shift);
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regmap_update_bits_async(arizona->regmap,
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ARIZONA_OUTPUT_ENABLES_1,
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1 << w->shift, 1 << w->shift);
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if (priv->spk_ena_pending) {
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msleep(75);
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snd_soc_write(codec, 0x4f5, 0xda);
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regmap_write_async(arizona->regmap, 0x4f5, 0xda);
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priv->spk_ena_pending = false;
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priv->spk_ena++;
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}
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@ -119,16 +120,19 @@ static int arizona_spk_ev(struct snd_soc_dapm_widget *w,
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if (manual_ena) {
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priv->spk_ena--;
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if (!priv->spk_ena)
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snd_soc_write(codec, 0x4f5, 0x25a);
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regmap_write_async(arizona->regmap,
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0x4f5, 0x25a);
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}
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snd_soc_update_bits(codec, ARIZONA_OUTPUT_ENABLES_1,
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1 << w->shift, 0);
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regmap_update_bits_async(arizona->regmap,
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ARIZONA_OUTPUT_ENABLES_1,
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1 << w->shift, 0);
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break;
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case SND_SOC_DAPM_POST_PMD:
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if (manual_ena) {
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if (!priv->spk_ena)
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snd_soc_write(codec, 0x4f5, 0x0da);
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regmap_write_async(arizona->regmap,
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0x4f5, 0x0da);
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}
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break;
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}
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@ -687,6 +691,7 @@ int arizona_hp_ev(struct snd_soc_dapm_widget *w,
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int event)
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{
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struct arizona_priv *priv = snd_soc_codec_get_drvdata(w->codec);
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struct arizona *arizona = priv->arizona;
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unsigned int mask = 1 << w->shift;
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unsigned int val;
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@ -709,7 +714,8 @@ int arizona_hp_ev(struct snd_soc_dapm_widget *w,
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if (priv->arizona->hpdet_magic)
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val = 0;
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snd_soc_update_bits(w->codec, ARIZONA_OUTPUT_ENABLES_1, mask, val);
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regmap_update_bits_async(arizona->regmap, ARIZONA_OUTPUT_ENABLES_1,
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mask, val);
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return arizona_out_ev(w, kcontrol, event);
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}
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@ -864,6 +870,8 @@ EXPORT_SYMBOL_GPL(arizona_set_sysclk);
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static int arizona_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
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{
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struct snd_soc_codec *codec = dai->codec;
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struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
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struct arizona *arizona = priv->arizona;
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int lrclk, bclk, mode, base;
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base = dai->driver->base;
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@ -920,17 +928,19 @@ static int arizona_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
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return -EINVAL;
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}
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snd_soc_update_bits(codec, base + ARIZONA_AIF_BCLK_CTRL,
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ARIZONA_AIF1_BCLK_INV | ARIZONA_AIF1_BCLK_MSTR,
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bclk);
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snd_soc_update_bits(codec, base + ARIZONA_AIF_TX_PIN_CTRL,
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ARIZONA_AIF1TX_LRCLK_INV |
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ARIZONA_AIF1TX_LRCLK_MSTR, lrclk);
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snd_soc_update_bits(codec, base + ARIZONA_AIF_RX_PIN_CTRL,
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ARIZONA_AIF1RX_LRCLK_INV |
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ARIZONA_AIF1RX_LRCLK_MSTR, lrclk);
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snd_soc_update_bits(codec, base + ARIZONA_AIF_FORMAT,
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ARIZONA_AIF1_FMT_MASK, mode);
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regmap_update_bits_async(arizona->regmap, base + ARIZONA_AIF_BCLK_CTRL,
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ARIZONA_AIF1_BCLK_INV |
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ARIZONA_AIF1_BCLK_MSTR,
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bclk);
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regmap_update_bits_async(arizona->regmap, base + ARIZONA_AIF_TX_PIN_CTRL,
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ARIZONA_AIF1TX_LRCLK_INV |
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ARIZONA_AIF1TX_LRCLK_MSTR, lrclk);
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regmap_update_bits_async(arizona->regmap,
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base + ARIZONA_AIF_RX_PIN_CTRL,
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ARIZONA_AIF1RX_LRCLK_INV |
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ARIZONA_AIF1RX_LRCLK_MSTR, lrclk);
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regmap_update_bits(arizona->regmap, base + ARIZONA_AIF_FORMAT,
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ARIZONA_AIF1_FMT_MASK, mode);
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return 0;
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}
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@ -1182,18 +1192,22 @@ static int arizona_hw_params(struct snd_pcm_substream *substream,
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if (ret != 0)
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return ret;
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snd_soc_update_bits(codec, base + ARIZONA_AIF_BCLK_CTRL,
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ARIZONA_AIF1_BCLK_FREQ_MASK, bclk);
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snd_soc_update_bits(codec, base + ARIZONA_AIF_TX_BCLK_RATE,
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ARIZONA_AIF1TX_BCPF_MASK, lrclk);
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snd_soc_update_bits(codec, base + ARIZONA_AIF_RX_BCLK_RATE,
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ARIZONA_AIF1RX_BCPF_MASK, lrclk);
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snd_soc_update_bits(codec, base + ARIZONA_AIF_FRAME_CTRL_1,
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ARIZONA_AIF1TX_WL_MASK |
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ARIZONA_AIF1TX_SLOT_LEN_MASK, frame);
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snd_soc_update_bits(codec, base + ARIZONA_AIF_FRAME_CTRL_2,
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ARIZONA_AIF1RX_WL_MASK |
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ARIZONA_AIF1RX_SLOT_LEN_MASK, frame);
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regmap_update_bits_async(arizona->regmap,
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base + ARIZONA_AIF_BCLK_CTRL,
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ARIZONA_AIF1_BCLK_FREQ_MASK, bclk);
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regmap_update_bits_async(arizona->regmap,
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base + ARIZONA_AIF_TX_BCLK_RATE,
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ARIZONA_AIF1TX_BCPF_MASK, lrclk);
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regmap_update_bits_async(arizona->regmap,
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base + ARIZONA_AIF_RX_BCLK_RATE,
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ARIZONA_AIF1RX_BCPF_MASK, lrclk);
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regmap_update_bits_async(arizona->regmap,
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base + ARIZONA_AIF_FRAME_CTRL_1,
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ARIZONA_AIF1TX_WL_MASK |
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ARIZONA_AIF1TX_SLOT_LEN_MASK, frame);
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regmap_update_bits(arizona->regmap, base + ARIZONA_AIF_FRAME_CTRL_2,
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ARIZONA_AIF1RX_WL_MASK |
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ARIZONA_AIF1RX_SLOT_LEN_MASK, frame);
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return 0;
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}
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@ -1446,31 +1460,31 @@ static void arizona_apply_fll(struct arizona *arizona, unsigned int base,
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struct arizona_fll_cfg *cfg, int source,
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bool sync)
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{
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regmap_update_bits(arizona->regmap, base + 3,
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ARIZONA_FLL1_THETA_MASK, cfg->theta);
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regmap_update_bits(arizona->regmap, base + 4,
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ARIZONA_FLL1_LAMBDA_MASK, cfg->lambda);
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regmap_update_bits(arizona->regmap, base + 5,
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ARIZONA_FLL1_FRATIO_MASK,
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cfg->fratio << ARIZONA_FLL1_FRATIO_SHIFT);
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regmap_update_bits(arizona->regmap, base + 6,
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ARIZONA_FLL1_CLK_REF_DIV_MASK |
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ARIZONA_FLL1_CLK_REF_SRC_MASK,
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cfg->refdiv << ARIZONA_FLL1_CLK_REF_DIV_SHIFT |
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source << ARIZONA_FLL1_CLK_REF_SRC_SHIFT);
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regmap_update_bits_async(arizona->regmap, base + 3,
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ARIZONA_FLL1_THETA_MASK, cfg->theta);
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regmap_update_bits_async(arizona->regmap, base + 4,
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ARIZONA_FLL1_LAMBDA_MASK, cfg->lambda);
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regmap_update_bits_async(arizona->regmap, base + 5,
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ARIZONA_FLL1_FRATIO_MASK,
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cfg->fratio << ARIZONA_FLL1_FRATIO_SHIFT);
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regmap_update_bits_async(arizona->regmap, base + 6,
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ARIZONA_FLL1_CLK_REF_DIV_MASK |
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ARIZONA_FLL1_CLK_REF_SRC_MASK,
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cfg->refdiv << ARIZONA_FLL1_CLK_REF_DIV_SHIFT |
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source << ARIZONA_FLL1_CLK_REF_SRC_SHIFT);
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if (sync)
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regmap_update_bits(arizona->regmap, base + 0x7,
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ARIZONA_FLL1_GAIN_MASK,
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cfg->gain << ARIZONA_FLL1_GAIN_SHIFT);
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regmap_update_bits_async(arizona->regmap, base + 0x7,
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ARIZONA_FLL1_GAIN_MASK,
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cfg->gain << ARIZONA_FLL1_GAIN_SHIFT);
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else
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regmap_update_bits(arizona->regmap, base + 0x9,
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ARIZONA_FLL1_GAIN_MASK,
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cfg->gain << ARIZONA_FLL1_GAIN_SHIFT);
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regmap_update_bits_async(arizona->regmap, base + 0x9,
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ARIZONA_FLL1_GAIN_MASK,
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cfg->gain << ARIZONA_FLL1_GAIN_SHIFT);
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regmap_update_bits(arizona->regmap, base + 2,
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ARIZONA_FLL1_CTRL_UPD | ARIZONA_FLL1_N_MASK,
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ARIZONA_FLL1_CTRL_UPD | cfg->n);
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regmap_update_bits_async(arizona->regmap, base + 2,
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ARIZONA_FLL1_CTRL_UPD | ARIZONA_FLL1_N_MASK,
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ARIZONA_FLL1_CTRL_UPD | cfg->n);
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}
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static bool arizona_is_enabled_fll(struct arizona_fll *fll)
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@ -1503,9 +1517,9 @@ static void arizona_enable_fll(struct arizona_fll *fll,
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*/
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if (fll->ref_src >= 0 && fll->ref_freq &&
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fll->ref_src != fll->sync_src) {
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regmap_update_bits(arizona->regmap, fll->base + 5,
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ARIZONA_FLL1_OUTDIV_MASK,
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ref->outdiv << ARIZONA_FLL1_OUTDIV_SHIFT);
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regmap_update_bits_async(arizona->regmap, fll->base + 5,
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ARIZONA_FLL1_OUTDIV_MASK,
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ref->outdiv << ARIZONA_FLL1_OUTDIV_SHIFT);
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arizona_apply_fll(arizona, fll->base, ref, fll->ref_src,
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false);
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@ -1515,15 +1529,15 @@ static void arizona_enable_fll(struct arizona_fll *fll,
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use_sync = true;
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}
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} else if (fll->sync_src >= 0) {
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regmap_update_bits(arizona->regmap, fll->base + 5,
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ARIZONA_FLL1_OUTDIV_MASK,
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sync->outdiv << ARIZONA_FLL1_OUTDIV_SHIFT);
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regmap_update_bits_async(arizona->regmap, fll->base + 5,
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ARIZONA_FLL1_OUTDIV_MASK,
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sync->outdiv << ARIZONA_FLL1_OUTDIV_SHIFT);
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arizona_apply_fll(arizona, fll->base, sync,
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fll->sync_src, false);
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regmap_update_bits(arizona->regmap, fll->base + 0x11,
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ARIZONA_FLL1_SYNC_ENA, 0);
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regmap_update_bits_async(arizona->regmap, fll->base + 0x11,
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ARIZONA_FLL1_SYNC_ENA, 0);
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} else {
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arizona_fll_err(fll, "No clocks provided\n");
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return;
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@ -1534,11 +1548,12 @@ static void arizona_enable_fll(struct arizona_fll *fll,
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* sync source.
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*/
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if (use_sync && fll->sync_freq > 100000)
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regmap_update_bits(arizona->regmap, fll->base + 0x17,
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ARIZONA_FLL1_SYNC_BW, 0);
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regmap_update_bits_async(arizona->regmap, fll->base + 0x17,
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ARIZONA_FLL1_SYNC_BW, 0);
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else
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regmap_update_bits(arizona->regmap, fll->base + 0x17,
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ARIZONA_FLL1_SYNC_BW, ARIZONA_FLL1_SYNC_BW);
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regmap_update_bits_async(arizona->regmap, fll->base + 0x17,
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ARIZONA_FLL1_SYNC_BW,
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ARIZONA_FLL1_SYNC_BW);
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if (!arizona_is_enabled_fll(fll))
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pm_runtime_get(arizona->dev);
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@ -1546,14 +1561,14 @@ static void arizona_enable_fll(struct arizona_fll *fll,
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/* Clear any pending completions */
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try_wait_for_completion(&fll->ok);
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regmap_update_bits(arizona->regmap, fll->base + 1,
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ARIZONA_FLL1_FREERUN, 0);
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regmap_update_bits(arizona->regmap, fll->base + 1,
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ARIZONA_FLL1_ENA, ARIZONA_FLL1_ENA);
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regmap_update_bits_async(arizona->regmap, fll->base + 1,
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ARIZONA_FLL1_FREERUN, 0);
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regmap_update_bits_async(arizona->regmap, fll->base + 1,
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ARIZONA_FLL1_ENA, ARIZONA_FLL1_ENA);
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if (use_sync)
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regmap_update_bits(arizona->regmap, fll->base + 0x11,
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ARIZONA_FLL1_SYNC_ENA,
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ARIZONA_FLL1_SYNC_ENA);
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regmap_update_bits_async(arizona->regmap, fll->base + 0x11,
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ARIZONA_FLL1_SYNC_ENA,
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ARIZONA_FLL1_SYNC_ENA);
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ret = wait_for_completion_timeout(&fll->ok,
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msecs_to_jiffies(250));
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@ -1566,8 +1581,8 @@ static void arizona_disable_fll(struct arizona_fll *fll)
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struct arizona *arizona = fll->arizona;
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bool change;
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regmap_update_bits(arizona->regmap, fll->base + 1,
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ARIZONA_FLL1_FREERUN, ARIZONA_FLL1_FREERUN);
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regmap_update_bits_async(arizona->regmap, fll->base + 1,
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ARIZONA_FLL1_FREERUN, ARIZONA_FLL1_FREERUN);
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regmap_update_bits_check(arizona->regmap, fll->base + 1,
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ARIZONA_FLL1_ENA, 0, &change);
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regmap_update_bits(arizona->regmap, fll->base + 0x11,
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