[PARISC] Abstract shift register left in .S
Abstract existing shift register left macros as shift register right are. This lends itself to a nice clean up of some #ifdef blocks in entry.S Signed-off-by: Kyle McMartin <kyle@parisc-linux.org>
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2 changed files with 8 additions and 17 deletions
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@ -30,6 +30,7 @@
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#include <asm/psw.h>
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#include <asm/cache.h> /* for L1_CACHE_SHIFT */
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#include <asm/assembly.h> /* for LDREG/STREG defines */
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#include <asm/pgtable.h>
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#include <asm/signal.h>
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@ -478,11 +479,7 @@
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bb,>=,n \pmd,_PxD_PRESENT_BIT,\fault
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DEP %r0,31,PxD_FLAG_SHIFT,\pmd /* clear flags */
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copy \pmd,%r9
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#ifdef CONFIG_64BIT
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shld %r9,PxD_VALUE_SHIFT,\pmd
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#else
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shlw %r9,PxD_VALUE_SHIFT,\pmd
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#endif
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SHLREG %r9,PxD_VALUE_SHIFT,\pmd
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EXTR \va,31-PAGE_SHIFT,ASM_BITS_PER_PTE,\index
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DEP %r0,31,PAGE_SHIFT,\pmd /* clear offset */
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shladd \index,BITS_PER_PTE_ENTRY,\pmd,\pmd
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@ -970,11 +967,7 @@ intr_return:
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/* shift left ____cacheline_aligned (aka L1_CACHE_BYTES) amount
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** irq_stat[] is defined using ____cacheline_aligned.
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*/
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#ifdef CONFIG_64BIT
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shld %r1, 6, %r20
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#else
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shlw %r1, 5, %r20
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#endif
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SHLREG %r1,L1_CACHE_SHIFT,%r20
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add %r19,%r20,%r19 /* now have &irq_stat[smp_processor_id()] */
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#endif /* CONFIG_SMP */
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@ -2115,11 +2108,7 @@ syscall_check_bh:
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ldw TI_CPU-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r26 /* cpu # */
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/* shift left ____cacheline_aligned (aka L1_CACHE_BYTES) bits */
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#ifdef CONFIG_64BIT
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shld %r26, 6, %r20
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#else
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shlw %r26, 5, %r20
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#endif
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SHLREG %r26,L1_CACHE_SHIFT,%r20
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add %r19,%r20,%r19 /* now have &irq_stat[smp_processor_id()] */
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#endif /* CONFIG_SMP */
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@ -29,7 +29,8 @@
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#define LDREGX ldd,s
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#define LDREGM ldd,mb
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#define STREGM std,ma
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#define SHRREG shrd
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#define SHRREG shrd
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#define SHLREG shld
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#define RP_OFFSET 16
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#define FRAME_SIZE 128
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#define CALLEE_REG_FRAME_SIZE 144
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@ -39,7 +40,8 @@
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#define LDREGX ldwx,s
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#define LDREGM ldwm
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#define STREGM stwm
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#define SHRREG shr
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#define SHRREG shr
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#define SHLREG shlw
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#define RP_OFFSET 20
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#define FRAME_SIZE 64
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#define CALLEE_REG_FRAME_SIZE 128
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