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locking/Documentation: Fix formatting inconsistencies

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Signed-off-by: SeongJae Park <sj38.park@gmail.com>
Signed-off-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
Acked-by: David Howells <dhowells@redhat.com>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: bobby.prani@gmail.com
Cc: dipankar@in.ibm.com
Cc: dvhart@linux.intel.com
Cc: edumazet@google.com
Cc: fweisbec@gmail.com
Cc: jiangshanlai@gmail.com
Cc: josh@joshtriplett.org
Cc: mathieu.desnoyers@efficios.com
Cc: oleg@redhat.com
Cc: rostedt@goodmis.org
Link: http://lkml.kernel.org/r/1460476375-27803-4-git-send-email-paulmck@linux.vnet.ibm.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
This commit is contained in:
SeongJae Park 2016-04-12 08:52:52 -07:00 committed by Ingo Molnar
parent 01e1cd6de8
commit 3dbf0913f6
1 changed files with 4 additions and 4 deletions
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8
Documentation/memory-barriers.txt
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@ -149,7 +149,7 @@ As a further example, consider this sequence of events:
CPU 1 CPU 2 CPU 1 CPU 2
=============== =============== =============== ===============
{ A == 1, B == 2, C = 3, P == &A, Q == &C } { A == 1, B == 2, C == 3, P == &A, Q == &C }
B = 4; Q = P; B = 4; Q = P;
P = &B D = *Q; P = &B D = *Q;
@ -518,7 +518,7 @@ following sequence of events:
CPU 1 CPU 2 CPU 1 CPU 2
=============== =============== =============== ===============
{ A == 1, B == 2, C = 3, P == &A, Q == &C } { A == 1, B == 2, C == 3, P == &A, Q == &C }
B = 4; B = 4;
<write barrier> <write barrier>
WRITE_ONCE(P, &B) WRITE_ONCE(P, &B)
@ -545,7 +545,7 @@ between the address load and the data load:
CPU 1 CPU 2 CPU 1 CPU 2
=============== =============== =============== ===============
{ A == 1, B == 2, C = 3, P == &A, Q == &C } { A == 1, B == 2, C == 3, P == &A, Q == &C }
B = 4; B = 4;
<write barrier> <write barrier>
WRITE_ONCE(P, &B); WRITE_ONCE(P, &B);
@ -3043,7 +3043,7 @@ The Alpha defines the Linux kernel's memory barrier model.
See the subsection on "Cache Coherency" above. See the subsection on "Cache Coherency" above.
VIRTUAL MACHINE GUESTS VIRTUAL MACHINE GUESTS
------------------- ----------------------
Guests running within virtual machines might be affected by SMP effects even if Guests running within virtual machines might be affected by SMP effects even if
the guest itself is compiled without SMP support. This is an artifact of the guest itself is compiled without SMP support. This is an artifact of