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[media] drx-j: CodingStyle fixes

Browse source 
Do the automatic CodingStyle fixes found at Lindent.

No functional changes.

Acked-by: Devin Heitmueller <dheitmueller@kernellabs.com>
Signed-off-by: Mauro Carvalho Chehab <m.chehab@samsung.com>
This commit is contained in:
Mauro Carvalho Chehab 2012-03-20 00:00:42 -03:00 committed by Mauro Carvalho Chehab
parent ca3355a947
commit 443f18d0d5
19 changed files with 25601 additions and 20641 deletions
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16
drivers/media/dvb-frontends/drx39xyj/bsp_host.h
View file

@ -50,7 +50,6 @@ extern "C" {
TYPEDEFS
-------------------------------------------------------------------------*/
/*-------------------------------------------------------------------------
DEFINES
-------------------------------------------------------------------------*/
@ -58,17 +57,17 @@ DEFINES
/*-------------------------------------------------------------------------
Exported FUNCTIONS
-------------------------------------------------------------------------*/
DRXStatus_t DRXBSP_HST_Init( void );
DRXStatus_t DRXBSP_HST_Init(void);
DRXStatus_t DRXBSP_HST_Term( void );
DRXStatus_t DRXBSP_HST_Term(void);
void* DRXBSP_HST_Memcpy( void *to, void *from, u32_t n);
void *DRXBSP_HST_Memcpy(void *to, void *from, u32_t n);
int DRXBSP_HST_Memcmp( void *s1, void *s2, u32_t n);
int DRXBSP_HST_Memcmp(void *s1, void *s2, u32_t n);
u32_t DRXBSP_HST_Clock( void );
u32_t DRXBSP_HST_Clock(void);
DRXStatus_t DRXBSP_HST_Sleep( u32_t n );
DRXStatus_t DRXBSP_HST_Sleep(u32_t n);
/*-------------------------------------------------------------------------
THE END
@ -76,5 +75,4 @@ THE END
#ifdef __cplusplus
}
#endif
#endif /* __DRXBSP_HOST_H__ */
#endif /* __DRXBSP_HOST_H__ */

46
drivers/media/dvb-frontends/drx39xyj/bsp_i2c.h
View file

@ -59,7 +59,7 @@ TYPEDEFS
* \typedef I2Caddr_t
* \brief I2C device address (7-bit or 10-bit)
*/
typedef u16_t I2Caddr_t;
typedef u16_t I2Caddr_t;
/**
* \typedef I2CdevId_t
@ -71,7 +71,7 @@ typedef u16_t I2Caddr_t;
* I2C bus.
*
*/
typedef u16_t I2CdevId_t;
typedef u16_t I2CdevId_t;
/**
* \struct _I2CDeviceAddr_t
@ -81,11 +81,14 @@ typedef u16_t I2CdevId_t;
* The userData pointer can be used for application specific purposes.
*
*/
struct _I2CDeviceAddr_t {
I2Caddr_t i2cAddr; /**< The I2C address of the device. */
I2CdevId_t i2cDevId; /**< The device identifier. */
void *userData; /**< User data pointer */
};
struct _I2CDeviceAddr_t {
I2Caddr_t i2cAddr;
/**< The I2C address of the device. */
I2CdevId_t i2cDevId;
/**< The device identifier. */
void *userData;
/**< User data pointer */
};
/**
* \typedef I2CDeviceAddr_t
@ -94,13 +97,13 @@ struct _I2CDeviceAddr_t {
* This structure contains the I2C address and the device ID.
*
*/
typedef struct _I2CDeviceAddr_t I2CDeviceAddr_t;
typedef struct _I2CDeviceAddr_t I2CDeviceAddr_t;
/**
* \typedef pI2CDeviceAddr_t
* \brief Pointer to I2C device parameters.
*/
typedef I2CDeviceAddr_t *pI2CDeviceAddr_t;
typedef I2CDeviceAddr_t *pI2CDeviceAddr_t;
/*------------------------------------------------------------------------------
DEFINES
@ -133,7 +136,6 @@ STRUCTS
Exported FUNCTIONS
------------------------------------------------------------------------------*/
/**
* \fn DRXBSP_I2C_Init()
* \brief Initialize I2C communication module.
@ -141,8 +143,7 @@ Exported FUNCTIONS
* \retval DRX_STS_OK Initialization successful.
* \retval DRX_STS_ERROR Initialization failed.
*/
DRXStatus_t DRXBSP_I2C_Init( void );
DRXStatus_t DRXBSP_I2C_Init(void);
/**
* \fn DRXBSP_I2C_Term()
@ -151,7 +152,7 @@ DRXStatus_t DRXBSP_I2C_Init( void );
* \retval DRX_STS_OK Termination successful.
* \retval DRX_STS_ERROR Termination failed.
*/
DRXStatus_t DRXBSP_I2C_Term( void );
DRXStatus_t DRXBSP_I2C_Term(void);
/**
* \fn DRXStatus_t DRXBSP_I2C_WriteRead( pI2CDeviceAddr_t wDevAddr,
@ -183,13 +184,11 @@ DRXStatus_t DRXBSP_I2C_Term( void );
* The device ID can be useful if several devices share an I2C address.
* It can be used to control a "switch" on the I2C bus to the correct device.
*/
DRXStatus_t DRXBSP_I2C_WriteRead( pI2CDeviceAddr_t wDevAddr,
u16_t wCount,
pu8_t wData,
pI2CDeviceAddr_t rDevAddr,
u16_t rCount,
pu8_t rData);
DRXStatus_t DRXBSP_I2C_WriteRead(pI2CDeviceAddr_t wDevAddr,
u16_t wCount,
pu8_t wData,
pI2CDeviceAddr_t rDevAddr,
u16_t rCount, pu8_t rData);
/**
* \fn DRXBSP_I2C_ErrorText()
@ -198,14 +197,13 @@ DRXStatus_t DRXBSP_I2C_WriteRead( pI2CDeviceAddr_t wDevAddr,
*
* \return char* Pointer to human readable error text.
*/
char* DRXBSP_I2C_ErrorText( void );
char *DRXBSP_I2C_ErrorText(void);
/**
* \var DRX_I2C_Error_g;
* \brief I2C specific error codes, platform dependent.
*/
extern int DRX_I2C_Error_g;
extern int DRX_I2C_Error_g;
/*------------------------------------------------------------------------------
THE END
@ -213,4 +211,4 @@ THE END
#ifdef __cplusplus
}
#endif
#endif /* __BSPI2C_H__ */
#endif /* __BSPI2C_H__ */

196
drivers/media/dvb-frontends/drx39xyj/bsp_tuner.h
View file

@ -51,24 +51,23 @@ extern "C" {
DEFINES
------------------------------------------------------------------------------*/
/* Sub-mode bits should be adjacent and incremental */
#define TUNER_MODE_SUB0 0x0001 /* for sub-mode (e.g. RF-AGC setting) */
#define TUNER_MODE_SUB1 0x0002 /* for sub-mode (e.g. RF-AGC setting) */
#define TUNER_MODE_SUB2 0x0004 /* for sub-mode (e.g. RF-AGC setting) */
#define TUNER_MODE_SUB3 0x0008 /* for sub-mode (e.g. RF-AGC setting) */
#define TUNER_MODE_SUB4 0x0010 /* for sub-mode (e.g. RF-AGC setting) */
#define TUNER_MODE_SUB5 0x0020 /* for sub-mode (e.g. RF-AGC setting) */
#define TUNER_MODE_SUB6 0x0040 /* for sub-mode (e.g. RF-AGC setting) */
#define TUNER_MODE_SUB7 0x0080 /* for sub-mode (e.g. RF-AGC setting) */
/* Sub-mode bits should be adjacent and incremental */
#define TUNER_MODE_SUB0 0x0001 /* for sub-mode (e.g. RF-AGC setting) */
#define TUNER_MODE_SUB1 0x0002 /* for sub-mode (e.g. RF-AGC setting) */
#define TUNER_MODE_SUB2 0x0004 /* for sub-mode (e.g. RF-AGC setting) */
#define TUNER_MODE_SUB3 0x0008 /* for sub-mode (e.g. RF-AGC setting) */
#define TUNER_MODE_SUB4 0x0010 /* for sub-mode (e.g. RF-AGC setting) */
#define TUNER_MODE_SUB5 0x0020 /* for sub-mode (e.g. RF-AGC setting) */
#define TUNER_MODE_SUB6 0x0040 /* for sub-mode (e.g. RF-AGC setting) */
#define TUNER_MODE_SUB7 0x0080 /* for sub-mode (e.g. RF-AGC setting) */
#define TUNER_MODE_DIGITAL 0x0100 /* for digital channel (e.g. DVB-T) */
#define TUNER_MODE_ANALOG 0x0200 /* for analog channel (e.g. PAL) */
#define TUNER_MODE_SWITCH 0x0400 /* during channel switch & scanning */
#define TUNER_MODE_LOCK 0x0800 /* after tuner has locked */
#define TUNER_MODE_6MHZ 0x1000 /* for 6MHz bandwidth channels */
#define TUNER_MODE_7MHZ 0x2000 /* for 7MHz bandwidth channels */
#define TUNER_MODE_8MHZ 0x4000 /* for 8MHz bandwidth channels */
#define TUNER_MODE_DIGITAL 0x0100 /* for digital channel (e.g. DVB-T) */
#define TUNER_MODE_ANALOG 0x0200 /* for analog channel (e.g. PAL) */
#define TUNER_MODE_SWITCH 0x0400 /* during channel switch & scanning */
#define TUNER_MODE_LOCK 0x0800 /* after tuner has locked */
#define TUNER_MODE_6MHZ 0x1000 /* for 6MHz bandwidth channels */
#define TUNER_MODE_7MHZ 0x2000 /* for 7MHz bandwidth channels */
#define TUNER_MODE_8MHZ 0x4000 /* for 8MHz bandwidth channels */
#define TUNER_MODE_SUB_MAX 8
#define TUNER_MODE_SUBALL ( TUNER_MODE_SUB0 | TUNER_MODE_SUB1 | \
@ -80,92 +79,90 @@ DEFINES
TYPEDEFS
------------------------------------------------------------------------------*/
typedef u32_t TUNERMode_t;
typedef pu32_t pTUNERMode_t;
typedef u32_t TUNERMode_t;
typedef pu32_t pTUNERMode_t;
typedef char* TUNERSubMode_t; /* description of submode */
typedef TUNERSubMode_t *pTUNERSubMode_t;
typedef char *TUNERSubMode_t; /* description of submode */
typedef TUNERSubMode_t *pTUNERSubMode_t;
typedef enum {
typedef enum {
TUNER_LOCKED,
TUNER_NOT_LOCKED
} TUNERLockStatus_t, *pTUNERLockStatus_t;
TUNER_LOCKED,
TUNER_NOT_LOCKED
typedef struct {
} TUNERLockStatus_t, *pTUNERLockStatus_t;
char *name; /* Tuner brand & type name */
DRXFrequency_t minFreqRF; /* Lowest RF input frequency, in kHz */
DRXFrequency_t maxFreqRF; /* Highest RF input frequency, in kHz */
u8_t subMode; /* Index to sub-mode in use */
pTUNERSubMode_t subModeDescriptions; /* Pointer to description of sub-modes */
u8_t subModes; /* Number of available sub-modes */
typedef struct {
/* The following fields will be either 0, NULL or FALSE and do not need
initialisation */
void *selfCheck; /* gives proof of initialization */
Bool_t programmed; /* only valid if selfCheck is OK */
DRXFrequency_t RFfrequency; /* only valid if programmed */
DRXFrequency_t IFfrequency; /* only valid if programmed */
char *name; /* Tuner brand & type name */
DRXFrequency_t minFreqRF; /* Lowest RF input frequency, in kHz */
DRXFrequency_t maxFreqRF; /* Highest RF input frequency, in kHz */
u8_t subMode; /* Index to sub-mode in use */
pTUNERSubMode_t subModeDescriptions; /* Pointer to description of sub-modes*/
u8_t subModes; /* Number of available sub-modes */
/* The following fields will be either 0, NULL or FALSE and do not need
initialisation */
void *selfCheck; /* gives proof of initialization */
Bool_t programmed; /* only valid if selfCheck is OK */
DRXFrequency_t RFfrequency; /* only valid if programmed */
DRXFrequency_t IFfrequency; /* only valid if programmed */
void* myUserData; /* pointer to associated demod instance */
u16_t myCapabilities; /* value for storing application flags */
} TUNERCommonAttr_t, *pTUNERCommonAttr_t;
void *myUserData; /* pointer to associated demod instance */
u16_t myCapabilities; /* value for storing application flags */
} TUNERCommonAttr_t, *pTUNERCommonAttr_t;
/*
* Generic functions for DRX devices.
*/
typedef struct TUNERInstance_s *pTUNERInstance_t;
typedef struct TUNERInstance_s *pTUNERInstance_t;
typedef DRXStatus_t (*TUNEROpenFunc_t)( pTUNERInstance_t tuner );
typedef DRXStatus_t (*TUNERCloseFunc_t)( pTUNERInstance_t tuner );
typedef DRXStatus_t(*TUNEROpenFunc_t) (pTUNERInstance_t tuner);
typedef DRXStatus_t(*TUNERCloseFunc_t) (pTUNERInstance_t tuner);
typedef DRXStatus_t (*TUNERSetFrequencyFunc_t)( pTUNERInstance_t tuner,
TUNERMode_t mode,
DRXFrequency_t frequency );
typedef DRXStatus_t(*TUNERSetFrequencyFunc_t) (pTUNERInstance_t tuner,
TUNERMode_t mode,
DRXFrequency_t
frequency);
typedef DRXStatus_t (*TUNERGetFrequencyFunc_t)( pTUNERInstance_t tuner,
TUNERMode_t mode,
pDRXFrequency_t RFfrequency,
pDRXFrequency_t IFfrequency );
typedef DRXStatus_t(*TUNERGetFrequencyFunc_t) (pTUNERInstance_t tuner,
TUNERMode_t mode,
pDRXFrequency_t
RFfrequency,
pDRXFrequency_t
IFfrequency);
typedef DRXStatus_t (*TUNERLockStatusFunc_t)( pTUNERInstance_t tuner,
pTUNERLockStatus_t lockStat );
typedef DRXStatus_t(*TUNERLockStatusFunc_t) (pTUNERInstance_t tuner,
pTUNERLockStatus_t
lockStat);
typedef DRXStatus_t (*TUNERi2cWriteReadFunc_t)( pTUNERInstance_t tuner,
pI2CDeviceAddr_t wDevAddr,
u16_t wCount,
pu8_t wData,
pI2CDeviceAddr_t rDevAddr,
u16_t rCount,
pu8_t rData );
typedef DRXStatus_t(*TUNERi2cWriteReadFunc_t) (pTUNERInstance_t tuner,
pI2CDeviceAddr_t
wDevAddr, u16_t wCount,
pu8_t wData,
pI2CDeviceAddr_t
rDevAddr, u16_t rCount,
pu8_t rData);
typedef struct
{
TUNEROpenFunc_t openFunc;
TUNERCloseFunc_t closeFunc;
TUNERSetFrequencyFunc_t setFrequencyFunc;
TUNERGetFrequencyFunc_t getFrequencyFunc;
TUNERLockStatusFunc_t lockStatusFunc;
TUNERi2cWriteReadFunc_t i2cWriteReadFunc;
typedef struct {
TUNEROpenFunc_t openFunc;
TUNERCloseFunc_t closeFunc;
TUNERSetFrequencyFunc_t setFrequencyFunc;
TUNERGetFrequencyFunc_t getFrequencyFunc;
TUNERLockStatusFunc_t lockStatusFunc;
TUNERi2cWriteReadFunc_t i2cWriteReadFunc;
} TUNERFunc_t, *pTUNERFunc_t;
} TUNERFunc_t, *pTUNERFunc_t;
typedef struct TUNERInstance_s {
typedef struct TUNERInstance_s {
I2CDeviceAddr_t myI2CDevAddr;
pTUNERCommonAttr_t myCommonAttr;
void* myExtAttr;
pTUNERFunc_t myFunct;
} TUNERInstance_t;
I2CDeviceAddr_t myI2CDevAddr;
pTUNERCommonAttr_t myCommonAttr;
void *myExtAttr;
pTUNERFunc_t myFunct;
} TUNERInstance_t;
/*------------------------------------------------------------------------------
ENUM
@ -175,34 +172,32 @@ ENUM
STRUCTS
------------------------------------------------------------------------------*/
/*------------------------------------------------------------------------------
Exported FUNCTIONS
------------------------------------------------------------------------------*/
DRXStatus_t DRXBSP_TUNER_Open( pTUNERInstance_t tuner );
DRXStatus_t DRXBSP_TUNER_Open(pTUNERInstance_t tuner);
DRXStatus_t DRXBSP_TUNER_Close( pTUNERInstance_t tuner );
DRXStatus_t DRXBSP_TUNER_Close(pTUNERInstance_t tuner);
DRXStatus_t DRXBSP_TUNER_SetFrequency( pTUNERInstance_t tuner,
TUNERMode_t mode,
DRXFrequency_t frequency );
DRXStatus_t DRXBSP_TUNER_SetFrequency(pTUNERInstance_t tuner,
TUNERMode_t mode,
DRXFrequency_t frequency);
DRXStatus_t DRXBSP_TUNER_GetFrequency( pTUNERInstance_t tuner,
TUNERMode_t mode,
pDRXFrequency_t RFfrequency,
pDRXFrequency_t IFfrequency );
DRXStatus_t DRXBSP_TUNER_GetFrequency(pTUNERInstance_t tuner,
TUNERMode_t mode,
pDRXFrequency_t RFfrequency,
pDRXFrequency_t IFfrequency);
DRXStatus_t DRXBSP_TUNER_LockStatus( pTUNERInstance_t tuner,
pTUNERLockStatus_t lockStat );
DRXStatus_t DRXBSP_TUNER_LockStatus(pTUNERInstance_t tuner,
pTUNERLockStatus_t lockStat);
DRXStatus_t DRXBSP_TUNER_DefaultI2CWriteRead( pTUNERInstance_t tuner,
pI2CDeviceAddr_t wDevAddr,
u16_t wCount,
pu8_t wData,
pI2CDeviceAddr_t rDevAddr,
u16_t rCount,
pu8_t rData);
DRXStatus_t DRXBSP_TUNER_DefaultI2CWriteRead(pTUNERInstance_t tuner,
pI2CDeviceAddr_t wDevAddr,
u16_t wCount,
pu8_t wData,
pI2CDeviceAddr_t rDevAddr,
u16_t rCount, pu8_t rData);
/*------------------------------------------------------------------------------
THE END
@ -210,6 +205,5 @@ THE END
#ifdef __cplusplus
}
#endif
#endif /* __DRXBSP_TUNER_H__ */
#endif /* __DRXBSP_TUNER_H__ */
/* End of file */

86
drivers/media/dvb-frontends/drx39xyj/bsp_types.h
View file

@ -56,114 +56,113 @@ TYPEDEFS
* \typedef unsigned char u8_t
* \brief type definition of an unsigned 8 bits integer
*/
typedef unsigned char u8_t;
typedef unsigned char u8_t;
/**
* \typedef char s8_t
* \brief type definition of a signed 8 bits integer
*/
typedef char s8_t;
typedef char s8_t;
/**
* \typedef unsigned short u16_t *pu16_t
* \brief type definition of an unsigned 16 bits integer
*/
typedef unsigned short u16_t;
typedef unsigned short u16_t;
/**
* \typedef short s16_t
* \brief type definition of a signed 16 bits integer
*/
typedef short s16_t;
typedef short s16_t;
/**
* \typedef unsigned long u32_t
* \brief type definition of an unsigned 32 bits integer
*/
typedef unsigned long u32_t;
typedef unsigned long u32_t;
/**
* \typedef long s32_t
* \brief type definition of a signed 32 bits integer
*/
typedef long s32_t;
typedef long s32_t;
/*
* \typedef struct ... u64_t
* \brief type definition of an usigned 64 bits integer
*/
typedef struct {
u32_t MSLW;
u32_t LSLW;
} u64_t;
typedef struct {
u32_t MSLW;
u32_t LSLW;
} u64_t;
/*
* \typedef struct ... i64_t
* \brief type definition of a signed 64 bits integer
*/
typedef struct {
s32_t MSLW;
u32_t LSLW;
} s64_t;
typedef struct {
s32_t MSLW;
u32_t LSLW;
} s64_t;
/**
* \typedef u8_t *pu8_t
* \brief type definition of pointer to an unsigned 8 bits integer
*/
typedef u8_t *pu8_t;
typedef u8_t *pu8_t;
/**
* \typedef s8_t *ps8_t
* \brief type definition of pointer to a signed 8 bits integer
*/
typedef s8_t *ps8_t;
typedef s8_t *ps8_t;
/**
* \typedef u16_t *pu16_t
* \brief type definition of pointer to an unsigned 16 bits integer
*/
typedef u16_t *pu16_t;
typedef u16_t *pu16_t;
/**
* \typedef s16_t *ps16_t
* \brief type definition of pointer to a signed 16 bits integer
*/
typedef s16_t *ps16_t;
typedef s16_t *ps16_t;
/**
* \typedef u32_t *pu32_t
* \brief type definition of pointer to an unsigned 32 bits integer
*/
typedef u32_t *pu32_t;
typedef u32_t *pu32_t;
/**
* \typedef s32_t *ps32_t
* \brief type definition of pointer to a signed 32 bits integer
*/
typedef s32_t *ps32_t;
typedef s32_t *ps32_t;
/**
* \typedef u64_t *pu64_t
* \brief type definition of pointer to an usigned 64 bits integer
*/
typedef u64_t *pu64_t;
typedef u64_t *pu64_t;
/**
* \typedef s64_t *ps64_t
* \brief type definition of pointer to a signed 64 bits integer
*/
typedef s64_t *ps64_t;
typedef s64_t *ps64_t;
/**
* \typedef s32_t DRXFrequency_t
* \brief type definition of frequency
*/
typedef s32_t DRXFrequency_t;
typedef s32_t DRXFrequency_t;
/**
* \typedef DRXFrequency_t *pDRXFrequency_t
* \brief type definition of a pointer to a frequency
*/
typedef DRXFrequency_t *pDRXFrequency_t;
typedef DRXFrequency_t *pDRXFrequency_t;
/**
* \typedef u32_t DRXSymbolrate_t
* \brief type definition of symbol rate
*/
typedef u32_t DRXSymbolrate_t;
typedef u32_t DRXSymbolrate_t;
/**
* \typedef DRXSymbolrate_t *pDRXSymbolrate_t
* \brief type definition of a pointer to a symbol rate
*/
typedef DRXSymbolrate_t *pDRXSymbolrate_t;
typedef DRXSymbolrate_t *pDRXSymbolrate_t;
/*-------------------------------------------------------------------------
DEFINES
@ -184,32 +183,33 @@ ENUM
* Boolean datatype. Only define if not already defined TRUE or FALSE.
*/
#if defined (TRUE) || defined (FALSE)
typedef int Bool_t;
typedef int Bool_t;
#else
/**
* \enum Bool_t
* \brief Boolean type
*/
typedef enum {
FALSE = 0,
TRUE
} Bool_t;
typedef enum {
FALSE = 0,
TRUE
} Bool_t;
#endif
typedef Bool_t *pBool_t;
typedef Bool_t *pBool_t;
/**
* \enum DRXStatus_t
* \brief Various return statusses
*/
typedef enum {
DRX_STS_READY = 3, /**< device/service is ready */
DRX_STS_BUSY = 2, /**< device/service is busy */
DRX_STS_OK = 1, /**< everything is OK */
DRX_STS_INVALID_ARG = -1, /**< invalid arguments */
DRX_STS_ERROR = -2, /**< general error */
DRX_STS_FUNC_NOT_AVAILABLE = -3 /**< unavailable functionality */
} DRXStatus_t, *pDRXStatus_t;
typedef enum {
DRX_STS_READY = 3, /**< device/service is ready */
DRX_STS_BUSY = 2, /**< device/service is busy */
DRX_STS_OK = 1, /**< everything is OK */
DRX_STS_INVALID_ARG = -1,
/**< invalid arguments */
DRX_STS_ERROR = -2, /**< general error */
DRX_STS_FUNC_NOT_AVAILABLE = -3
/**< unavailable functionality */
} DRXStatus_t, *pDRXStatus_t;
/*-------------------------------------------------------------------------
STRUCTS
@ -225,4 +225,4 @@ THE END
#ifdef __cplusplus
}
#endif
#endif /* __BSP_TYPES_H__ */
#endif /* __BSP_TYPES_H__ */

168
drivers/media/dvb-frontends/drx39xyj/drx39xxj.c
View file

@ -32,7 +32,7 @@
#include "drxj_mc.h"
#include "drxj.h"
static int drx39xxj_set_powerstate(struct dvb_frontend* fe, int enable)
static int drx39xxj_set_powerstate(struct dvb_frontend *fe, int enable)
{
struct drx39xxj_state *state = fe->demodulator_priv;
DRXDemodInstance_t *demod = state->demod;
@ -54,10 +54,10 @@ static int drx39xxj_set_powerstate(struct dvb_frontend* fe, int enable)
return 0;
}
static int drx39xxj_read_status(struct dvb_frontend* fe, fe_status_t* status)
static int drx39xxj_read_status(struct dvb_frontend *fe, fe_status_t * status)
{
struct drx39xxj_state* state = fe->demodulator_priv;
DRXDemodInstance_t *demod = state->demod;
struct drx39xxj_state *state = fe->demodulator_priv;
DRXDemodInstance_t *demod = state->demod;
DRXStatus_t result;
DRXLockStatus_t lock_status;
@ -87,16 +87,12 @@ static int drx39xxj_read_status(struct dvb_frontend* fe, fe_status_t* status)
case DRX_LOCK_STATE_8:
case DRX_LOCK_STATE_9:
*status = FE_HAS_SIGNAL
| FE_HAS_CARRIER
| FE_HAS_VITERBI
| FE_HAS_SYNC;
| FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC;
break;
case DRX_LOCKED:
*status = FE_HAS_SIGNAL
| FE_HAS_CARRIER
| FE_HAS_VITERBI
| FE_HAS_SYNC
| FE_HAS_LOCK;
| FE_HAS_CARRIER
| FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
break;
default:
printk("Lock state unknown %d\n", lock_status);
@ -105,10 +101,10 @@ static int drx39xxj_read_status(struct dvb_frontend* fe, fe_status_t* status)
return 0;
}
static int drx39xxj_read_ber(struct dvb_frontend* fe, u32* ber)
static int drx39xxj_read_ber(struct dvb_frontend *fe, u32 * ber)
{
struct drx39xxj_state* state = fe->demodulator_priv;
DRXDemodInstance_t *demod = state->demod;
struct drx39xxj_state *state = fe->demodulator_priv;
DRXDemodInstance_t *demod = state->demod;
DRXStatus_t result;
DRXSigQuality_t sig_quality;
@ -123,10 +119,11 @@ static int drx39xxj_read_ber(struct dvb_frontend* fe, u32* ber)
return 0;
}
static int drx39xxj_read_signal_strength(struct dvb_frontend* fe, u16* strength)
static int drx39xxj_read_signal_strength(struct dvb_frontend *fe,
u16 * strength)
{
struct drx39xxj_state* state = fe->demodulator_priv;
DRXDemodInstance_t *demod = state->demod;
struct drx39xxj_state *state = fe->demodulator_priv;
DRXDemodInstance_t *demod = state->demod;
DRXStatus_t result;
DRXSigQuality_t sig_quality;
@ -142,10 +139,10 @@ static int drx39xxj_read_signal_strength(struct dvb_frontend* fe, u16* strength)
return 0;
}
static int drx39xxj_read_snr(struct dvb_frontend* fe, u16* snr)
static int drx39xxj_read_snr(struct dvb_frontend *fe, u16 * snr)
{
struct drx39xxj_state* state = fe->demodulator_priv;
DRXDemodInstance_t *demod = state->demod;
struct drx39xxj_state *state = fe->demodulator_priv;
DRXDemodInstance_t *demod = state->demod;
DRXStatus_t result;
DRXSigQuality_t sig_quality;
@ -160,10 +157,10 @@ static int drx39xxj_read_snr(struct dvb_frontend* fe, u16* snr)
return 0;
}
static int drx39xxj_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
static int drx39xxj_read_ucblocks(struct dvb_frontend *fe, u32 * ucblocks)
{
struct drx39xxj_state* state = fe->demodulator_priv;
DRXDemodInstance_t *demod = state->demod;
struct drx39xxj_state *state = fe->demodulator_priv;
DRXDemodInstance_t *demod = state->demod;
DRXStatus_t result;
DRXSigQuality_t sig_quality;
@ -178,38 +175,40 @@ static int drx39xxj_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
return 0;
}
static int drx39xxj_get_frontend(struct dvb_frontend* fe, struct dvb_frontend_parameters *p)
static int drx39xxj_get_frontend(struct dvb_frontend *fe,
struct dvb_frontend_parameters *p)
{
return 0;
}
static int drx39xxj_set_frontend(struct dvb_frontend* fe, struct dvb_frontend_parameters *p)
static int drx39xxj_set_frontend(struct dvb_frontend *fe,
struct dvb_frontend_parameters *p)
{
#ifdef DJH_DEBUG
int i;
#endif
struct drx39xxj_state* state = fe->demodulator_priv;
DRXDemodInstance_t *demod = state->demod;
struct drx39xxj_state *state = fe->demodulator_priv;
DRXDemodInstance_t *demod = state->demod;
DRXStandard_t standard = DRX_STANDARD_8VSB;
DRXChannel_t channel;
DRXStatus_t result;
DRXUIOData_t uioData;
DRXChannel_t defChannel = {/* frequency */ 0,
/* bandwidth */ DRX_BANDWIDTH_6MHZ,
/* mirror */ DRX_MIRROR_NO,
/* constellation */ DRX_CONSTELLATION_AUTO,
/* hierarchy */ DRX_HIERARCHY_UNKNOWN,
/* priority */ DRX_PRIORITY_UNKNOWN,
/* coderate */ DRX_CODERATE_UNKNOWN,
/* guard */ DRX_GUARD_UNKNOWN,
/* fftmode */ DRX_FFTMODE_UNKNOWN,
/* classification */ DRX_CLASSIFICATION_AUTO,
/* symbolrate */ 5057000,
/* interleavemode */ DRX_INTERLEAVEMODE_UNKNOWN,
/* ldpc */ DRX_LDPC_UNKNOWN,
/* carrier */ DRX_CARRIER_UNKNOWN,
/* frame mode */ DRX_FRAMEMODE_UNKNOWN
};
DRXChannel_t defChannel = { /* frequency */ 0,
/* bandwidth */ DRX_BANDWIDTH_6MHZ,
/* mirror */ DRX_MIRROR_NO,
/* constellation */ DRX_CONSTELLATION_AUTO,
/* hierarchy */ DRX_HIERARCHY_UNKNOWN,
/* priority */ DRX_PRIORITY_UNKNOWN,
/* coderate */ DRX_CODERATE_UNKNOWN,
/* guard */ DRX_GUARD_UNKNOWN,
/* fftmode */ DRX_FFTMODE_UNKNOWN,
/* classification */ DRX_CLASSIFICATION_AUTO,
/* symbolrate */ 5057000,
/* interleavemode */ DRX_INTERLEAVEMODE_UNKNOWN,
/* ldpc */ DRX_LDPC_UNKNOWN,
/* carrier */ DRX_CARRIER_UNKNOWN,
/* frame mode */ DRX_FRAMEMODE_UNKNOWN
};
/* Bring the demod out of sleep */
drx39xxj_set_powerstate(fe, 1);
@ -236,9 +235,9 @@ static int drx39xxj_set_frontend(struct dvb_frontend* fe, struct dvb_frontend_pa
/* set channel parameters */
channel = defChannel;
channel.frequency = p->frequency / 1000;
channel.bandwidth = DRX_BANDWIDTH_6MHZ;
channel.constellation = DRX_CONSTELLATION_AUTO;
channel.frequency = p->frequency / 1000;
channel.bandwidth = DRX_BANDWIDTH_6MHZ;
channel.constellation = DRX_CONSTELLATION_AUTO;
/* program channel */
result = DRX_Ctrl(demod, DRX_CTRL_SET_CHANNEL, &channel);
@ -246,31 +245,28 @@ static int drx39xxj_set_frontend(struct dvb_frontend* fe, struct dvb_frontend_pa
printk("Failed to set channel!\n");
return -EINVAL;
}
// Just for giggles, let's shut off the LNA again....
uioData.uio = DRX_UIO1;
uioData.uio = DRX_UIO1;
uioData.value = FALSE;
result = DRX_Ctrl(demod, DRX_CTRL_UIO_WRITE, &uioData);
if (result != DRX_STS_OK) {
printk("Failed to disable LNA!\n");
return 0;
}
#ifdef DJH_DEBUG
for(i = 0; i < 2000; i++) {
fe_status_t status;
drx39xxj_read_status(fe, &status);
printk("i=%d status=%d\n", i, status);
msleep(100);
i += 100;
for (i = 0; i < 2000; i++) {
fe_status_t status;
drx39xxj_read_status(fe, &status);
printk("i=%d status=%d\n", i, status);
msleep(100);
i += 100;
}
#endif
return 0;
}
static int drx39xxj_sleep(struct dvb_frontend* fe)
static int drx39xxj_sleep(struct dvb_frontend *fe)
{
/* power-down the demodulator */
return drx39xxj_set_powerstate(fe, 0);
@ -308,8 +304,7 @@ static int drx39xxj_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
return 0;
}
static int drx39xxj_init(struct dvb_frontend* fe)
static int drx39xxj_init(struct dvb_frontend *fe)
{
/* Bring the demod out of sleep */
drx39xxj_set_powerstate(fe, 1);
@ -318,15 +313,15 @@ static int drx39xxj_init(struct dvb_frontend* fe)
}
static int drx39xxj_get_tune_settings(struct dvb_frontend *fe,
struct dvb_frontend_tune_settings *tune)
struct dvb_frontend_tune_settings *tune)
{
tune->min_delay_ms = 1000;
return 0;
}
static void drx39xxj_release(struct dvb_frontend* fe)
static void drx39xxj_release(struct dvb_frontend *fe)
{
struct drx39xxj_state* state = fe->demodulator_priv;
struct drx39xxj_state *state = fe->demodulator_priv;
kfree(state);
}
@ -334,31 +329,36 @@ static struct dvb_frontend_ops drx39xxj_ops;
struct dvb_frontend *drx39xxj_attach(struct i2c_adapter *i2c)
{
struct drx39xxj_state* state = NULL;
struct drx39xxj_state *state = NULL;
I2CDeviceAddr_t *demodAddr = NULL;
DRXCommonAttr_t *demodCommAttr = NULL;
DRXJData_t *demodExtAttr = NULL;
DRXDemodInstance_t *demod = NULL;
I2CDeviceAddr_t *demodAddr = NULL;
DRXCommonAttr_t *demodCommAttr = NULL;
DRXJData_t *demodExtAttr = NULL;
DRXDemodInstance_t *demod = NULL;
DRXUIOCfg_t uioCfg;
DRXUIOData_t uioData;
DRXStatus_t result;
/* allocate memory for the internal state */
state = kmalloc(sizeof(struct drx39xxj_state), GFP_KERNEL);
if (state == NULL) goto error;
if (state == NULL)
goto error;
demod = kmalloc(sizeof(DRXDemodInstance_t), GFP_KERNEL);
if (demod == NULL) goto error;
if (demod == NULL)
goto error;
demodAddr = kmalloc(sizeof(I2CDeviceAddr_t), GFP_KERNEL);
if (demodAddr == NULL) goto error;
if (demodAddr == NULL)
goto error;
demodCommAttr = kmalloc(sizeof(DRXCommonAttr_t), GFP_KERNEL);
if (demodCommAttr == NULL) goto error;
if (demodCommAttr == NULL)
goto error;
demodExtAttr = kmalloc(sizeof(DRXJData_t), GFP_KERNEL);
if (demodExtAttr == NULL) goto error;
if (demodExtAttr == NULL)
goto error;
/* setup the state */
state->i2c = i2c;
@ -374,13 +374,14 @@ struct dvb_frontend *drx39xxj_attach(struct i2c_adapter *i2c)
memcpy(demod->myCommonAttr, &DRXJDefaultCommAttr_g,
sizeof(DRXCommonAttr_t));
demod->myCommonAttr->microcode = DRXJ_MC_MAIN;
// demod->myCommonAttr->verifyMicrocode = FALSE;
// demod->myCommonAttr->verifyMicrocode = FALSE;
demod->myCommonAttr->verifyMicrocode = TRUE;
demod->myCommonAttr->intermediateFreq = 5000;
demod->myExtAttr = demodExtAttr;
memcpy(demod->myExtAttr, &DRXJData_g, sizeof(DRXJData_t));
((DRXJData_t *) demod->myExtAttr)->uioSmaTxMode = DRX_UIO_MODE_READWRITE;
((DRXJData_t *) demod->myExtAttr)->uioSmaTxMode =
DRX_UIO_MODE_READWRITE;
demod->myTuner = NULL;
@ -392,8 +393,8 @@ struct dvb_frontend *drx39xxj_attach(struct i2c_adapter *i2c)
}
/* Turn off the LNA */
uioCfg.uio = DRX_UIO1;
uioCfg.mode = DRX_UIO_MODE_READWRITE;
uioCfg.uio = DRX_UIO1;
uioCfg.mode = DRX_UIO_MODE_READWRITE;
/* Configure user-I/O #3: enable read/write */
result = DRX_Ctrl(demod, DRX_CTRL_UIO_CFG, &uioCfg);
if (result != DRX_STS_OK) {
@ -401,7 +402,7 @@ struct dvb_frontend *drx39xxj_attach(struct i2c_adapter *i2c)
return NULL;
}
uioData.uio = DRX_UIO1;
uioData.uio = DRX_UIO1;
uioData.value = FALSE;
result = DRX_Ctrl(demod, DRX_CTRL_UIO_WRITE, &uioData);
if (result != DRX_STS_OK) {
@ -427,13 +428,12 @@ error:
static struct dvb_frontend_ops drx39xxj_ops = {
.info = {
.name = "Micronas DRX39xxj family Frontend",
.type = FE_ATSC | FE_QAM,
.frequency_stepsize = 62500,
.frequency_min = 51000000,
.frequency_max = 858000000,
.caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB
},
.name = "Micronas DRX39xxj family Frontend",
.type = FE_ATSC | FE_QAM,
.frequency_stepsize = 62500,
.frequency_min = 51000000,
.frequency_max = 858000000,
.caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB},
.init = drx39xxj_init,
.i2c_gate_ctrl = drx39xxj_i2c_gate_ctrl,

2
drivers/media/dvb-frontends/drx39xyj/drx39xxj.h
View file

@ -35,6 +35,6 @@ struct drx39xxj_state {
unsigned int i2c_gate_open:1;
};
extern struct dvb_frontend* drx39xxj_attach(struct i2c_adapter *i2c);
extern struct dvb_frontend *drx39xxj_attach(struct i2c_adapter *i2c);
#endif // DVB_DUMMY_FE_H

53
drivers/media/dvb-frontends/drx39xyj/drx39xxj_dummy.c
View file

@ -13,59 +13,58 @@
#include "drx39xxj.h"
/* Dummy function to satisfy drxj.c */
DRXStatus_t DRXBSP_TUNER_Open( pTUNERInstance_t tuner )
DRXStatus_t DRXBSP_TUNER_Open(pTUNERInstance_t tuner)
{
return DRX_STS_OK;
}
DRXStatus_t DRXBSP_TUNER_Close( pTUNERInstance_t tuner )
DRXStatus_t DRXBSP_TUNER_Close(pTUNERInstance_t tuner)
{
return DRX_STS_OK;
}
DRXStatus_t DRXBSP_TUNER_SetFrequency( pTUNERInstance_t tuner,
TUNERMode_t mode,
DRXFrequency_t centerFrequency )
DRXStatus_t DRXBSP_TUNER_SetFrequency(pTUNERInstance_t tuner,
TUNERMode_t mode,
DRXFrequency_t centerFrequency)
{
return DRX_STS_OK;
}
DRXStatus_t
DRXBSP_TUNER_GetFrequency( pTUNERInstance_t tuner,
TUNERMode_t mode,
pDRXFrequency_t RFfrequency,
pDRXFrequency_t IFfrequency )
DRXBSP_TUNER_GetFrequency(pTUNERInstance_t tuner,
TUNERMode_t mode,
pDRXFrequency_t RFfrequency,
pDRXFrequency_t IFfrequency)
{
return DRX_STS_OK;
}
DRXStatus_t DRXBSP_HST_Sleep( u32_t n )
DRXStatus_t DRXBSP_HST_Sleep(u32_t n)
{
msleep(n);
return DRX_STS_OK;
}
u32_t DRXBSP_HST_Clock( void )
u32_t DRXBSP_HST_Clock(void)
{
return jiffies_to_msecs(jiffies);
}
int DRXBSP_HST_Memcmp( void *s1, void *s2, u32_t n)
int DRXBSP_HST_Memcmp(void *s1, void *s2, u32_t n)
{
return ( memcmp( s1, s2, (size_t) n) );
return (memcmp(s1, s2, (size_t) n));
}
void* DRXBSP_HST_Memcpy( void *to, void *from, u32_t n)
void *DRXBSP_HST_Memcpy(void *to, void *from, u32_t n)
{
return ( memcpy( to, from, (size_t) n) );
return (memcpy(to, from, (size_t) n));
}
DRXStatus_t DRXBSP_I2C_WriteRead( pI2CDeviceAddr_t wDevAddr,
u16_t wCount,
pu8_t wData,
pI2CDeviceAddr_t rDevAddr,
u16_t rCount,
pu8_t rData )
DRXStatus_t DRXBSP_I2C_WriteRead(pI2CDeviceAddr_t wDevAddr,
u16_t wCount,
pu8_t wData,
pI2CDeviceAddr_t rDevAddr,
u16_t rCount, pu8_t rData)
{
struct drx39xxj_state *state;
struct i2c_msg msg[2];
@ -102,8 +101,8 @@ DRXStatus_t DRXBSP_I2C_WriteRead( pI2CDeviceAddr_t wDevAddr,
}
if (state->i2c == NULL) {
printk("i2c was zero, aborting\n");
return 0;
printk("i2c was zero, aborting\n");
return 0;
}
if (i2c_transfer(state->i2c, msg, num_msgs) != num_msgs) {
printk(KERN_WARNING "drx3933: I2C write/read failed\n");
@ -116,10 +115,10 @@ DRXStatus_t DRXBSP_I2C_WriteRead( pI2CDeviceAddr_t wDevAddr,
struct drx39xxj_state *state = wDevAddr->userData;
struct i2c_msg msg[2] = {
{ .addr = wDevAddr->i2cAddr,
.flags = 0, .buf = wData, .len = wCount },
{ .addr = rDevAddr->i2cAddr,
.flags = I2C_M_RD, .buf = rData, .len = rCount },
{.addr = wDevAddr->i2cAddr,
.flags = 0,.buf = wData,.len = wCount},
{.addr = rDevAddr->i2cAddr,
.flags = I2C_M_RD,.buf = rData,.len = rCount},
};
printk("drx3933 i2c operation addr=%x i2c=%p, wc=%x rc=%x\n",

658
drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.c
View file

@ -50,154 +50,137 @@
*******************************************************************************/
#include "drx_dap_fasi.h"
#include "bsp_host.h" /* for DRXBSP_HST_Memcpy() */
#include "bsp_host.h" /* for DRXBSP_HST_Memcpy() */
/*============================================================================*/
/* Function prototypes */
static DRXStatus_t DRXDAP_FASI_WriteBlock (
pI2CDeviceAddr_t devAddr, /* address of I2C device */
DRXaddr_t addr, /* address of register/memory */
u16_t datasize, /* size of data */
pu8_t data, /* data to send */
DRXflags_t flags); /* special device flags */
static DRXStatus_t DRXDAP_FASI_WriteBlock(pI2CDeviceAddr_t devAddr, /* address of I2C device */
DRXaddr_t addr, /* address of register/memory */
u16_t datasize, /* size of data */
pu8_t data, /* data to send */
DRXflags_t flags); /* special device flags */
static DRXStatus_t DRXDAP_FASI_ReadBlock (
pI2CDeviceAddr_t devAddr, /* address of I2C device */
DRXaddr_t addr, /* address of register/memory */
u16_t datasize, /* size of data */
pu8_t data, /* data to send */
DRXflags_t flags); /* special device flags */
static DRXStatus_t DRXDAP_FASI_ReadBlock(pI2CDeviceAddr_t devAddr, /* address of I2C device */
DRXaddr_t addr, /* address of register/memory */
u16_t datasize, /* size of data */
pu8_t data, /* data to send */
DRXflags_t flags); /* special device flags */
static DRXStatus_t DRXDAP_FASI_WriteReg8 (
pI2CDeviceAddr_t devAddr, /* address of I2C device */
DRXaddr_t addr, /* address of register */
u8_t data, /* data to write */
DRXflags_t flags); /* special device flags */
static DRXStatus_t DRXDAP_FASI_WriteReg8(pI2CDeviceAddr_t devAddr, /* address of I2C device */
DRXaddr_t addr, /* address of register */
u8_t data, /* data to write */
DRXflags_t flags); /* special device flags */
static DRXStatus_t DRXDAP_FASI_ReadReg8 (
pI2CDeviceAddr_t devAddr, /* address of I2C device */
DRXaddr_t addr, /* address of register */
pu8_t data, /* buffer to receive data */
DRXflags_t flags); /* special device flags */
static DRXStatus_t DRXDAP_FASI_ReadReg8(pI2CDeviceAddr_t devAddr, /* address of I2C device */
DRXaddr_t addr, /* address of register */
pu8_t data, /* buffer to receive data */
DRXflags_t flags); /* special device flags */
static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg8 (
pI2CDeviceAddr_t devAddr, /* address of I2C device */
DRXaddr_t waddr, /* address of register */
DRXaddr_t raddr, /* address to read back from */
u8_t datain, /* data to send */
pu8_t dataout); /* data to receive back */
static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg8(pI2CDeviceAddr_t devAddr, /* address of I2C device */
DRXaddr_t waddr, /* address of register */
DRXaddr_t raddr, /* address to read back from */
u8_t datain, /* data to send */
pu8_t dataout); /* data to receive back */
static DRXStatus_t DRXDAP_FASI_WriteReg16 (
pI2CDeviceAddr_t devAddr, /* address of I2C device */
DRXaddr_t addr, /* address of register */
u16_t data, /* data to write */
DRXflags_t flags); /* special device flags */
static DRXStatus_t DRXDAP_FASI_WriteReg16(pI2CDeviceAddr_t devAddr, /* address of I2C device */
DRXaddr_t addr, /* address of register */
u16_t data, /* data to write */
DRXflags_t flags); /* special device flags */
static DRXStatus_t DRXDAP_FASI_ReadReg16 (
pI2CDeviceAddr_t devAddr, /* address of I2C device */
DRXaddr_t addr, /* address of register */
pu16_t data, /* buffer to receive data */
DRXflags_t flags); /* special device flags */
static DRXStatus_t DRXDAP_FASI_ReadReg16(pI2CDeviceAddr_t devAddr, /* address of I2C device */
DRXaddr_t addr, /* address of register */
pu16_t data, /* buffer to receive data */
DRXflags_t flags); /* special device flags */
static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg16 (
pI2CDeviceAddr_t devAddr, /* address of I2C device */
DRXaddr_t waddr, /* address of register */
DRXaddr_t raddr, /* address to read back from */
u16_t datain, /* data to send */
pu16_t dataout); /* data to receive back */
static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg16(pI2CDeviceAddr_t devAddr, /* address of I2C device */
DRXaddr_t waddr, /* address of register */
DRXaddr_t raddr, /* address to read back from */
u16_t datain, /* data to send */
pu16_t dataout); /* data to receive back */
static DRXStatus_t DRXDAP_FASI_WriteReg32 (
pI2CDeviceAddr_t devAddr, /* address of I2C device */
DRXaddr_t addr, /* address of register */
u32_t data, /* data to write */
DRXflags_t flags); /* special device flags */
static DRXStatus_t DRXDAP_FASI_WriteReg32(pI2CDeviceAddr_t devAddr, /* address of I2C device */
DRXaddr_t addr, /* address of register */
u32_t data, /* data to write */
DRXflags_t flags); /* special device flags */
static DRXStatus_t DRXDAP_FASI_ReadReg32 (
pI2CDeviceAddr_t devAddr, /* address of I2C device */
DRXaddr_t addr, /* address of register */
pu32_t data, /* buffer to receive data */
DRXflags_t flags); /* special device flags */
static DRXStatus_t DRXDAP_FASI_ReadReg32(pI2CDeviceAddr_t devAddr, /* address of I2C device */
DRXaddr_t addr, /* address of register */
pu32_t data, /* buffer to receive data */
DRXflags_t flags); /* special device flags */
static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg32 (
pI2CDeviceAddr_t devAddr, /* address of I2C device */
DRXaddr_t waddr, /* address of register */
DRXaddr_t raddr, /* address to read back from */
u32_t datain, /* data to send */
pu32_t dataout); /* data to receive back */
static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg32(pI2CDeviceAddr_t devAddr, /* address of I2C device */
DRXaddr_t waddr, /* address of register */
DRXaddr_t raddr, /* address to read back from */
u32_t datain, /* data to send */
pu32_t dataout); /* data to receive back */
/* The version structure of this protocol implementation */
char drxDapFASIModuleName[] = "FASI Data Access Protocol";
char drxDapFASIModuleName[] = "FASI Data Access Protocol";
char drxDapFASIVersionText[] = "";
DRXVersion_t drxDapFASIVersion =
{
DRX_MODULE_DAP, /**< type identifier of the module */
drxDapFASIModuleName, /**< name or description of module */
DRXVersion_t drxDapFASIVersion = {
DRX_MODULE_DAP, /**< type identifier of the module */
drxDapFASIModuleName, /**< name or description of module */
0, /**< major version number */
0, /**< minor version number */
0, /**< patch version number */
drxDapFASIVersionText /**< version as text string */
0, /**< major version number */
0, /**< minor version number */
0, /**< patch version number */
drxDapFASIVersionText /**< version as text string */
};
/* The structure containing the protocol interface */
DRXAccessFunc_t drxDapFASIFunct_g =
{
&drxDapFASIVersion,
DRXDAP_FASI_WriteBlock, /* Supported */
DRXDAP_FASI_ReadBlock, /* Supported */
DRXDAP_FASI_WriteReg8, /* Not supported */
DRXDAP_FASI_ReadReg8, /* Not supported */
DRXDAP_FASI_ReadModifyWriteReg8, /* Not supported */
DRXDAP_FASI_WriteReg16, /* Supported */
DRXDAP_FASI_ReadReg16, /* Supported */
DRXDAP_FASI_ReadModifyWriteReg16, /* Supported */
DRXDAP_FASI_WriteReg32, /* Supported */
DRXDAP_FASI_ReadReg32, /* Supported */
DRXDAP_FASI_ReadModifyWriteReg32 /* Not supported */
DRXAccessFunc_t drxDapFASIFunct_g = {
&drxDapFASIVersion,
DRXDAP_FASI_WriteBlock, /* Supported */
DRXDAP_FASI_ReadBlock, /* Supported */
DRXDAP_FASI_WriteReg8, /* Not supported */
DRXDAP_FASI_ReadReg8, /* Not supported */
DRXDAP_FASI_ReadModifyWriteReg8, /* Not supported */
DRXDAP_FASI_WriteReg16, /* Supported */
DRXDAP_FASI_ReadReg16, /* Supported */
DRXDAP_FASI_ReadModifyWriteReg16, /* Supported */
DRXDAP_FASI_WriteReg32, /* Supported */
DRXDAP_FASI_ReadReg32, /* Supported */
DRXDAP_FASI_ReadModifyWriteReg32 /* Not supported */
};
/*============================================================================*/
/* Functions not supported by protocol*/
static DRXStatus_t DRXDAP_FASI_WriteReg8 (
pI2CDeviceAddr_t devAddr, /* address of I2C device */
DRXaddr_t addr, /* address of register */
u8_t data, /* data to write */
DRXflags_t flags) /* special device flags */
{
return DRX_STS_ERROR;
static DRXStatus_t DRXDAP_FASI_WriteReg8(pI2CDeviceAddr_t devAddr, /* address of I2C device */
DRXaddr_t addr, /* address of register */
u8_t data, /* data to write */
DRXflags_t flags)
{ /* special device flags */
return DRX_STS_ERROR;
}
static DRXStatus_t DRXDAP_FASI_ReadReg8 (
pI2CDeviceAddr_t devAddr, /* address of I2C device */
DRXaddr_t addr, /* address of register */
pu8_t data, /* buffer to receive data */
DRXflags_t flags) /* special device flags */
{
return DRX_STS_ERROR;
static DRXStatus_t DRXDAP_FASI_ReadReg8(pI2CDeviceAddr_t devAddr, /* address of I2C device */
DRXaddr_t addr, /* address of register */
pu8_t data, /* buffer to receive data */
DRXflags_t flags)
{ /* special device flags */
return DRX_STS_ERROR;
}
static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg8 (
pI2CDeviceAddr_t devAddr, /* address of I2C device */
DRXaddr_t waddr, /* address of register */
DRXaddr_t raddr, /* address to read back from */
u8_t datain, /* data to send */
pu8_t dataout) /* data to receive back */
{
return DRX_STS_ERROR;
static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg8(pI2CDeviceAddr_t devAddr, /* address of I2C device */
DRXaddr_t waddr, /* address of register */
DRXaddr_t raddr, /* address to read back from */
u8_t datain, /* data to send */
pu8_t dataout)
{ /* data to receive back */
return DRX_STS_ERROR;
}
static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg32 (
pI2CDeviceAddr_t devAddr, /* address of I2C device */
DRXaddr_t waddr, /* address of register */
DRXaddr_t raddr, /* address to read back from */
u32_t datain, /* data to send */
pu32_t dataout) /* data to receive back */
{
return DRX_STS_ERROR;
static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg32(pI2CDeviceAddr_t devAddr, /* address of I2C device */
DRXaddr_t waddr, /* address of register */
DRXaddr_t raddr, /* address to read back from */
u32_t datain, /* data to send */
pu32_t dataout)
{ /* data to receive back */
return DRX_STS_ERROR;
}
/*============================================================================*/
@ -227,105 +210,96 @@ static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg32 (
*
******************************/
static DRXStatus_t DRXDAP_FASI_ReadBlock ( pI2CDeviceAddr_t devAddr,
DRXaddr_t addr,
u16_t datasize,
pu8_t data,
DRXflags_t flags )
static DRXStatus_t DRXDAP_FASI_ReadBlock(pI2CDeviceAddr_t devAddr,
DRXaddr_t addr,
u16_t datasize,
pu8_t data, DRXflags_t flags)
{
u8_t buf[4];
u16_t bufx;
DRXStatus_t rc;
u16_t overheadSize = 0;
u8_t buf[4];
u16_t bufx;
DRXStatus_t rc;
u16_t overheadSize = 0;
/* Check parameters ********************************************************/
if ( devAddr == NULL )
{
return DRX_STS_INVALID_ARG;
}
/* Check parameters ******************************************************* */
if (devAddr == NULL) {
return DRX_STS_INVALID_ARG;
}
overheadSize = (IS_I2C_10BIT (devAddr->i2cAddr) ? 2 : 1) +
(DRXDAP_FASI_LONG_FORMAT(addr) ? 4 : 2 );
overheadSize = (IS_I2C_10BIT(devAddr->i2cAddr) ? 2 : 1) +
(DRXDAP_FASI_LONG_FORMAT(addr) ? 4 : 2);
if ( ( DRXDAP_FASI_OFFSET_TOO_LARGE(addr) ) ||
( ( !(DRXDAPFASI_LONG_ADDR_ALLOWED) ) &&
DRXDAP_FASI_LONG_FORMAT( addr ) ) ||
(overheadSize > (DRXDAP_MAX_WCHUNKSIZE)) ||
((datasize!=0) && (data==NULL)) ||
((datasize & 1)==1 ) )
{
return DRX_STS_INVALID_ARG;
}
if ((DRXDAP_FASI_OFFSET_TOO_LARGE(addr)) ||
((!(DRXDAPFASI_LONG_ADDR_ALLOWED)) &&
DRXDAP_FASI_LONG_FORMAT(addr)) ||
(overheadSize > (DRXDAP_MAX_WCHUNKSIZE)) ||
((datasize != 0) && (data == NULL)) || ((datasize & 1) == 1)) {
return DRX_STS_INVALID_ARG;
}
/* ReadModifyWrite & mode flag bits are not allowed */
flags &= (~DRXDAP_FASI_RMW & ~DRXDAP_FASI_MODEFLAGS);
/* ReadModifyWrite & mode flag bits are not allowed */
flags &= (~DRXDAP_FASI_RMW & ~DRXDAP_FASI_MODEFLAGS);
#if DRXDAP_SINGLE_MASTER
flags |= DRXDAP_FASI_SINGLE_MASTER;
flags |= DRXDAP_FASI_SINGLE_MASTER;
#endif
/* Read block from I2C *****************************************************/
do {
u16_t todo = ( datasize < DRXDAP_MAX_RCHUNKSIZE ?
datasize : DRXDAP_MAX_RCHUNKSIZE);
/* Read block from I2C **************************************************** */
do {
u16_t todo = (datasize < DRXDAP_MAX_RCHUNKSIZE ?
datasize : DRXDAP_MAX_RCHUNKSIZE);
bufx = 0;
bufx = 0;
addr &= ~DRXDAP_FASI_FLAGS;
addr |= flags;
addr &= ~DRXDAP_FASI_FLAGS;
addr |= flags;
#if ( ( DRXDAPFASI_LONG_ADDR_ALLOWED==1 ) && \
( DRXDAPFASI_SHORT_ADDR_ALLOWED==1 ) )
/* short format address preferred but long format otherwise */
if ( DRXDAP_FASI_LONG_FORMAT(addr) )
{
/* short format address preferred but long format otherwise */
if (DRXDAP_FASI_LONG_FORMAT(addr)) {
#endif
#if ( DRXDAPFASI_LONG_ADDR_ALLOWED==1 )
buf[bufx++] = (u8_t) (((addr << 1) & 0xFF)|0x01);
buf[bufx++] = (u8_t) ((addr >> 16) & 0xFF);
buf[bufx++] = (u8_t) ((addr >> 24) & 0xFF);
buf[bufx++] = (u8_t) ((addr >> 7) & 0xFF);
buf[bufx++] = (u8_t) (((addr << 1) & 0xFF) | 0x01);
buf[bufx++] = (u8_t) ((addr >> 16) & 0xFF);
buf[bufx++] = (u8_t) ((addr >> 24) & 0xFF);
buf[bufx++] = (u8_t) ((addr >> 7) & 0xFF);
#endif
#if ( ( DRXDAPFASI_LONG_ADDR_ALLOWED==1 ) && \
( DRXDAPFASI_SHORT_ADDR_ALLOWED==1 ) )
} else {
} else {
#endif
#if ( DRXDAPFASI_SHORT_ADDR_ALLOWED==1 )
buf[bufx++] = (u8_t) ((addr << 1) & 0xFF);
buf[bufx++] = (u8_t) ( ((addr >> 16) & 0x0F) | ((addr >> 18) & 0xF0) );
buf[bufx++] = (u8_t) ((addr << 1) & 0xFF);
buf[bufx++] =
(u8_t) (((addr >> 16) & 0x0F) |
((addr >> 18) & 0xF0));
#endif
#if ( ( DRXDAPFASI_LONG_ADDR_ALLOWED==1 ) && \
( DRXDAPFASI_SHORT_ADDR_ALLOWED==1 ) )
}
}
#endif
#if DRXDAP_SINGLE_MASTER
/*
* In single master mode, split the read and write actions.
* No special action is needed for write chunks here.
*/
rc = DRXBSP_I2C_WriteRead (devAddr, bufx, buf, 0, 0, 0);
if (rc == DRX_STS_OK)
{
rc = DRXBSP_I2C_WriteRead (0, 0, 0, devAddr, todo, data);
}
/*
* In single master mode, split the read and write actions.
* No special action is needed for write chunks here.
*/
rc = DRXBSP_I2C_WriteRead(devAddr, bufx, buf, 0, 0, 0);
if (rc == DRX_STS_OK) {
rc = DRXBSP_I2C_WriteRead(0, 0, 0, devAddr, todo, data);
}
#else
/* In multi master mode, do everything in one RW action */
rc = DRXBSP_I2C_WriteRead (devAddr, bufx, buf, devAddr, todo, data);
/* In multi master mode, do everything in one RW action */
rc = DRXBSP_I2C_WriteRead(devAddr, bufx, buf, devAddr, todo,
data);
#endif
data += todo;
addr += (todo >> 1);
datasize -= todo;
} while (datasize && rc == DRX_STS_OK);
data += todo;
addr += (todo >> 1);
datasize -= todo;
} while (datasize && rc == DRX_STS_OK);
return rc;
return rc;
}
/******************************
*
* DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg16 (
@ -351,33 +325,27 @@ static DRXStatus_t DRXDAP_FASI_ReadBlock ( pI2CDeviceAddr_t devAddr,
*
******************************/
static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg16 ( pI2CDeviceAddr_t devAddr,
DRXaddr_t waddr,
DRXaddr_t raddr,
u16_t wdata,
pu16_t rdata )
static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg16(pI2CDeviceAddr_t devAddr,
DRXaddr_t waddr,
DRXaddr_t raddr,
u16_t wdata, pu16_t rdata)
{
DRXStatus_t rc=DRX_STS_ERROR;
DRXStatus_t rc = DRX_STS_ERROR;
#if ( DRXDAPFASI_LONG_ADDR_ALLOWED==1 )
if (rdata == NULL)
{
return DRX_STS_INVALID_ARG;
}
if (rdata == NULL) {
return DRX_STS_INVALID_ARG;
}
rc = DRXDAP_FASI_WriteReg16 (devAddr, waddr, wdata, DRXDAP_FASI_RMW);
if (rc == DRX_STS_OK)
{
rc = DRXDAP_FASI_ReadReg16 (devAddr, raddr, rdata, 0);
}
rc = DRXDAP_FASI_WriteReg16(devAddr, waddr, wdata, DRXDAP_FASI_RMW);
if (rc == DRX_STS_OK) {
rc = DRXDAP_FASI_ReadReg16(devAddr, raddr, rdata, 0);
}
#endif
return rc;
return rc;
}
/******************************
*
* DRXStatus_t DRXDAP_FASI_ReadReg16 (
@ -396,26 +364,21 @@ static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg16 ( pI2CDeviceAddr_t devAddr,
*
******************************/
static DRXStatus_t DRXDAP_FASI_ReadReg16 ( pI2CDeviceAddr_t devAddr,
DRXaddr_t addr,
pu16_t data,
DRXflags_t flags )
static DRXStatus_t DRXDAP_FASI_ReadReg16(pI2CDeviceAddr_t devAddr,
DRXaddr_t addr,
pu16_t data, DRXflags_t flags)
{
u8_t buf[sizeof (*data)];
DRXStatus_t rc;
u8_t buf[sizeof(*data)];
DRXStatus_t rc;
if (!data)
{
return DRX_STS_INVALID_ARG;
}
rc = DRXDAP_FASI_ReadBlock (devAddr, addr, sizeof (*data), buf, flags);
*data = buf[0] + (((u16_t) buf[1]) << 8);
return rc;
if (!data) {
return DRX_STS_INVALID_ARG;
}
rc = DRXDAP_FASI_ReadBlock(devAddr, addr, sizeof(*data), buf, flags);
*data = buf[0] + (((u16_t) buf[1]) << 8);
return rc;
}
/******************************
*
* DRXStatus_t DRXDAP_FASI_ReadReg32 (
@ -434,29 +397,23 @@ static DRXStatus_t DRXDAP_FASI_ReadReg16 ( pI2CDeviceAddr_t devAddr,
*
******************************/
static DRXStatus_t DRXDAP_FASI_ReadReg32 ( pI2CDeviceAddr_t devAddr,
DRXaddr_t addr,
pu32_t data,
DRXflags_t flags )
static DRXStatus_t DRXDAP_FASI_ReadReg32(pI2CDeviceAddr_t devAddr,
DRXaddr_t addr,
pu32_t data, DRXflags_t flags)
{
u8_t buf[sizeof (*data)];
DRXStatus_t rc;
u8_t buf[sizeof(*data)];
DRXStatus_t rc;
if (!data)
{
return DRX_STS_INVALID_ARG;
}
rc = DRXDAP_FASI_ReadBlock (devAddr, addr, sizeof (*data), buf, flags);
*data = (((u32_t) buf[0]) << 0) +
(((u32_t) buf[1]) << 8) +
(((u32_t) buf[2]) << 16) +
(((u32_t) buf[3]) << 24);
return rc;
if (!data) {
return DRX_STS_INVALID_ARG;
}
rc = DRXDAP_FASI_ReadBlock(devAddr, addr, sizeof(*data), buf, flags);
*data = (((u32_t) buf[0]) << 0) +
(((u32_t) buf[1]) << 8) +
(((u32_t) buf[2]) << 16) + (((u32_t) buf[3]) << 24);
return rc;
}
/******************************
*
* DRXStatus_t DRXDAP_FASI_WriteBlock (
@ -479,136 +436,128 @@ static DRXStatus_t DRXDAP_FASI_ReadReg32 ( pI2CDeviceAddr_t devAddr,
*
******************************/
static DRXStatus_t DRXDAP_FASI_WriteBlock ( pI2CDeviceAddr_t devAddr,
DRXaddr_t addr,
u16_t datasize,
pu8_t data,
DRXflags_t flags )
static DRXStatus_t DRXDAP_FASI_WriteBlock(pI2CDeviceAddr_t devAddr,
DRXaddr_t addr,
u16_t datasize,
pu8_t data, DRXflags_t flags)
{
u8_t buf[ DRXDAP_MAX_WCHUNKSIZE ];
DRXStatus_t st = DRX_STS_ERROR;
DRXStatus_t firstErr = DRX_STS_OK;
u16_t overheadSize = 0;
u16_t blockSize = 0;
u8_t buf[DRXDAP_MAX_WCHUNKSIZE];
DRXStatus_t st = DRX_STS_ERROR;
DRXStatus_t firstErr = DRX_STS_OK;
u16_t overheadSize = 0;
u16_t blockSize = 0;
/* Check parameters ********************************************************/
if ( devAddr == NULL )
{
return DRX_STS_INVALID_ARG;
}
/* Check parameters ******************************************************* */
if (devAddr == NULL) {
return DRX_STS_INVALID_ARG;
}
overheadSize = (IS_I2C_10BIT (devAddr->i2cAddr) ? 2 : 1) +
(DRXDAP_FASI_LONG_FORMAT(addr) ? 4 : 2 );
overheadSize = (IS_I2C_10BIT(devAddr->i2cAddr) ? 2 : 1) +
(DRXDAP_FASI_LONG_FORMAT(addr) ? 4 : 2);
if ( ( DRXDAP_FASI_OFFSET_TOO_LARGE(addr) ) ||
( ( !(DRXDAPFASI_LONG_ADDR_ALLOWED) ) &&
DRXDAP_FASI_LONG_FORMAT( addr ) ) ||
(overheadSize > (DRXDAP_MAX_WCHUNKSIZE)) ||
((datasize!=0) && (data==NULL)) ||
((datasize & 1)==1 ) )
{
return DRX_STS_INVALID_ARG;
}
if ((DRXDAP_FASI_OFFSET_TOO_LARGE(addr)) ||
((!(DRXDAPFASI_LONG_ADDR_ALLOWED)) &&
DRXDAP_FASI_LONG_FORMAT(addr)) ||
(overheadSize > (DRXDAP_MAX_WCHUNKSIZE)) ||
((datasize != 0) && (data == NULL)) || ((datasize & 1) == 1)) {
return DRX_STS_INVALID_ARG;
}
flags &= DRXDAP_FASI_FLAGS;
flags &= ~DRXDAP_FASI_MODEFLAGS;
flags &= DRXDAP_FASI_FLAGS;
flags &= ~DRXDAP_FASI_MODEFLAGS;
#if DRXDAP_SINGLE_MASTER
flags |= DRXDAP_FASI_SINGLE_MASTER;
flags |= DRXDAP_FASI_SINGLE_MASTER;
#endif
/* Write block to I2C ******************************************************/
blockSize = ( (DRXDAP_MAX_WCHUNKSIZE) - overheadSize) & ~1;
do
{
u16_t todo = 0;
u16_t bufx = 0;
/* Write block to I2C ***************************************************** */
blockSize = ((DRXDAP_MAX_WCHUNKSIZE) - overheadSize) & ~1;
do {
u16_t todo = 0;
u16_t bufx = 0;
/* Buffer device address */
addr &= ~DRXDAP_FASI_FLAGS;
addr |= flags;
/* Buffer device address */
addr &= ~DRXDAP_FASI_FLAGS;
addr |= flags;
#if ( ( (DRXDAPFASI_LONG_ADDR_ALLOWED)==1 ) && \
( (DRXDAPFASI_SHORT_ADDR_ALLOWED)==1 ) )
/* short format address preferred but long format otherwise */
if ( DRXDAP_FASI_LONG_FORMAT(addr) )
{
/* short format address preferred but long format otherwise */
if (DRXDAP_FASI_LONG_FORMAT(addr)) {
#endif
#if ( (DRXDAPFASI_LONG_ADDR_ALLOWED)==1 )
buf[bufx++] = (u8_t) (((addr << 1) & 0xFF)|0x01);
buf[bufx++] = (u8_t) ((addr >> 16) & 0xFF);
buf[bufx++] = (u8_t) ((addr >> 24) & 0xFF);
buf[bufx++] = (u8_t) ((addr >> 7) & 0xFF);
buf[bufx++] = (u8_t) (((addr << 1) & 0xFF) | 0x01);
buf[bufx++] = (u8_t) ((addr >> 16) & 0xFF);
buf[bufx++] = (u8_t) ((addr >> 24) & 0xFF);
buf[bufx++] = (u8_t) ((addr >> 7) & 0xFF);
#endif
#if ( ( (DRXDAPFASI_LONG_ADDR_ALLOWED)==1 ) && \
( (DRXDAPFASI_SHORT_ADDR_ALLOWED)==1 ) )
} else {
} else {
#endif
#if ( (DRXDAPFASI_SHORT_ADDR_ALLOWED)==1 )
buf[bufx++] = (u8_t) ((addr << 1) & 0xFF);
buf[bufx++] = (u8_t) ( ((addr >> 16) & 0x0F) | ((addr >> 18) & 0xF0) );
buf[bufx++] = (u8_t) ((addr << 1) & 0xFF);
buf[bufx++] =
(u8_t) (((addr >> 16) & 0x0F) |
((addr >> 18) & 0xF0));
#endif
#if ( ( (DRXDAPFASI_LONG_ADDR_ALLOWED)==1 ) && \
( (DRXDAPFASI_SHORT_ADDR_ALLOWED)==1 ) )
}
}
#endif
/*
In single master mode blockSize can be 0. In such a case this I2C
sequense will be visible: (1) write address {i2c addr,
4 bytes chip address} (2) write data {i2c addr, 4 bytes data }
(3) write address (4) write data etc...
Addres must be rewriten because HI is reset after data transport and
expects an address.
*/
todo = (blockSize < datasize ? blockSize : datasize);
if (todo==0)
{
u16_t overheadSizeI2cAddr = 0;
u16_t dataBlockSize = 0;
/*
In single master mode blockSize can be 0. In such a case this I2C
sequense will be visible: (1) write address {i2c addr,
4 bytes chip address} (2) write data {i2c addr, 4 bytes data }
(3) write address (4) write data etc...
Addres must be rewriten because HI is reset after data transport and
expects an address.
*/
todo = (blockSize < datasize ? blockSize : datasize);
if (todo == 0) {
u16_t overheadSizeI2cAddr = 0;
u16_t dataBlockSize = 0;
overheadSizeI2cAddr = (IS_I2C_10BIT (devAddr->i2cAddr) ? 2 : 1);
dataBlockSize = ( DRXDAP_MAX_WCHUNKSIZE - overheadSizeI2cAddr) & ~1;
overheadSizeI2cAddr =
(IS_I2C_10BIT(devAddr->i2cAddr) ? 2 : 1);
dataBlockSize =
(DRXDAP_MAX_WCHUNKSIZE - overheadSizeI2cAddr) & ~1;
/* write device address */
st = DRXBSP_I2C_WriteRead( devAddr,
(u16_t) (bufx),
buf,
(pI2CDeviceAddr_t)(NULL),
0,
(pu8_t)(NULL) );
/* write device address */
st = DRXBSP_I2C_WriteRead(devAddr,
(u16_t) (bufx),
buf,
(pI2CDeviceAddr_t) (NULL),
0, (pu8_t) (NULL));
if ( ( st != DRX_STS_OK ) && ( firstErr == DRX_STS_OK ) )
{
/* at the end, return the first error encountered */
firstErr = st;
}
bufx = 0;
todo = (dataBlockSize < datasize ? dataBlockSize : datasize);
}
DRXBSP_HST_Memcpy (&buf[bufx], data, todo);
/* write (address if can do and) data */
st = DRXBSP_I2C_WriteRead( devAddr,
(u16_t)(bufx + todo),
buf,
(pI2CDeviceAddr_t)(NULL),
0,
(pu8_t)(NULL) );
if ((st != DRX_STS_OK) && (firstErr == DRX_STS_OK)) {
/* at the end, return the first error encountered */
firstErr = st;
}
bufx = 0;
todo =
(dataBlockSize <
datasize ? dataBlockSize : datasize);
}
DRXBSP_HST_Memcpy(&buf[bufx], data, todo);
/* write (address if can do and) data */
st = DRXBSP_I2C_WriteRead(devAddr,
(u16_t) (bufx + todo),
buf,
(pI2CDeviceAddr_t) (NULL),
0, (pu8_t) (NULL));
if ( ( st != DRX_STS_OK ) && ( firstErr == DRX_STS_OK ) )
{
/* at the end, return the first error encountered */
firstErr = st;
}
datasize -= todo;
data += todo;
addr += (todo >> 1);
} while (datasize);
if ((st != DRX_STS_OK) && (firstErr == DRX_STS_OK)) {
/* at the end, return the first error encountered */
firstErr = st;
}
datasize -= todo;
data += todo;
addr += (todo >> 1);
} while (datasize);
return firstErr;
return firstErr;
}
/******************************
*
* DRXStatus_t DRXDAP_FASI_WriteReg16 (
@ -626,22 +575,18 @@ static DRXStatus_t DRXDAP_FASI_WriteBlock ( pI2CDeviceAddr_t devAddr,
*
******************************/
static DRXStatus_t DRXDAP_FASI_WriteReg16 ( pI2CDeviceAddr_t devAddr,
DRXaddr_t addr,
u16_t data,
DRXflags_t flags )
static DRXStatus_t DRXDAP_FASI_WriteReg16(pI2CDeviceAddr_t devAddr,
DRXaddr_t addr,
u16_t data, DRXflags_t flags)
{
u8_t buf[sizeof (data)];
u8_t buf[sizeof(data)];
buf[0] = (u8_t) ( (data >> 0 ) & 0xFF );
buf[1] = (u8_t) ( (data >> 8 ) & 0xFF );
buf[0] = (u8_t) ((data >> 0) & 0xFF);
buf[1] = (u8_t) ((data >> 8) & 0xFF);
return DRXDAP_FASI_WriteBlock (devAddr, addr, sizeof (data), buf, flags);
return DRXDAP_FASI_WriteBlock(devAddr, addr, sizeof(data), buf, flags);
}
/******************************
*
* DRXStatus_t DRXDAP_FASI_WriteReg32 (
@ -659,17 +604,16 @@ static DRXStatus_t DRXDAP_FASI_WriteReg16 ( pI2CDeviceAddr_t devAddr,
*
******************************/
static DRXStatus_t DRXDAP_FASI_WriteReg32 ( pI2CDeviceAddr_t devAddr,
DRXaddr_t addr,
u32_t data,
DRXflags_t flags )
static DRXStatus_t DRXDAP_FASI_WriteReg32(pI2CDeviceAddr_t devAddr,
DRXaddr_t addr,
u32_t data, DRXflags_t flags)
{
u8_t buf[sizeof (data)];
u8_t buf[sizeof(data)];
buf[0] = (u8_t) ( (data >> 0 ) & 0xFF );
buf[1] = (u8_t) ( (data >> 8 ) & 0xFF );
buf[2] = (u8_t) ( (data >> 16) & 0xFF );
buf[3] = (u8_t) ( (data >> 24) & 0xFF );
buf[0] = (u8_t) ((data >> 0) & 0xFF);
buf[1] = (u8_t) ((data >> 8) & 0xFF);
buf[2] = (u8_t) ((data >> 16) & 0xFF);
buf[3] = (u8_t) ((data >> 24) & 0xFF);
return DRXDAP_FASI_WriteBlock (devAddr, addr, sizeof (data), buf, flags);
return DRXDAP_FASI_WriteBlock(devAddr, addr, sizeof(data), buf, flags);
}

25
drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.h
View file

@ -96,10 +96,9 @@
#if ( ( DRXDAPFASI_LONG_ADDR_ALLOWED==0 ) && \
( DRXDAPFASI_SHORT_ADDR_ALLOWED==0 ) )
#error At least one of short- or long-addressing format must be allowed.
*; /* illegal statement to force compiler error */
*; /* illegal statement to force compiler error */
#endif
/********************************************
* Single/master multi master setting
********************************************/
@ -200,18 +199,18 @@
#if ( (DRXDAPFASI_LONG_ADDR_ALLOWED==0)&&(DRXDAPFASI_SHORT_ADDR_ALLOWED==1) )
#if DRXDAP_SINGLE_MASTER
#error DRXDAP_MAX_WCHUNKSIZE must be at least 3 in single master mode
*; /* illegal statement to force compiler error */
*; /* illegal statement to force compiler error */
#else
#error DRXDAP_MAX_WCHUNKSIZE must be at least 5 in multi master mode
*; /* illegal statement to force compiler error */
*; /* illegal statement to force compiler error */
#endif
#else
#if DRXDAP_SINGLE_MASTER
#error DRXDAP_MAX_WCHUNKSIZE must be at least 5 in single master mode
*; /* illegal statement to force compiler error */
*; /* illegal statement to force compiler error */
#else
#error DRXDAP_MAX_WCHUNKSIZE must be at least 7 in multi master mode
*; /* illegal statement to force compiler error */
*; /* illegal statement to force compiler error */
#endif
#endif
#endif
@ -224,13 +223,13 @@
/* check */
#if DRXDAP_MAX_RCHUNKSIZE < 2
#error DRXDAP_MAX_RCHUNKSIZE must be at least 2
*; /* illegal statement to force compiler error */
*; /* illegal statement to force compiler error */
#endif
/* check */
#if DRXDAP_MAX_RCHUNKSIZE & 1
#error DRXDAP_MAX_RCHUNKSIZE must be even
*; /* illegal statement to force compiler error */
*; /* illegal statement to force compiler error */
#endif
/*-------- Public API functions ----------------------------------------------*/
@ -239,15 +238,14 @@
extern "C" {
#endif
extern DRXAccessFunc_t drxDapFASIFunct_g;
extern DRXAccessFunc_t drxDapFASIFunct_g;
#define DRXDAP_FASI_RMW 0x10000000
#define DRXDAP_FASI_BROADCAST 0x20000000
#define DRXDAP_FASI_CLEARCRC 0x80000000
#define DRXDAP_FASI_SINGLE_MASTER 0xC0000000
#define DRXDAP_FASI_MULTI_MASTER 0x40000000
#define DRXDAP_FASI_SMM_SWITCH 0x40000000 /* single/multi master switch */
#define DRXDAP_FASI_SMM_SWITCH 0x40000000 /* single/multi master switch */
#define DRXDAP_FASI_MODEFLAGS 0xC0000000
#define DRXDAP_FASI_FLAGS 0xF0000000
@ -259,10 +257,7 @@ extern DRXAccessFunc_t drxDapFASIFunct_g;
#define DRXDAP_FASI_LONG_FORMAT( addr ) (((addr)& 0xFC30FF80)!=0)
#define DRXDAP_FASI_OFFSET_TOO_LARGE( addr ) (((addr)& 0x00008000)!=0)
#ifdef __cplusplus
}
#endif
#endif /* __DRX_DAP_FASI_H__ */
#endif /* __DRX_DAP_FASI_H__ */

1778
drivers/media/dvb-frontends/drx39xyj/drx_driver.c
View file

File diff suppressed because it is too large Load diff

1812
drivers/media/dvb-frontends/drx39xyj/drx_driver.h
View file

File diff suppressed because it is too large Load diff

11
drivers/media/dvb-frontends/drx39xyj/drx_driver_version.h
View file

@ -53,10 +53,9 @@ extern "C" {
#ifdef _REGISTERTABLE_
#include <registertable.h>
extern RegisterTable_t drx_driver_version[];
extern RegisterTableInfo_t drx_driver_version_info[];
#endif /* _REGISTERTABLE_ */
extern RegisterTable_t drx_driver_version[];
extern RegisterTableInfo_t drx_driver_version_info[];
#endif /* _REGISTERTABLE_ */
/*
*==============================================================================
@ -73,9 +72,7 @@ extern RegisterTableInfo_t drx_driver_version_info[];
#ifdef __cplusplus
}
#endif
#endif /* __DRX_DRIVER_VERSION__H__ */
#endif /* __DRX_DRIVER_VERSION__H__ */
/*
* End of file (drx_driver_version.h)
*******************************************************************************

22573
drivers/media/dvb-frontends/drx39xyj/drxj.c
View file

File diff suppressed because it is too large Load diff

601
drivers/media/dvb-frontends/drx39xyj/drxj.h
View file

@ -55,8 +55,8 @@ extern "C" {
cannot be done with short addr only in multi master mode. */
#if ((DRXDAP_SINGLE_MASTER==0)&&(DRXDAPFASI_LONG_ADDR_ALLOWED==0))
#error "Multi master mode and short addressing only is an illegal combination"
*; /* Generate a fatal compiler error to make sure it stops here,
this is necesarry because not all compilers stop after a #error. */
*; /* Generate a fatal compiler error to make sure it stops here,
this is necesarry because not all compilers stop after a #error. */
#endif
/*-------------------------------------------------------------------------
@ -74,14 +74,18 @@ TYPEDEFS
/*============================================================================*/
/*============================================================================*/
typedef struct {
u16_t command; /**< Command number */
u16_t parameterLen; /**< Data length in byte */
u16_t resultLen; /**< result length in byte */
u16_t *parameter; /**< General purpous param */
u16_t *result; /**< General purpous param */
} DRXJSCUCmd_t, *pDRXJSCUCmd_t;
typedef struct {
u16_t command;
/**< Command number */
u16_t parameterLen;
/**< Data length in byte */
u16_t resultLen;
/**< result length in byte */
u16_t *parameter;
/**< General purpous param */
u16_t *result;
/**< General purpous param */
} DRXJSCUCmd_t, *pDRXJSCUCmd_t;
/*============================================================================*/
/*============================================================================*/
@ -93,8 +97,8 @@ typedef struct {
#define DRXJ_DEMOD_LOCK (DRX_LOCK_STATE_1)
/* OOB lock states */
#define DRXJ_OOB_AGC_LOCK (DRX_LOCK_STATE_1) /* analog gain control lock */
#define DRXJ_OOB_SYNC_LOCK (DRX_LOCK_STATE_2) /* digital gain control lock */
#define DRXJ_OOB_AGC_LOCK (DRX_LOCK_STATE_1) /* analog gain control lock */
#define DRXJ_OOB_SYNC_LOCK (DRX_LOCK_STATE_2) /* digital gain control lock */
/* Intermediate powermodes for DRXJ */
#define DRXJ_POWER_DOWN_MAIN_PATH DRX_POWER_MODE_8
@ -107,62 +111,61 @@ typedef struct {
/*#define DRX_CTRL_BASE (0x0000)*/
#define DRXJ_CTRL_CFG_BASE (0x1000)
typedef enum {
DRXJ_CFG_AGC_RF = DRXJ_CTRL_CFG_BASE,
DRXJ_CFG_AGC_IF,
DRXJ_CFG_AGC_INTERNAL,
DRXJ_CFG_PRE_SAW,
DRXJ_CFG_AFE_GAIN,
DRXJ_CFG_SYMBOL_CLK_OFFSET,
DRXJ_CFG_ACCUM_CR_RS_CW_ERR,
DRXJ_CFG_FEC_MERS_SEQ_COUNT,
DRXJ_CFG_OOB_MISC,
DRXJ_CFG_SMART_ANT,
DRXJ_CFG_OOB_PRE_SAW,
DRXJ_CFG_VSB_MISC,
DRXJ_CFG_RESET_PACKET_ERR,
typedef enum {
DRXJ_CFG_AGC_RF = DRXJ_CTRL_CFG_BASE,
DRXJ_CFG_AGC_IF,
DRXJ_CFG_AGC_INTERNAL,
DRXJ_CFG_PRE_SAW,
DRXJ_CFG_AFE_GAIN,
DRXJ_CFG_SYMBOL_CLK_OFFSET,
DRXJ_CFG_ACCUM_CR_RS_CW_ERR,
DRXJ_CFG_FEC_MERS_SEQ_COUNT,
DRXJ_CFG_OOB_MISC,
DRXJ_CFG_SMART_ANT,
DRXJ_CFG_OOB_PRE_SAW,
DRXJ_CFG_VSB_MISC,
DRXJ_CFG_RESET_PACKET_ERR,
/* ATV (FM) */
DRXJ_CFG_ATV_OUTPUT, /* also for FM (SIF control) but not likely */
DRXJ_CFG_ATV_MISC,
DRXJ_CFG_ATV_EQU_COEF,
DRXJ_CFG_ATV_AGC_STATUS, /* also for FM ( IF,RF, audioAGC ) */
/* ATV (FM) */
DRXJ_CFG_ATV_OUTPUT, /* also for FM (SIF control) but not likely */
DRXJ_CFG_ATV_MISC,
DRXJ_CFG_ATV_EQU_COEF,
DRXJ_CFG_ATV_AGC_STATUS, /* also for FM ( IF,RF, audioAGC ) */
DRXJ_CFG_MPEG_OUTPUT_MISC,
DRXJ_CFG_HW_CFG,
DRXJ_CFG_OOB_LO_POW,
DRXJ_CFG_MPEG_OUTPUT_MISC,
DRXJ_CFG_HW_CFG,
DRXJ_CFG_OOB_LO_POW,
DRXJ_CFG_MAX /* dummy, never to be used */
} DRXJCfgType_t, *pDRXJCfgType_t;
DRXJ_CFG_MAX /* dummy, never to be used */
} DRXJCfgType_t, *pDRXJCfgType_t;
/**
* /struct DRXJCfgSmartAntIO_t
* smart antenna i/o.
*/
typedef enum DRXJCfgSmartAntIO_t {
DRXJ_SMT_ANT_OUTPUT = 0,
DRXJ_SMT_ANT_INPUT
} DRXJCfgSmartAntIO_t, *pDRXJCfgSmartAntIO_t;
typedef enum DRXJCfgSmartAntIO_t {
DRXJ_SMT_ANT_OUTPUT = 0,
DRXJ_SMT_ANT_INPUT
} DRXJCfgSmartAntIO_t, *pDRXJCfgSmartAntIO_t;
/**
* /struct DRXJCfgSmartAnt_t
* Set smart antenna.
*/
typedef struct {
DRXJCfgSmartAntIO_t io;
u16_t ctrlData;
} DRXJCfgSmartAnt_t, *pDRXJCfgSmartAnt_t;
typedef struct {
DRXJCfgSmartAntIO_t io;
u16_t ctrlData;
} DRXJCfgSmartAnt_t, *pDRXJCfgSmartAnt_t;
/**
* /struct DRXJAGCSTATUS_t
* AGC status information from the DRXJ-IQM-AF.
*/
typedef struct {
u16_t IFAGC;
u16_t RFAGC;
u16_t DigitalAGC;
}DRXJAgcStatus_t, *pDRXJAgcStatus_t;
typedef struct {
u16_t IFAGC;
u16_t RFAGC;
u16_t DigitalAGC;
} DRXJAgcStatus_t, *pDRXJAgcStatus_t;
/* DRXJ_CFG_AGC_RF, DRXJ_CFG_AGC_IF */
@ -170,27 +173,27 @@ typedef struct {
* /struct DRXJAgcCtrlMode_t
* Available AGCs modes in the DRXJ.
*/
typedef enum {
DRX_AGC_CTRL_AUTO = 0,
DRX_AGC_CTRL_USER,
DRX_AGC_CTRL_OFF
} DRXJAgcCtrlMode_t, *pDRXJAgcCtrlMode_t;
typedef enum {
DRX_AGC_CTRL_AUTO = 0,
DRX_AGC_CTRL_USER,
DRX_AGC_CTRL_OFF
} DRXJAgcCtrlMode_t, *pDRXJAgcCtrlMode_t;
/**
* /struct DRXJCfgAgc_t
* Generic interface for all AGCs present on the DRXJ.
*/
typedef struct {
DRXStandard_t standard; /* standard for which these settings apply */
DRXJAgcCtrlMode_t ctrlMode; /* off, user, auto */
u16_t outputLevel; /* range dependent on AGC */
u16_t minOutputLevel; /* range dependent on AGC */
u16_t maxOutputLevel; /* range dependent on AGC */
u16_t speed; /* range dependent on AGC */
u16_t top; /* rf-agc take over point */
u16_t cutOffCurrent; /* rf-agc is accelerated if output current
is below cut-off current */
}DRXJCfgAgc_t, *pDRXJCfgAgc_t;
typedef struct {
DRXStandard_t standard; /* standard for which these settings apply */
DRXJAgcCtrlMode_t ctrlMode; /* off, user, auto */
u16_t outputLevel; /* range dependent on AGC */
u16_t minOutputLevel; /* range dependent on AGC */
u16_t maxOutputLevel; /* range dependent on AGC */
u16_t speed; /* range dependent on AGC */
u16_t top; /* rf-agc take over point */
u16_t cutOffCurrent; /* rf-agc is accelerated if output current
is below cut-off current */
} DRXJCfgAgc_t, *pDRXJCfgAgc_t;
/* DRXJ_CFG_PRE_SAW */
@ -198,11 +201,11 @@ typedef struct {
* /struct DRXJCfgPreSaw_t
* Interface to configure pre SAW sense.
*/
typedef struct {
DRXStandard_t standard; /* standard to which these settings apply */
u16_t reference; /* pre SAW reference value, range 0 .. 31 */
Bool_t usePreSaw; /* TRUE algorithms must use pre SAW sense */
} DRXJCfgPreSaw_t, *pDRXJCfgPreSaw_t;
typedef struct {
DRXStandard_t standard; /* standard to which these settings apply */
u16_t reference; /* pre SAW reference value, range 0 .. 31 */
Bool_t usePreSaw; /* TRUE algorithms must use pre SAW sense */
} DRXJCfgPreSaw_t, *pDRXJCfgPreSaw_t;
/* DRXJ_CFG_AFE_GAIN */
@ -210,10 +213,10 @@ typedef struct {
* /struct DRXJCfgAfeGain_t
* Interface to configure gain of AFE (LNA + PGA).
*/
typedef struct {
DRXStandard_t standard; /* standard to which these settings apply */
u16_t gain; /* gain in 0.1 dB steps, DRXJ range 140 .. 335 */
} DRXJCfgAfeGain_t, *pDRXJCfgAfeGain_t;
typedef struct {
DRXStandard_t standard; /* standard to which these settings apply */
u16_t gain; /* gain in 0.1 dB steps, DRXJ range 140 .. 335 */
} DRXJCfgAfeGain_t, *pDRXJCfgAfeGain_t;
/**
* /struct DRXJRSErrors_t
@ -222,46 +225,52 @@ typedef struct {
* Container for errors that are received in the most recently finished measurment period
*
*/
typedef struct {
u16_t nrBitErrors; /**< no of pre RS bit errors */
u16_t nrSymbolErrors; /**< no of pre RS symbol errors */
u16_t nrPacketErrors; /**< no of pre RS packet errors */
u16_t nrFailures; /**< no of post RS failures to decode */
u16_t nrSncParFailCount; /**< no of post RS bit erros */
} DRXJRSErrors_t, *pDRXJRSErrors_t;
typedef struct {
u16_t nrBitErrors;
/**< no of pre RS bit errors */
u16_t nrSymbolErrors;
/**< no of pre RS symbol errors */
u16_t nrPacketErrors;
/**< no of pre RS packet errors */
u16_t nrFailures;
/**< no of post RS failures to decode */
u16_t nrSncParFailCount;
/**< no of post RS bit erros */
} DRXJRSErrors_t, *pDRXJRSErrors_t;
/**
* /struct DRXJCfgVSBMisc_t
* symbol error rate
*/
typedef struct{
u32_t symbError; /**< symbol error rate sps */
}DRXJCfgVSBMisc_t, *pDRXJCfgVSBMisc_t;
typedef struct {
u32_t symbError;
/**< symbol error rate sps */
} DRXJCfgVSBMisc_t, *pDRXJCfgVSBMisc_t;
/**
* /enum DRXJMpegOutputClockRate_t
* Mpeg output clock rate.
*
*/
typedef enum {
DRXJ_MPEG_START_WIDTH_1CLKCYC,
DRXJ_MPEG_START_WIDTH_8CLKCYC
} DRXJMpegStartWidth_t, *pDRXJMpegStartWidth_t;
typedef enum {
DRXJ_MPEG_START_WIDTH_1CLKCYC,
DRXJ_MPEG_START_WIDTH_8CLKCYC
} DRXJMpegStartWidth_t, *pDRXJMpegStartWidth_t;
/**
* /enum DRXJMpegOutputClockRate_t
* Mpeg output clock rate.
*
*/
typedef enum {
DRXJ_MPEGOUTPUT_CLOCK_RATE_AUTO,
DRXJ_MPEGOUTPUT_CLOCK_RATE_75973K,
DRXJ_MPEGOUTPUT_CLOCK_RATE_50625K,
DRXJ_MPEGOUTPUT_CLOCK_RATE_37968K,
DRXJ_MPEGOUTPUT_CLOCK_RATE_30375K,
DRXJ_MPEGOUTPUT_CLOCK_RATE_25313K,
DRXJ_MPEGOUTPUT_CLOCK_RATE_21696K
} DRXJMpegOutputClockRate_t, *pDRXJMpegOutputClockRate_t;
typedef enum {
DRXJ_MPEGOUTPUT_CLOCK_RATE_AUTO,
DRXJ_MPEGOUTPUT_CLOCK_RATE_75973K,
DRXJ_MPEGOUTPUT_CLOCK_RATE_50625K,
DRXJ_MPEGOUTPUT_CLOCK_RATE_37968K,
DRXJ_MPEGOUTPUT_CLOCK_RATE_30375K,
DRXJ_MPEGOUTPUT_CLOCK_RATE_25313K,
DRXJ_MPEGOUTPUT_CLOCK_RATE_21696K
} DRXJMpegOutputClockRate_t, *pDRXJMpegOutputClockRate_t;
/**
* /struct DRXJCfgMisc_t
@ -269,49 +278,52 @@ typedef enum {
* reverse MPEG output bit order
* set MPEG output clock rate
*/
typedef struct{
Bool_t disableTEIHandling; /**< if TRUE pass (not change) TEI bit */
Bool_t bitReverseMpegOutout; /**< if TRUE, parallel: msb on MD0; serial: lsb out first */
DRXJMpegOutputClockRate_t mpegOutputClockRate; /**< set MPEG output clock rate that overwirtes the derived one from symbol rate */
DRXJMpegStartWidth_t mpegStartWidth; /**< set MPEG output start width */
}DRXJCfgMpegOutputMisc_t, *pDRXJCfgMpegOutputMisc_t;
typedef struct {
Bool_t disableTEIHandling; /**< if TRUE pass (not change) TEI bit */
Bool_t bitReverseMpegOutout; /**< if TRUE, parallel: msb on MD0; serial: lsb out first */
DRXJMpegOutputClockRate_t mpegOutputClockRate;
/**< set MPEG output clock rate that overwirtes the derived one from symbol rate */
DRXJMpegStartWidth_t mpegStartWidth; /**< set MPEG output start width */
} DRXJCfgMpegOutputMisc_t, *pDRXJCfgMpegOutputMisc_t;
/**
* /enum DRXJXtalFreq_t
* Supported external crystal reference frequency.
*/
typedef enum{
DRXJ_XTAL_FREQ_RSVD,
DRXJ_XTAL_FREQ_27MHZ,
DRXJ_XTAL_FREQ_20P25MHZ,
DRXJ_XTAL_FREQ_4MHZ
}DRXJXtalFreq_t, *pDRXJXtalFreq_t;
typedef enum {
DRXJ_XTAL_FREQ_RSVD,
DRXJ_XTAL_FREQ_27MHZ,
DRXJ_XTAL_FREQ_20P25MHZ,
DRXJ_XTAL_FREQ_4MHZ
} DRXJXtalFreq_t, *pDRXJXtalFreq_t;
/**
* /enum DRXJXtalFreq_t
* Supported external crystal reference frequency.
*/
typedef enum{
DRXJ_I2C_SPEED_400KBPS,
DRXJ_I2C_SPEED_100KBPS
}DRXJI2CSpeed_t, *pDRXJI2CSpeed_t;
typedef enum {
DRXJ_I2C_SPEED_400KBPS,
DRXJ_I2C_SPEED_100KBPS
} DRXJI2CSpeed_t, *pDRXJI2CSpeed_t;
/**
* /struct DRXJCfgHwCfg_t
* Get hw configuration, such as crystal reference frequency, I2C speed, etc...
*/
typedef struct{
DRXJXtalFreq_t xtalFreq; /**< crystal reference frequency */
DRXJI2CSpeed_t i2cSpeed; /**< 100 or 400 kbps */
}DRXJCfgHwCfg_t, *pDRXJCfgHwCfg_t;
typedef struct {
DRXJXtalFreq_t xtalFreq;
/**< crystal reference frequency */
DRXJI2CSpeed_t i2cSpeed;
/**< 100 or 400 kbps */
} DRXJCfgHwCfg_t, *pDRXJCfgHwCfg_t;
/*
* DRXJ_CFG_ATV_MISC
*/
typedef struct{
s16_t peakFilter; /* -8 .. 15 */
u16_t noiseFilter; /* 0 .. 15 */
}DRXJCfgAtvMisc_t, *pDRXJCfgAtvMisc_t;
typedef struct {
s16_t peakFilter; /* -8 .. 15 */
u16_t noiseFilter; /* 0 .. 15 */
} DRXJCfgAtvMisc_t, *pDRXJCfgAtvMisc_t;
/*
* DRXJCfgOOBMisc_t
@ -327,51 +339,51 @@ typedef struct{
#define DRXJ_OOB_STATE_EQT_HUNT 0x30
#define DRXJ_OOB_STATE_SYNC 0x40
typedef struct{
DRXJAgcStatus_t agc;
Bool_t eqLock;
Bool_t symTimingLock;
Bool_t phaseLock;
Bool_t freqLock;
Bool_t digGainLock;
Bool_t anaGainLock;
u8_t state;
}DRXJCfgOOBMisc_t, *pDRXJCfgOOBMisc_t;
typedef struct {
DRXJAgcStatus_t agc;
Bool_t eqLock;
Bool_t symTimingLock;
Bool_t phaseLock;
Bool_t freqLock;
Bool_t digGainLock;
Bool_t anaGainLock;
u8_t state;
} DRXJCfgOOBMisc_t, *pDRXJCfgOOBMisc_t;
/*
* Index of in array of coef
*/
typedef enum {
DRXJ_OOB_LO_POW_MINUS0DB = 0,
DRXJ_OOB_LO_POW_MINUS5DB,
DRXJ_OOB_LO_POW_MINUS10DB,
DRXJ_OOB_LO_POW_MINUS15DB,
DRXJ_OOB_LO_POW_MAX
} DRXJCfgOobLoPower_t, *pDRXJCfgOobLoPower_t;
typedef enum {
DRXJ_OOB_LO_POW_MINUS0DB = 0,
DRXJ_OOB_LO_POW_MINUS5DB,
DRXJ_OOB_LO_POW_MINUS10DB,
DRXJ_OOB_LO_POW_MINUS15DB,
DRXJ_OOB_LO_POW_MAX
} DRXJCfgOobLoPower_t, *pDRXJCfgOobLoPower_t;
/*
* DRXJ_CFG_ATV_EQU_COEF
*/
typedef struct {
s16_t coef0; /* -256 .. 255 */
s16_t coef1; /* -256 .. 255 */
s16_t coef2; /* -256 .. 255 */
s16_t coef3; /* -256 .. 255 */
} DRXJCfgAtvEquCoef_t, *pDRXJCfgAtvEquCoef_t;
typedef struct {
s16_t coef0; /* -256 .. 255 */
s16_t coef1; /* -256 .. 255 */
s16_t coef2; /* -256 .. 255 */
s16_t coef3; /* -256 .. 255 */
} DRXJCfgAtvEquCoef_t, *pDRXJCfgAtvEquCoef_t;
/*
* Index of in array of coef
*/
typedef enum {
DRXJ_COEF_IDX_MN = 0,
DRXJ_COEF_IDX_FM ,
DRXJ_COEF_IDX_L ,
DRXJ_COEF_IDX_LP ,
DRXJ_COEF_IDX_BG ,
DRXJ_COEF_IDX_DK ,
DRXJ_COEF_IDX_I ,
DRXJ_COEF_IDX_MAX
} DRXJCoefArrayIndex_t, *pDRXJCoefArrayIndex_t;
typedef enum {
DRXJ_COEF_IDX_MN = 0,
DRXJ_COEF_IDX_FM,
DRXJ_COEF_IDX_L,
DRXJ_COEF_IDX_LP,
DRXJ_COEF_IDX_BG,
DRXJ_COEF_IDX_DK,
DRXJ_COEF_IDX_I,
DRXJ_COEF_IDX_MAX
} DRXJCoefArrayIndex_t, *pDRXJCoefArrayIndex_t;
/*
* DRXJ_CFG_ATV_OUTPUT
@ -382,37 +394,37 @@ typedef enum {
* Attenuation setting for SIF AGC.
*
*/
typedef enum {
DRXJ_SIF_ATTENUATION_0DB,
DRXJ_SIF_ATTENUATION_3DB,
DRXJ_SIF_ATTENUATION_6DB,
DRXJ_SIF_ATTENUATION_9DB
} DRXJSIFAttenuation_t, *pDRXJSIFAttenuation_t;
typedef enum {
DRXJ_SIF_ATTENUATION_0DB,
DRXJ_SIF_ATTENUATION_3DB,
DRXJ_SIF_ATTENUATION_6DB,
DRXJ_SIF_ATTENUATION_9DB
} DRXJSIFAttenuation_t, *pDRXJSIFAttenuation_t;
/**
* /struct DRXJCfgAtvOutput_t
* SIF attenuation setting.
*
*/
typedef struct {
Bool_t enableCVBSOutput; /* TRUE= enabled */
Bool_t enableSIFOutput; /* TRUE= enabled */
DRXJSIFAttenuation_t sifAttenuation;
} DRXJCfgAtvOutput_t, *pDRXJCfgAtvOutput_t;
typedef struct {
Bool_t enableCVBSOutput; /* TRUE= enabled */
Bool_t enableSIFOutput; /* TRUE= enabled */
DRXJSIFAttenuation_t sifAttenuation;
} DRXJCfgAtvOutput_t, *pDRXJCfgAtvOutput_t;
/*
DRXJ_CFG_ATV_AGC_STATUS (get only)
*/
/* TODO : AFE interface not yet finished, subject to change */
typedef struct {
u16_t rfAgcGain ; /* 0 .. 877 uA */
u16_t ifAgcGain ; /* 0 .. 877 uA */
s16_t videoAgcGain ; /* -75 .. 1972 in 0.1 dB steps */
s16_t audioAgcGain ; /* -4 .. 1020 in 0.1 dB steps */
u16_t rfAgcLoopGain ; /* 0 .. 7 */
u16_t ifAgcLoopGain ; /* 0 .. 7 */
u16_t videoAgcLoopGain; /* 0 .. 7 */
} DRXJCfgAtvAgcStatus_t, *pDRXJCfgAtvAgcStatus_t;
typedef struct {
u16_t rfAgcGain; /* 0 .. 877 uA */
u16_t ifAgcGain; /* 0 .. 877 uA */
s16_t videoAgcGain; /* -75 .. 1972 in 0.1 dB steps */
s16_t audioAgcGain; /* -4 .. 1020 in 0.1 dB steps */
u16_t rfAgcLoopGain; /* 0 .. 7 */
u16_t ifAgcLoopGain; /* 0 .. 7 */
u16_t videoAgcLoopGain; /* 0 .. 7 */
} DRXJCfgAtvAgcStatus_t, *pDRXJCfgAtvAgcStatus_t;
/*============================================================================*/
/*============================================================================*/
@ -433,129 +445,136 @@ typedef struct {
* Global data container for DRXJ specific data.
*
*/
typedef struct {
/* device capabilties (determined during DRX_Open()) */
Bool_t hasLNA; /**< TRUE if LNA (aka PGA) present */
Bool_t hasOOB; /**< TRUE if OOB supported */
Bool_t hasNTSC; /**< TRUE if NTSC supported */
Bool_t hasBTSC; /**< TRUE if BTSC supported */
Bool_t hasSMATX; /**< TRUE if mat_tx is available */
Bool_t hasSMARX; /**< TRUE if mat_rx is available */
Bool_t hasGPIO; /**< TRUE if GPIO is available */
Bool_t hasIRQN; /**< TRUE if IRQN is available */
/* A1/A2/A... */
u8_t mfx; /**< metal fix */
typedef struct {
/* device capabilties (determined during DRX_Open()) */
Bool_t hasLNA; /**< TRUE if LNA (aka PGA) present */
Bool_t hasOOB; /**< TRUE if OOB supported */
Bool_t hasNTSC; /**< TRUE if NTSC supported */
Bool_t hasBTSC; /**< TRUE if BTSC supported */
Bool_t hasSMATX; /**< TRUE if mat_tx is available */
Bool_t hasSMARX; /**< TRUE if mat_rx is available */
Bool_t hasGPIO; /**< TRUE if GPIO is available */
Bool_t hasIRQN; /**< TRUE if IRQN is available */
/* A1/A2/A... */
u8_t mfx; /**< metal fix */
/* tuner settings */
Bool_t mirrorFreqSpectOOB; /**< tuner inversion (TRUE = tuner mirrors the signal */
/* tuner settings */
Bool_t mirrorFreqSpectOOB;/**< tuner inversion (TRUE = tuner mirrors the signal */
/* standard/channel settings */
DRXStandard_t standard; /**< current standard information */
DRXConstellation_t constellation; /**< current constellation */
DRXFrequency_t frequency; /**< center signal frequency in KHz */
DRXBandwidth_t currBandwidth; /**< current channel bandwidth */
DRXMirror_t mirror; /**< current channel mirror */
/* standard/channel settings */
DRXStandard_t standard; /**< current standard information */
DRXConstellation_t constellation;
/**< current constellation */
DRXFrequency_t frequency; /**< center signal frequency in KHz */
DRXBandwidth_t currBandwidth;
/**< current channel bandwidth */
DRXMirror_t mirror; /**< current channel mirror */
/* signal quality information */
u32_t fecBitsDesired; /**< BER accounting period */
u16_t fecVdPlen; /**< no of trellis symbols: VD SER measurement period */
u16_t qamVdPrescale; /**< Viterbi Measurement Prescale */
u16_t qamVdPeriod; /**< Viterbi Measurement period */
u16_t fecRsPlen; /**< defines RS BER measurement period */
u16_t fecRsPrescale; /**< ReedSolomon Measurement Prescale */
u16_t fecRsPeriod; /**< ReedSolomon Measurement period */
Bool_t resetPktErrAcc; /**< Set a flag to reset accumulated packet error */
u16_t pktErrAccStart; /**< Set a flag to reset accumulated packet error */
/* signal quality information */
u32_t fecBitsDesired; /**< BER accounting period */
u16_t fecVdPlen; /**< no of trellis symbols: VD SER measurement period */
u16_t qamVdPrescale; /**< Viterbi Measurement Prescale */
u16_t qamVdPeriod; /**< Viterbi Measurement period */
u16_t fecRsPlen; /**< defines RS BER measurement period */
u16_t fecRsPrescale; /**< ReedSolomon Measurement Prescale */
u16_t fecRsPeriod; /**< ReedSolomon Measurement period */
Bool_t resetPktErrAcc; /**< Set a flag to reset accumulated packet error */
u16_t pktErrAccStart; /**< Set a flag to reset accumulated packet error */
/* HI configuration */
u16_t HICfgTimingDiv; /**< HI Configure() parameter 2 */
u16_t HICfgBridgeDelay; /**< HI Configure() parameter 3 */
u16_t HICfgWakeUpKey; /**< HI Configure() parameter 4 */
u16_t HICfgCtrl; /**< HI Configure() parameter 5 */
u16_t HICfgTransmit; /**< HI Configure() parameter 6 */
/* HI configuration */
u16_t HICfgTimingDiv; /**< HI Configure() parameter 2 */
u16_t HICfgBridgeDelay; /**< HI Configure() parameter 3 */
u16_t HICfgWakeUpKey; /**< HI Configure() parameter 4 */
u16_t HICfgCtrl; /**< HI Configure() parameter 5 */
u16_t HICfgTransmit; /**< HI Configure() parameter 6 */
/* UIO configuartion */
DRXUIOMode_t uioSmaRxMode; /**< current mode of SmaRx pin */
DRXUIOMode_t uioSmaTxMode; /**< current mode of SmaTx pin */
DRXUIOMode_t uioGPIOMode; /**< current mode of ASEL pin */
DRXUIOMode_t uioIRQNMode; /**< current mode of IRQN pin */
/* UIO configuartion */
DRXUIOMode_t uioSmaRxMode;/**< current mode of SmaRx pin */
DRXUIOMode_t uioSmaTxMode;/**< current mode of SmaTx pin */
DRXUIOMode_t uioGPIOMode; /**< current mode of ASEL pin */
DRXUIOMode_t uioIRQNMode; /**< current mode of IRQN pin */
/* IQM fs frequecy shift and inversion */
u32_t iqmFsRateOfs; /**< frequency shifter setting after setchannel */
Bool_t posImage; /**< Ture: positive image */
/* IQM RC frequecy shift */
u32_t iqmRcRateOfs; /**< frequency shifter setting after setchannel */
/* IQM fs frequecy shift and inversion */
u32_t iqmFsRateOfs; /**< frequency shifter setting after setchannel */
Bool_t posImage; /**< Ture: positive image */
/* IQM RC frequecy shift */
u32_t iqmRcRateOfs; /**< frequency shifter setting after setchannel */
/* ATV configuartion */
u32_t atvCfgChangedFlags; /**< flag: flags cfg changes */
s16_t atvTopEqu0[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU0__A */
s16_t atvTopEqu1[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU1__A */
s16_t atvTopEqu2[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU2__A */
s16_t atvTopEqu3[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU3__A */
Bool_t phaseCorrectionBypass; /**< flag: TRUE=bypass */
s16_t atvTopVidPeak; /**< shadow of ATV_TOP_VID_PEAK__A */
u16_t atvTopNoiseTh; /**< shadow of ATV_TOP_NOISE_TH__A */
Bool_t enableCVBSOutput; /**< flag CVBS ouput enable */
Bool_t enableSIFOutput; /**< flag SIF ouput enable */
DRXJSIFAttenuation_t
sifAttenuation; /**< current SIF att setting */
/* Agc configuration for QAM and VSB */
DRXJCfgAgc_t qamRfAgcCfg; /**< qam RF AGC config */
DRXJCfgAgc_t qamIfAgcCfg; /**< qam IF AGC config */
DRXJCfgAgc_t vsbRfAgcCfg; /**< vsb RF AGC config */
DRXJCfgAgc_t vsbIfAgcCfg; /**< vsb IF AGC config */
/* ATV configuartion */
u32_t atvCfgChangedFlags; /**< flag: flags cfg changes */
s16_t atvTopEqu0[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU0__A */
s16_t atvTopEqu1[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU1__A */
s16_t atvTopEqu2[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU2__A */
s16_t atvTopEqu3[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU3__A */
Bool_t phaseCorrectionBypass;/**< flag: TRUE=bypass */
s16_t atvTopVidPeak; /**< shadow of ATV_TOP_VID_PEAK__A */
u16_t atvTopNoiseTh; /**< shadow of ATV_TOP_NOISE_TH__A */
Bool_t enableCVBSOutput; /**< flag CVBS ouput enable */
Bool_t enableSIFOutput; /**< flag SIF ouput enable */
DRXJSIFAttenuation_t sifAttenuation;
/**< current SIF att setting */
/* Agc configuration for QAM and VSB */
DRXJCfgAgc_t qamRfAgcCfg; /**< qam RF AGC config */
DRXJCfgAgc_t qamIfAgcCfg; /**< qam IF AGC config */
DRXJCfgAgc_t vsbRfAgcCfg; /**< vsb RF AGC config */
DRXJCfgAgc_t vsbIfAgcCfg; /**< vsb IF AGC config */
/* PGA gain configuration for QAM and VSB */
u16_t qamPgaCfg; /**< qam PGA config */
u16_t vsbPgaCfg; /**< vsb PGA config */
/* PGA gain configuration for QAM and VSB */
u16_t qamPgaCfg; /**< qam PGA config */
u16_t vsbPgaCfg; /**< vsb PGA config */
/* Pre SAW configuration for QAM and VSB */
DRXJCfgPreSaw_t qamPreSawCfg; /**< qam pre SAW config */
DRXJCfgPreSaw_t vsbPreSawCfg; /**< qam pre SAW config */
/* Pre SAW configuration for QAM and VSB */
DRXJCfgPreSaw_t qamPreSawCfg;
/**< qam pre SAW config */
DRXJCfgPreSaw_t vsbPreSawCfg;
/**< qam pre SAW config */
/* Version information */
char vText[2][12]; /**< allocated text versions */
DRXVersion_t vVersion[2]; /**< allocated versions structs */
DRXVersionList_t vListElements[2]; /**< allocated version list */
/* Version information */
char vText[2][12]; /**< allocated text versions */
DRXVersion_t vVersion[2]; /**< allocated versions structs */
DRXVersionList_t vListElements[2];
/**< allocated version list */
/* smart antenna configuration */
Bool_t smartAntInverted;
/* smart antenna configuration */
Bool_t smartAntInverted;
/* Tracking filter setting for OOB */
u16_t oobTrkFilterCfg[8];
Bool_t oobPowerOn;
/* Tracking filter setting for OOB */
u16_t oobTrkFilterCfg[8];
Bool_t oobPowerOn;
/* MPEG static bitrate setting */
u32_t mpegTsStaticBitrate; /**< bitrate static MPEG output */
Bool_t disableTEIhandling; /**< MPEG TS TEI handling */
Bool_t bitReverseMpegOutout; /**< MPEG output bit order */
DRXJMpegOutputClockRate_t
mpegOutputClockRate; /**< MPEG output clock rate */
DRXJMpegStartWidth_t
mpegStartWidth; /**< MPEG Start width */
/* MPEG static bitrate setting */
u32_t mpegTsStaticBitrate; /**< bitrate static MPEG output */
Bool_t disableTEIhandling; /**< MPEG TS TEI handling */
Bool_t bitReverseMpegOutout;/**< MPEG output bit order */
DRXJMpegOutputClockRate_t mpegOutputClockRate;
/**< MPEG output clock rate */
DRXJMpegStartWidth_t mpegStartWidth;
/**< MPEG Start width */
/* Pre SAW & Agc configuration for ATV */
DRXJCfgPreSaw_t atvPreSawCfg; /**< atv pre SAW config */
DRXJCfgAgc_t atvRfAgcCfg; /**< atv RF AGC config */
DRXJCfgAgc_t atvIfAgcCfg; /**< atv IF AGC config */
u16_t atvPgaCfg; /**< atv pga config */
/* Pre SAW & Agc configuration for ATV */
DRXJCfgPreSaw_t atvPreSawCfg;
/**< atv pre SAW config */
DRXJCfgAgc_t atvRfAgcCfg; /**< atv RF AGC config */
DRXJCfgAgc_t atvIfAgcCfg; /**< atv IF AGC config */
u16_t atvPgaCfg; /**< atv pga config */
u32_t currSymbolRate;
u32_t currSymbolRate;
/* pin-safe mode */
Bool_t pdrSafeMode; /**< PDR safe mode activated */
u16_t pdrSafeRestoreValGpio;
u16_t pdrSafeRestoreValVSync;
u16_t pdrSafeRestoreValSmaRx;
u16_t pdrSafeRestoreValSmaTx;
/* pin-safe mode */
Bool_t pdrSafeMode; /**< PDR safe mode activated */
u16_t pdrSafeRestoreValGpio;
u16_t pdrSafeRestoreValVSync;
u16_t pdrSafeRestoreValSmaRx;
u16_t pdrSafeRestoreValSmaTx;
/* OOB pre-saw value */
u16_t oobPreSaw;
DRXJCfgOobLoPower_t oobLoPow;
/* OOB pre-saw value */
u16_t oobPreSaw;
DRXJCfgOobLoPower_t oobLoPow;
DRXAudData_t audData; /**< audio storage */
DRXAudData_t audData;
/**< audio storage */
} DRXJData_t, *pDRXJData_t;
} DRXJData_t, *pDRXJData_t;
/*-------------------------------------------------------------------------
Access MACROS
@ -595,7 +614,6 @@ Access MACROS
DRXJ_ATTR_BTSC_DETECT( d ) = (x); \
} while(0)
/*-------------------------------------------------------------------------
DEFINES
-------------------------------------------------------------------------*/
@ -705,21 +723,20 @@ STRUCTS
Exported FUNCTIONS
-------------------------------------------------------------------------*/
extern DRXStatus_t DRXJ_Open(pDRXDemodInstance_t demod);
extern DRXStatus_t DRXJ_Close(pDRXDemodInstance_t demod);
extern DRXStatus_t DRXJ_Ctrl(pDRXDemodInstance_t demod,
DRXCtrlIndex_t ctrl,
void *ctrlData);
extern DRXStatus_t DRXJ_Open(pDRXDemodInstance_t demod);
extern DRXStatus_t DRXJ_Close(pDRXDemodInstance_t demod);
extern DRXStatus_t DRXJ_Ctrl(pDRXDemodInstance_t demod,
DRXCtrlIndex_t ctrl, void *ctrlData);
/*-------------------------------------------------------------------------
Exported GLOBAL VARIABLES
-------------------------------------------------------------------------*/
extern DRXAccessFunc_t drxDapDRXJFunct_g;
extern DRXDemodFunc_t DRXJFunctions_g;
extern DRXJData_t DRXJData_g;
extern I2CDeviceAddr_t DRXJDefaultAddr_g;
extern DRXCommonAttr_t DRXJDefaultCommAttr_g;
extern DRXDemodInstance_t DRXJDefaultDemod_g;
extern DRXAccessFunc_t drxDapDRXJFunct_g;
extern DRXDemodFunc_t DRXJFunctions_g;
extern DRXJData_t DRXJData_g;
extern I2CDeviceAddr_t DRXJDefaultAddr_g;
extern DRXCommonAttr_t DRXJDefaultCommAttr_g;
extern DRXDemodInstance_t DRXJDefaultDemod_g;
/*-------------------------------------------------------------------------
THE END
@ -727,4 +744,4 @@ THE END
#ifdef __cplusplus
}
#endif
#endif /* __DRXJ_H__ */
#endif /* __DRXJ_H__ */

299
drivers/media/dvb-frontends/drx39xyj/drxj_map.h
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11670
drivers/media/dvb-frontends/drx39xyj/drxj_mc.h
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2085
drivers/media/dvb-frontends/drx39xyj/drxj_mc_vsb.h
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drivers/media/dvb-frontends/drx39xyj/drxj_mc_vsbqam.h
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2
drivers/media/dvb-frontends/drx39xyj/drxj_options.h
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@ -62,4 +62,4 @@ THE END
#ifdef __cplusplus
}
#endif
#endif /* __DRXJ_OPTIONS_H__ */
#endif /* __DRXJ_OPTIONS_H__ */