PCI/PM: add PCIe runtime D3cold support
This patch adds runtime D3cold support and corresponding ACPI platform support. This patch only enables runtime D3cold support; it does not enable D3cold support during system suspend/hibernate. D3cold is the deepest power saving state for a PCIe device, where its main power is removed. While it is in D3cold, you can't access the device at all, not even its configuration space (which is still accessible in D3hot). Therefore the PCI PM registers can not be used to transition into/out of the D3cold state; that must be done by platform logic such as ACPI _PR3. To support wakeup from D3cold, a system may provide auxiliary power, which allows a device to request wakeup using a Beacon or the sideband WAKE# signal. WAKE# is usually connected to platform logic such as ACPI GPE. This is quite different from other power saving states, where devices request wakeup via a PME message on the PCIe link. Some devices, such as those in plug-in slots, have no direct platform logic. For example, there is usually no ACPI _PR3 for them. D3cold support for these devices can be done via the PCIe Downstream Port leading to the device. When the PCIe port is powered on/off, the device is powered on/off too. Wakeup events from the device will be notified to the corresponding PCIe port. For more information about PCIe D3cold and corresponding ACPI support, please refer to: - PCI Express Base Specification Revision 2.0 - Advanced Configuration and Power Interface Specification Revision 5.0 [bhelgaas: changelog] Reviewed-by: Rafael J. Wysocki <rjw@sisk.pl> Originally-by: Zheng Yan <zheng.z.yan@intel.com> Signed-off-by: Huang Ying <ying.huang@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
This commit is contained in:
Huang Ying
Bjorn Helgaas
parent
8497f69668
commit
448bd857d4
7 changed files with 215 additions and 22 deletions
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@ -48,6 +48,12 @@ static void pci_acpi_wake_dev(acpi_handle handle, u32 event, void *context)
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if (event != ACPI_NOTIFY_DEVICE_WAKE || !pci_dev)
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return;
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if (pci_dev->current_state == PCI_D3cold) {
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pci_wakeup_event(pci_dev);
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pm_runtime_resume(&pci_dev->dev);
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return;
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}
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if (!pci_dev->pm_cap || !pci_dev->pme_support
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|| pci_check_pme_status(pci_dev)) {
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if (pci_dev->pme_poll)
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@ -187,10 +193,13 @@ acpi_status pci_acpi_remove_pm_notifier(struct acpi_device *dev)
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static pci_power_t acpi_pci_choose_state(struct pci_dev *pdev)
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{
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int acpi_state;
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int acpi_state, d_max;
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acpi_state = acpi_pm_device_sleep_state(&pdev->dev, NULL,
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ACPI_STATE_D3);
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if (pdev->no_d3cold)
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d_max = ACPI_STATE_D3_HOT;
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else
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d_max = ACPI_STATE_D3_COLD;
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acpi_state = acpi_pm_device_sleep_state(&pdev->dev, NULL, d_max);
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if (acpi_state < 0)
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return PCI_POWER_ERROR;
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@ -297,7 +306,13 @@ static void acpi_pci_propagate_run_wake(struct pci_bus *bus, bool enable)
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static int acpi_pci_run_wake(struct pci_dev *dev, bool enable)
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{
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if (dev->pme_interrupt)
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/*
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* Per PCI Express Base Specification Revision 2.0 section
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* 5.3.3.2 Link Wakeup, platform support is needed for D3cold
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* waking up to power on the main link even if there is PME
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* support for D3cold
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*/
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if (dev->pme_interrupt && !dev->runtime_d3cold)
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return 0;
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if (!acpi_pm_device_run_wake(&dev->dev, enable))
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@ -1019,10 +1019,13 @@ static int pci_pm_runtime_suspend(struct device *dev)
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if (!pm || !pm->runtime_suspend)
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return -ENOSYS;
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pci_dev->no_d3cold = false;
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error = pm->runtime_suspend(dev);
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suspend_report_result(pm->runtime_suspend, error);
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if (error)
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return error;
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if (!pci_dev->d3cold_allowed)
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pci_dev->no_d3cold = true;
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pci_fixup_device(pci_fixup_suspend, pci_dev);
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@ -1044,6 +1047,7 @@ static int pci_pm_runtime_suspend(struct device *dev)
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static int pci_pm_runtime_resume(struct device *dev)
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{
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int rc;
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struct pci_dev *pci_dev = to_pci_dev(dev);
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const struct dev_pm_ops *pm = dev->driver ? dev->driver->pm : NULL;
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@ -1054,7 +1058,11 @@ static int pci_pm_runtime_resume(struct device *dev)
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__pci_enable_wake(pci_dev, PCI_D0, true, false);
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pci_fixup_device(pci_fixup_resume, pci_dev);
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return pm->runtime_resume(dev);
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rc = pm->runtime_resume(dev);
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pci_dev->runtime_d3cold = false;
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return rc;
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}
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static int pci_pm_runtime_idle(struct device *dev)
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@ -28,6 +28,7 @@
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#include <linux/pci-aspm.h>
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#include <linux/slab.h>
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#include <linux/vgaarb.h>
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#include <linux/pm_runtime.h>
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#include "pci.h"
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static int sysfs_initialized; /* = 0 */
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@ -378,6 +379,31 @@ dev_bus_rescan_store(struct device *dev, struct device_attribute *attr,
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#endif
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#if defined(CONFIG_PM_RUNTIME) && defined(CONFIG_ACPI)
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static ssize_t d3cold_allowed_store(struct device *dev,
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struct device_attribute *attr,
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const char *buf, size_t count)
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{
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struct pci_dev *pdev = to_pci_dev(dev);
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unsigned long val;
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if (strict_strtoul(buf, 0, &val) < 0)
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return -EINVAL;
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pdev->d3cold_allowed = !!val;
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pm_runtime_resume(dev);
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return count;
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}
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static ssize_t d3cold_allowed_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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struct pci_dev *pdev = to_pci_dev(dev);
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return sprintf (buf, "%u\n", pdev->d3cold_allowed);
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}
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#endif
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struct device_attribute pci_dev_attrs[] = {
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__ATTR_RO(resource),
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__ATTR_RO(vendor),
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@ -401,6 +427,9 @@ struct device_attribute pci_dev_attrs[] = {
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#ifdef CONFIG_HOTPLUG
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__ATTR(remove, (S_IWUSR|S_IWGRP), NULL, remove_store),
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__ATTR(rescan, (S_IWUSR|S_IWGRP), NULL, dev_rescan_store),
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#endif
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#if defined(CONFIG_PM_RUNTIME) && defined(CONFIG_ACPI)
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__ATTR(d3cold_allowed, 0644, d3cold_allowed_show, d3cold_allowed_store),
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#endif
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__ATTR_NULL,
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};
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@ -622,7 +622,8 @@ static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
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dev_info(&dev->dev, "Refused to change power state, "
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"currently in D%d\n", dev->current_state);
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/* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
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/*
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* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
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* INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
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* from D3hot to D0 _may_ perform an internal reset, thereby
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* going to "D0 Uninitialized" rather than "D0 Initialized".
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@ -654,6 +655,16 @@ void pci_update_current_state(struct pci_dev *dev, pci_power_t state)
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if (dev->pm_cap) {
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u16 pmcsr;
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/*
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* Configuration space is not accessible for device in
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* D3cold, so just keep or set D3cold for safety
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*/
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if (dev->current_state == PCI_D3cold)
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return;
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if (state == PCI_D3cold) {
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dev->current_state = PCI_D3cold;
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return;
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}
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pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
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dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
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} else {
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@ -694,8 +705,50 @@ static int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state)
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*/
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static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state)
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{
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if (state == PCI_D0)
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if (state == PCI_D0) {
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pci_platform_power_transition(dev, PCI_D0);
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/*
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* Mandatory power management transition delays, see
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* PCI Express Base Specification Revision 2.0 Section
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* 6.6.1: Conventional Reset. Do not delay for
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* devices powered on/off by corresponding bridge,
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* because have already delayed for the bridge.
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*/
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if (dev->runtime_d3cold) {
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msleep(dev->d3cold_delay);
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/*
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* When powering on a bridge from D3cold, the
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* whole hierarchy may be powered on into
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* D0uninitialized state, resume them to give
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* them a chance to suspend again
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*/
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pci_wakeup_bus(dev->subordinate);
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}
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}
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}
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/**
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* __pci_dev_set_current_state - Set current state of a PCI device
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* @dev: Device to handle
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* @data: pointer to state to be set
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*/
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static int __pci_dev_set_current_state(struct pci_dev *dev, void *data)
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{
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pci_power_t state = *(pci_power_t *)data;
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dev->current_state = state;
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return 0;
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}
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/**
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* __pci_bus_set_current_state - Walk given bus and set current state of devices
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* @bus: Top bus of the subtree to walk.
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* @state: state to be set
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*/
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static void __pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state)
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{
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if (bus)
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pci_walk_bus(bus, __pci_dev_set_current_state, &state);
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}
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/**
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@ -707,8 +760,15 @@ static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state)
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*/
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int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state)
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{
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return state >= PCI_D0 ?
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pci_platform_power_transition(dev, state) : -EINVAL;
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int ret;
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if (state < PCI_D0)
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return -EINVAL;
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ret = pci_platform_power_transition(dev, state);
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/* Power off the bridge may power off the whole hierarchy */
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if (!ret && state == PCI_D3cold)
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__pci_bus_set_current_state(dev->subordinate, PCI_D3cold);
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return ret;
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}
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EXPORT_SYMBOL_GPL(__pci_complete_power_transition);
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@ -732,8 +792,8 @@ int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
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int error;
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/* bound the state we're entering */
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if (state > PCI_D3hot)
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state = PCI_D3hot;
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if (state > PCI_D3cold)
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state = PCI_D3cold;
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else if (state < PCI_D0)
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state = PCI_D0;
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else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
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@ -748,10 +808,15 @@ int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
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/* This device is quirked not to be put into D3, so
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don't put it in D3 */
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if (state == PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3))
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if (state >= PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3))
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return 0;
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error = pci_raw_set_power_state(dev, state);
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/*
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* To put device in D3cold, we put device into D3hot in native
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* way, then put device into D3cold with platform ops
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*/
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error = pci_raw_set_power_state(dev, state > PCI_D3hot ?
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PCI_D3hot : state);
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if (!__pci_complete_power_transition(dev, state))
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error = 0;
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@ -1497,6 +1562,28 @@ void pci_pme_wakeup_bus(struct pci_bus *bus)
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pci_walk_bus(bus, pci_pme_wakeup, (void *)true);
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}
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/**
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* pci_wakeup - Wake up a PCI device
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* @dev: Device to handle.
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* @ign: ignored parameter
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*/
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static int pci_wakeup(struct pci_dev *pci_dev, void *ign)
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{
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pci_wakeup_event(pci_dev);
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pm_request_resume(&pci_dev->dev);
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return 0;
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}
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/**
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* pci_wakeup_bus - Walk given bus and wake up devices on it
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* @bus: Top bus of the subtree to walk.
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*/
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void pci_wakeup_bus(struct pci_bus *bus)
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{
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if (bus)
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pci_walk_bus(bus, pci_wakeup, NULL);
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}
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/**
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* pci_pme_capable - check the capability of PCI device to generate PME#
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* @dev: PCI device to handle.
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@ -1754,6 +1841,10 @@ int pci_prepare_to_sleep(struct pci_dev *dev)
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if (target_state == PCI_POWER_ERROR)
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return -EIO;
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/* D3cold during system suspend/hibernate is not supported */
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if (target_state > PCI_D3hot)
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target_state = PCI_D3hot;
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pci_enable_wake(dev, target_state, device_may_wakeup(&dev->dev));
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error = pci_set_power_state(dev, target_state);
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@ -1791,12 +1882,16 @@ int pci_finish_runtime_suspend(struct pci_dev *dev)
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if (target_state == PCI_POWER_ERROR)
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return -EIO;
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dev->runtime_d3cold = target_state == PCI_D3cold;
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__pci_enable_wake(dev, target_state, true, pci_dev_run_wake(dev));
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error = pci_set_power_state(dev, target_state);
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if (error)
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if (error) {
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__pci_enable_wake(dev, target_state, true, false);
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dev->runtime_d3cold = false;
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}
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return error;
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}
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@ -1866,6 +1961,7 @@ void pci_pm_init(struct pci_dev *dev)
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dev->pm_cap = pm;
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dev->d3_delay = PCI_PM_D3_WAIT;
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dev->d3cold_delay = PCI_PM_D3COLD_WAIT;
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dev->d1_support = false;
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dev->d2_support = false;
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@ -70,6 +70,7 @@ extern void pci_update_current_state(struct pci_dev *dev, pci_power_t state);
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extern void pci_disable_enabled_device(struct pci_dev *dev);
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extern int pci_finish_runtime_suspend(struct pci_dev *dev);
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extern int __pci_pme_wakeup(struct pci_dev *dev, void *ign);
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extern void pci_wakeup_bus(struct pci_bus *bus);
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extern void pci_pm_init(struct pci_dev *dev);
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extern void platform_pci_wakeup_init(struct pci_dev *dev);
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extern void pci_allocate_cap_save_buffers(struct pci_dev *dev);
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@ -101,12 +101,48 @@ static int pcie_port_resume_noirq(struct device *dev)
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}
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#ifdef CONFIG_PM_RUNTIME
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static int pcie_port_runtime_pm(struct device *dev)
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struct d3cold_info {
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bool no_d3cold;
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unsigned int d3cold_delay;
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};
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static int pci_dev_d3cold_info(struct pci_dev *pdev, void *data)
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{
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struct d3cold_info *info = data;
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info->d3cold_delay = max_t(unsigned int, pdev->d3cold_delay,
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info->d3cold_delay);
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if (pdev->no_d3cold)
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info->no_d3cold = true;
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return 0;
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}
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static int pcie_port_runtime_suspend(struct device *dev)
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{
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struct pci_dev *pdev = to_pci_dev(dev);
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struct d3cold_info d3cold_info = {
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.no_d3cold = false,
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.d3cold_delay = PCI_PM_D3_WAIT,
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};
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/*
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* If any subordinate device disable D3cold, we should not put
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* the port into D3cold. The D3cold delay of port should be
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* the max of that of all subordinate devices.
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*/
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pci_walk_bus(pdev->subordinate, pci_dev_d3cold_info, &d3cold_info);
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pdev->no_d3cold = d3cold_info.no_d3cold;
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pdev->d3cold_delay = d3cold_info.d3cold_delay;
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return 0;
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}
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static int pcie_port_runtime_resume(struct device *dev)
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{
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return 0;
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}
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#else
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#define pcie_port_runtime_pm NULL
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#define pcie_port_runtime_suspend NULL
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#define pcie_port_runtime_resume NULL
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#endif
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static const struct dev_pm_ops pcie_portdrv_pm_ops = {
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@ -117,8 +153,8 @@ static const struct dev_pm_ops pcie_portdrv_pm_ops = {
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.poweroff = pcie_port_device_suspend,
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.restore = pcie_port_device_resume,
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.resume_noirq = pcie_port_resume_noirq,
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.runtime_suspend = pcie_port_runtime_pm,
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.runtime_resume = pcie_port_runtime_pm,
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.runtime_suspend = pcie_port_runtime_suspend,
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.runtime_resume = pcie_port_runtime_resume,
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};
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#define PCIE_PORTDRV_PM_OPS (&pcie_portdrv_pm_ops)
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@ -132,9 +132,10 @@ static inline const char *pci_power_name(pci_power_t state)
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return pci_power_names[1 + (int) state];
|
||||
}
|
||||
|
||||
#define PCI_PM_D2_DELAY 200
|
||||
#define PCI_PM_D3_WAIT 10
|
||||
#define PCI_PM_BUS_WAIT 50
|
||||
#define PCI_PM_D2_DELAY 200
|
||||
#define PCI_PM_D3_WAIT 10
|
||||
#define PCI_PM_D3COLD_WAIT 100
|
||||
#define PCI_PM_BUS_WAIT 50
|
||||
|
||||
/** The pci_channel state describes connectivity between the CPU and
|
||||
* the pci device. If some PCI bus between here and the pci device
|
||||
|
|
@ -278,11 +279,18 @@ struct pci_dev {
|
|||
unsigned int pme_poll:1; /* Poll device's PME status bit */
|
||||
unsigned int d1_support:1; /* Low power state D1 is supported */
|
||||
unsigned int d2_support:1; /* Low power state D2 is supported */
|
||||
unsigned int no_d1d2:1; /* Only allow D0 and D3 */
|
||||
unsigned int no_d1d2:1; /* D1 and D2 are forbidden */
|
||||
unsigned int no_d3cold:1; /* D3cold is forbidden */
|
||||
unsigned int d3cold_allowed:1; /* D3cold is allowed by user */
|
||||
unsigned int mmio_always_on:1; /* disallow turning off io/mem
|
||||
decoding during bar sizing */
|
||||
unsigned int wakeup_prepared:1;
|
||||
unsigned int runtime_d3cold:1; /* whether go through runtime
|
||||
D3cold, not set for devices
|
||||
powered on/off by the
|
||||
corresponding bridge */
|
||||
unsigned int d3_delay; /* D3->D0 transition time in ms */
|
||||
unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */
|
||||
|
||||
#ifdef CONFIG_PCIEASPM
|
||||
struct pcie_link_state *link_state; /* ASPM link state. */
|
||||
|
|
|
|||
Loading…
Reference in a new issue