pinctrl: aspeed: g4: Add pinconf support
Testing for pinctrl-aspeed-g4 was performed on an OpenPOWER Palmetto system, using the strategy outlined in the commit message for the change to the Aspeed pinctrl core. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Andrew Jeffery
Linus Walleij
parent
7f354fd138
commit
47b50b3743
1 changed files with 116 additions and 1 deletions
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@ -2234,6 +2234,110 @@ static const struct aspeed_pin_function aspeed_g4_functions[] = {
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ASPEED_PINCTRL_FUNC(WDTRST2),
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};
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static const struct aspeed_pin_config aspeed_g4_configs[] = {
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/* GPIO banks ranges [A, B], [D, J], [M, R] */
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{ PIN_CONFIG_BIAS_PULL_DOWN, { D6, D5 }, SCU8C, 16 },
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{ PIN_CONFIG_BIAS_DISABLE, { D6, D5 }, SCU8C, 16 },
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{ PIN_CONFIG_BIAS_PULL_DOWN, { J21, E18 }, SCU8C, 17 },
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{ PIN_CONFIG_BIAS_DISABLE, { J21, E18 }, SCU8C, 17 },
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{ PIN_CONFIG_BIAS_PULL_DOWN, { A18, E15 }, SCU8C, 19 },
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{ PIN_CONFIG_BIAS_DISABLE, { A18, E15 }, SCU8C, 19 },
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{ PIN_CONFIG_BIAS_PULL_DOWN, { D15, B14 }, SCU8C, 20 },
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{ PIN_CONFIG_BIAS_DISABLE, { D15, B14 }, SCU8C, 20 },
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{ PIN_CONFIG_BIAS_PULL_DOWN, { D18, C17 }, SCU8C, 21 },
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{ PIN_CONFIG_BIAS_DISABLE, { D18, C17 }, SCU8C, 21 },
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{ PIN_CONFIG_BIAS_PULL_DOWN, { A14, U18 }, SCU8C, 22 },
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{ PIN_CONFIG_BIAS_DISABLE, { A14, U18 }, SCU8C, 22 },
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{ PIN_CONFIG_BIAS_PULL_DOWN, { A8, E7 }, SCU8C, 23 },
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{ PIN_CONFIG_BIAS_DISABLE, { A8, E7 }, SCU8C, 23 },
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{ PIN_CONFIG_BIAS_PULL_DOWN, { C22, E20 }, SCU8C, 24 },
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{ PIN_CONFIG_BIAS_DISABLE, { C22, E20 }, SCU8C, 24 },
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{ PIN_CONFIG_BIAS_PULL_DOWN, { J5, T1 }, SCU8C, 25 },
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{ PIN_CONFIG_BIAS_DISABLE, { J5, T1 }, SCU8C, 25 },
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{ PIN_CONFIG_BIAS_PULL_DOWN, { U1, U5 }, SCU8C, 26 },
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{ PIN_CONFIG_BIAS_DISABLE, { U1, U5 }, SCU8C, 26 },
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{ PIN_CONFIG_BIAS_PULL_DOWN, { V3, V5 }, SCU8C, 27 },
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{ PIN_CONFIG_BIAS_DISABLE, { V3, V5 }, SCU8C, 27 },
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{ PIN_CONFIG_BIAS_PULL_DOWN, { W4, AB2 }, SCU8C, 28 },
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{ PIN_CONFIG_BIAS_DISABLE, { W4, AB2 }, SCU8C, 28 },
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{ PIN_CONFIG_BIAS_PULL_DOWN, { V6, V7 }, SCU8C, 29 },
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{ PIN_CONFIG_BIAS_DISABLE, { V6, V7 }, SCU8C, 29 },
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{ PIN_CONFIG_BIAS_PULL_DOWN, { Y6, AB7 }, SCU8C, 30 },
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{ PIN_CONFIG_BIAS_DISABLE, { Y6, AB7 }, SCU8C, 30 },
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{ PIN_CONFIG_BIAS_PULL_DOWN, { V20, A5 }, SCU8C, 31 },
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{ PIN_CONFIG_BIAS_DISABLE, { V20, A5 }, SCU8C, 31 },
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/* GPIOs T[0-5] (RGMII1 Tx pins) */
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{ PIN_CONFIG_DRIVE_STRENGTH, { A12, A13 }, SCU90, 9 },
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{ PIN_CONFIG_BIAS_PULL_DOWN, { A12, A13 }, SCU90, 12 },
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{ PIN_CONFIG_BIAS_DISABLE, { A12, A13 }, SCU90, 12 },
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/* GPIOs T[6-7], U[0-3] (RGMII2 TX pins) */
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{ PIN_CONFIG_DRIVE_STRENGTH, { D9, D10 }, SCU90, 11 },
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{ PIN_CONFIG_BIAS_PULL_DOWN, { D9, D10 }, SCU90, 14 },
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{ PIN_CONFIG_BIAS_DISABLE, { D9, D10 }, SCU90, 14 },
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/* GPIOs U[4-7], V[0-1] (RGMII1 Rx pins) */
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{ PIN_CONFIG_BIAS_PULL_DOWN, { E11, E10 }, SCU90, 13 },
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{ PIN_CONFIG_BIAS_DISABLE, { E11, E10 }, SCU90, 13 },
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/* GPIOs V[2-7] (RGMII2 Rx pins) */
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{ PIN_CONFIG_BIAS_PULL_DOWN, { C9, C8 }, SCU90, 15 },
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{ PIN_CONFIG_BIAS_DISABLE, { C9, C8 }, SCU90, 15 },
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/* ADC pull-downs (SCUA8[19:4]) */
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{ PIN_CONFIG_BIAS_PULL_DOWN, { L5, L5 }, SCUA8, 4 },
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{ PIN_CONFIG_BIAS_DISABLE, { L5, L5 }, SCUA8, 4 },
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{ PIN_CONFIG_BIAS_PULL_DOWN, { L4, L4 }, SCUA8, 5 },
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{ PIN_CONFIG_BIAS_DISABLE, { L4, L4 }, SCUA8, 5 },
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{ PIN_CONFIG_BIAS_PULL_DOWN, { L3, L3 }, SCUA8, 6 },
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{ PIN_CONFIG_BIAS_DISABLE, { L3, L3 }, SCUA8, 6 },
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{ PIN_CONFIG_BIAS_PULL_DOWN, { L2, L2 }, SCUA8, 7 },
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{ PIN_CONFIG_BIAS_DISABLE, { L2, L2 }, SCUA8, 7 },
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{ PIN_CONFIG_BIAS_PULL_DOWN, { L1, L1 }, SCUA8, 8 },
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{ PIN_CONFIG_BIAS_DISABLE, { L1, L1 }, SCUA8, 8 },
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{ PIN_CONFIG_BIAS_PULL_DOWN, { M5, M5 }, SCUA8, 9 },
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{ PIN_CONFIG_BIAS_DISABLE, { M5, M5 }, SCUA8, 9 },
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{ PIN_CONFIG_BIAS_PULL_DOWN, { M4, M4 }, SCUA8, 10 },
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{ PIN_CONFIG_BIAS_DISABLE, { M4, M4 }, SCUA8, 10 },
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{ PIN_CONFIG_BIAS_PULL_DOWN, { M3, M3 }, SCUA8, 11 },
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{ PIN_CONFIG_BIAS_DISABLE, { M3, M3 }, SCUA8, 11 },
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{ PIN_CONFIG_BIAS_PULL_DOWN, { M2, M2 }, SCUA8, 12 },
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{ PIN_CONFIG_BIAS_DISABLE, { M2, M2 }, SCUA8, 12 },
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{ PIN_CONFIG_BIAS_PULL_DOWN, { M1, M1 }, SCUA8, 13 },
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{ PIN_CONFIG_BIAS_DISABLE, { M1, M1 }, SCUA8, 13 },
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{ PIN_CONFIG_BIAS_PULL_DOWN, { N5, N5 }, SCUA8, 14 },
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{ PIN_CONFIG_BIAS_DISABLE, { N5, N5 }, SCUA8, 14 },
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{ PIN_CONFIG_BIAS_PULL_DOWN, { N4, N4 }, SCUA8, 15 },
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{ PIN_CONFIG_BIAS_DISABLE, { N4, N4 }, SCUA8, 15 },
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{ PIN_CONFIG_BIAS_PULL_DOWN, { N3, N3 }, SCUA8, 16 },
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{ PIN_CONFIG_BIAS_DISABLE, { N3, N3 }, SCUA8, 16 },
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{ PIN_CONFIG_BIAS_PULL_DOWN, { N2, N2 }, SCUA8, 17 },
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{ PIN_CONFIG_BIAS_DISABLE, { N2, N2 }, SCUA8, 17 },
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{ PIN_CONFIG_BIAS_PULL_DOWN, { N1, N1 }, SCUA8, 18 },
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{ PIN_CONFIG_BIAS_DISABLE, { N1, N1 }, SCUA8, 18 },
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{ PIN_CONFIG_BIAS_PULL_DOWN, { P5, P5 }, SCUA8, 19 },
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{ PIN_CONFIG_BIAS_DISABLE, { P5, P5 }, SCUA8, 19 },
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/*
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* Debounce settings for GPIOs D and E passthrough mode are in
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* SCUA8[27:20] and so are managed by pinctrl. Normal GPIO debounce for
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* banks D and E is handled by the GPIO driver - GPIO passthrough is
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* treated like any other non-GPIO mux function. There is a catch
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* however, in that the debounce period is configured in the GPIO
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* controller. Due to this tangle between GPIO and pinctrl we don't yet
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* fully support pass-through debounce.
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*/
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{ PIN_CONFIG_INPUT_DEBOUNCE, { A18, D16 }, SCUA8, 20 },
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{ PIN_CONFIG_INPUT_DEBOUNCE, { B17, A17 }, SCUA8, 21 },
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{ PIN_CONFIG_INPUT_DEBOUNCE, { C16, B16 }, SCUA8, 22 },
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{ PIN_CONFIG_INPUT_DEBOUNCE, { A16, E15 }, SCUA8, 23 },
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{ PIN_CONFIG_INPUT_DEBOUNCE, { D15, C15 }, SCUA8, 24 },
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{ PIN_CONFIG_INPUT_DEBOUNCE, { B15, A15 }, SCUA8, 25 },
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{ PIN_CONFIG_INPUT_DEBOUNCE, { E14, D14 }, SCUA8, 26 },
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{ PIN_CONFIG_INPUT_DEBOUNCE, { C14, B14 }, SCUA8, 27 },
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};
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static struct aspeed_pinctrl_data aspeed_g4_pinctrl_data = {
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.pins = aspeed_g4_pins,
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.npins = ARRAY_SIZE(aspeed_g4_pins),
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@ -2241,6 +2345,8 @@ static struct aspeed_pinctrl_data aspeed_g4_pinctrl_data = {
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.ngroups = ARRAY_SIZE(aspeed_g4_groups),
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.functions = aspeed_g4_functions,
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.nfunctions = ARRAY_SIZE(aspeed_g4_functions),
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.configs = aspeed_g4_configs,
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.nconfigs = ARRAY_SIZE(aspeed_g4_configs),
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};
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static struct pinmux_ops aspeed_g4_pinmux_ops = {
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@ -2257,16 +2363,25 @@ static struct pinctrl_ops aspeed_g4_pinctrl_ops = {
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.get_group_name = aspeed_pinctrl_get_group_name,
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.get_group_pins = aspeed_pinctrl_get_group_pins,
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.pin_dbg_show = aspeed_pinctrl_pin_dbg_show,
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.dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
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.dt_node_to_map = pinconf_generic_dt_node_to_map_all,
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.dt_free_map = pinctrl_utils_free_map,
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};
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static const struct pinconf_ops aspeed_g4_conf_ops = {
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.is_generic = true,
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.pin_config_get = aspeed_pin_config_get,
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.pin_config_set = aspeed_pin_config_set,
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.pin_config_group_get = aspeed_pin_config_group_get,
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.pin_config_group_set = aspeed_pin_config_group_set,
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};
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static struct pinctrl_desc aspeed_g4_pinctrl_desc = {
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.name = "aspeed-g4-pinctrl",
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.pins = aspeed_g4_pins,
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.npins = ARRAY_SIZE(aspeed_g4_pins),
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.pctlops = &aspeed_g4_pinctrl_ops,
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.pmxops = &aspeed_g4_pinmux_ops,
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.confops = &aspeed_g4_conf_ops,
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};
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static int aspeed_g4_pinctrl_probe(struct platform_device *pdev)
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