[PATCH] Fix and enable EDAC sysfs operation
When EDAC was first introduced into the kernel it had a sysfs interface, but due to some problems it was disabled in 2.6.16 and remained disabled in 2.6.17. With feedback, several of the control and attribute files of that interface had some good constructive feedback. PCI Blacklist/Whitelist was a major set which has design issues and it has been removed in this patch. Instead of storing PCI broken parity status in EDAC, it has been moved to the pci_dev structure itself by a previous PCI patch. A future patch will enable that feature in EDAC by utilizing the pci_dev info. The sysfs is now enabled in this patch, with a minimal set of control and attribute files for examining EDAC state and for enabling/disabling the memory and PCI operations. The Documentation for EDAC has also been updated to reflect the new state of EDAC operation. Signed-off-by:Doug Thompson <norsk5@xmisson.com> Cc: Greg KH <greg@kroah.com> Cc: Alan Cox <alan@lxorguk.ukuu.org.uk> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
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@ -35,15 +35,14 @@ the vendor should tie the parity status bits to 0 if they do not intend
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to generate parity. Some vendors do not do this, and thus the parity bit
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can "float" giving false positives.
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The PCI Parity EDAC device has the ability to "skip" known flaky
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cards during the parity scan. These are set by the parity "blacklist"
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interface in the sysfs for PCI Parity. (See the PCI section in the sysfs
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section below.) There is also a parity "whitelist" which is used as
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an explicit list of devices to scan, while the blacklist is a list
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of devices to skip.
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[There are patches in the kernel queue which will allow for storage of
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quirks of PCI devices reporting false parity positives. The 2.6.18
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kernel should have those patches included. When that becomes available,
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then EDAC will be patched to utilize that information to "skip" such
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devices.]
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EDAC will have future error detectors that will be added or integrated
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into EDAC in the following list:
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EDAC will have future error detectors that will be integrated with
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EDAC or added to it, in the following list:
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MCE Machine Check Exception
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MCA Machine Check Architecture
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@ -93,22 +92,24 @@ EDAC lives in the /sys/devices/system/edac directory. Within this directory
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there currently reside 2 'edac' components:
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mc memory controller(s) system
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pci PCI status system
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pci PCI control and status system
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============================================================================
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Memory Controller (mc) Model
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First a background on the memory controller's model abstracted in EDAC.
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Each mc device controls a set of DIMM memory modules. These modules are
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Each 'mc' device controls a set of DIMM memory modules. These modules are
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laid out in a Chip-Select Row (csrowX) and Channel table (chX). There can
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be multiple csrows and two channels.
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be multiple csrows and multiple channels.
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Memory controllers allow for several csrows, with 8 csrows being a typical value.
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Yet, the actual number of csrows depends on the electrical "loading"
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of a given motherboard, memory controller and DIMM characteristics.
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Dual channels allows for 128 bit data transfers to the CPU from memory.
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Some newer chipsets allow for more than 2 channels, like Fully Buffered DIMMs
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(FB-DIMMs). The following example will assume 2 channels:
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Channel 0 Channel 1
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@ -234,23 +235,15 @@ Polling period control file:
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The time period, in milliseconds, for polling for error information.
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Too small a value wastes resources. Too large a value might delay
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necessary handling of errors and might loose valuable information for
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locating the error. 1000 milliseconds (once each second) is about
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right for most uses.
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locating the error. 1000 milliseconds (once each second) is the current
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default. Systems which require all the bandwidth they can get, may
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increase this.
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LOAD TIME: module/kernel parameter: poll_msec=[0|1]
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RUN TIME: echo "1000" >/sys/devices/system/edac/mc/poll_msec
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Module Version read-only attribute file:
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'mc_version'
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The EDAC CORE module's version and compile date are shown here to
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indicate what EDAC is running.
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============================================================================
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'mcX' DIRECTORIES
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@ -284,35 +277,6 @@ Seconds since last counter reset control file:
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DIMM capability attribute file:
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'edac_capability'
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The EDAC (Error Detection and Correction) capabilities/modes of
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the memory controller hardware.
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DIMM Current Capability attribute file:
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'edac_current_capability'
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The EDAC capabilities available with the hardware
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configuration. This may not be the same as "EDAC capability"
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if the correct memory is not used. If a memory controller is
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capable of EDAC, but DIMMs without check bits are in use, then
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Parity, SECDED, S4ECD4ED capabilities will not be available
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even though the memory controller might be capable of those
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modes with the proper memory loaded.
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Memory Type supported on this controller attribute file:
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'supported_mem_type'
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This attribute file displays the memory type, usually
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buffered and unbuffered DIMMs.
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Memory Controller name attribute file:
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'mc_name'
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@ -321,16 +285,6 @@ Memory Controller name attribute file:
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that is being utilized.
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Memory Controller Module name attribute file:
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'module_name'
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This attribute file displays the memory controller module name,
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version and date built. The name of the memory controller
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hardware - some drivers work with multiple controllers and
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this field shows which hardware is present.
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Total memory managed by this memory controller attribute file:
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'size_mb'
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This attribute file will display what type of memory is currently
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on this csrow. Normally, either buffered or unbuffered memory.
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Examples:
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Registered-DDR
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Unbuffered-DDR
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EDAC Mode of operation attribute file:
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'dev_type'
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This attribute file will display what type of DIMM device is
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being utilized. Example: x4
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This attribute file will display what type of DRAM device is
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being utilized on this DIMM.
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Examples:
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x1
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x2
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x4
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x8
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Channel 0 CE Count attribute file:
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@ -522,10 +484,10 @@ SYSTEM LOGGING
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If logging for UEs and CEs are enabled then system logs will have
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error notices indicating errors that have been detected:
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MC0: CE page 0x283, offset 0xce0, grain 8, syndrome 0x6ec3, row 0,
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EDAC MC0: CE page 0x283, offset 0xce0, grain 8, syndrome 0x6ec3, row 0,
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channel 1 "DIMM_B1": amd76x_edac
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MC0: CE page 0x1e5, offset 0xfb0, grain 8, syndrome 0xb741, row 0,
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EDAC MC0: CE page 0x1e5, offset 0xfb0, grain 8, syndrome 0xb741, row 0,
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channel 1 "DIMM_B1": amd76x_edac
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@ -610,64 +572,4 @@ Parity Count:
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PCI Device Whitelist:
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'pci_parity_whitelist'
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This control file allows for an explicit list of PCI devices to be
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scanned for parity errors. Only devices found on this list will
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be examined. The list is a line of hexadecimal VENDOR and DEVICE
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ID tuples:
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1022:7450,1434:16a6
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One or more can be inserted, separated by a comma.
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To write the above list doing the following as one command line:
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echo "1022:7450,1434:16a6"
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> /sys/devices/system/edac/pci/pci_parity_whitelist
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To display what the whitelist is, simply 'cat' the same file.
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PCI Device Blacklist:
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'pci_parity_blacklist'
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This control file allows for a list of PCI devices to be
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skipped for scanning.
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The list is a line of hexadecimal VENDOR and DEVICE ID tuples:
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1022:7450,1434:16a6
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One or more can be inserted, separated by a comma.
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To write the above list doing the following as one command line:
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echo "1022:7450,1434:16a6"
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> /sys/devices/system/edac/pci/pci_parity_blacklist
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To display what the whitelist currently contains,
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simply 'cat' the same file.
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=======================================================================
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PCI Vendor and Devices IDs can be obtained with the lspci command. Using
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the -n option lspci will display the vendor and device IDs. The system
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administrator will have to determine which devices should be scanned or
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skipped.
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The two lists (white and black) are prioritized. blacklist is the lower
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priority and will NOT be utilized when a whitelist has been set.
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Turn OFF a whitelist by an empty echo command:
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echo > /sys/devices/system/edac/pci/pci_parity_whitelist
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and any previous blacklist will be utilized.
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