[PATCH] ARM: 2663/1: straightify TLS register emulation a bit more
Patch from Nicolas Pitre This better express things, and should cover RMK's weird SMP toys. Signed-off-by: Nicolas Pitre Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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3 changed files with 25 additions and 20 deletions
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@ -505,9 +505,9 @@ ENTRY(__switch_to)
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mra r4, r5, acc0
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mra r4, r5, acc0
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stmia ip, {r4, r5}
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stmia ip, {r4, r5}
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#endif
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#endif
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#ifdef CONFIG_HAS_TLS_REG
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#if defined(CONFIG_HAS_TLS_REG)
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mcr p15, 0, r3, c13, c0, 3 @ set TLS register
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mcr p15, 0, r3, c13, c0, 3 @ set TLS register
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#else
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#elif !defined(CONFIG_TLS_REG_EMUL)
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mov r4, #0xffff0fff
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mov r4, #0xffff0fff
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str r3, [r4, #-15] @ TLS val at 0xffff0ff0
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str r3, [r4, #-15] @ TLS val at 0xffff0ff0
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#endif
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#endif
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@ -690,11 +690,7 @@ __kuser_cmpxchg: @ 0xffff0fc0
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__kuser_get_tls: @ 0xffff0fe0
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__kuser_get_tls: @ 0xffff0fe0
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#ifndef CONFIG_HAS_TLS_REG
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#if !defined(CONFIG_HAS_TLS_REG) && !defined(CONFIG_TLS_REG_EMUL)
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#ifdef CONFIG_SMP /* sanity check */
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#error "CONFIG_SMP without CONFIG_HAS_TLS_REG is wrong"
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#endif
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ldr r0, [pc, #(16 - 8)] @ TLS stored at 0xffff0ff0
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ldr r0, [pc, #(16 - 8)] @ TLS stored at 0xffff0ff0
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mov pc, lr
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mov pc, lr
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@ -451,9 +451,9 @@ asmlinkage int arm_syscall(int no, struct pt_regs *regs)
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case NR(set_tls):
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case NR(set_tls):
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thread->tp_value = regs->ARM_r0;
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thread->tp_value = regs->ARM_r0;
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#ifdef CONFIG_HAS_TLS_REG
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#if defined(CONFIG_HAS_TLS_REG)
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asm ("mcr p15, 0, %0, c13, c0, 3" : : "r" (regs->ARM_r0) );
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asm ("mcr p15, 0, %0, c13, c0, 3" : : "r" (regs->ARM_r0) );
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#else
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#elif !defined(CONFIG_TLS_REG_EMUL)
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/*
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/*
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* User space must never try to access this directly.
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* User space must never try to access this directly.
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* Expect your app to break eventually if you do so.
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* Expect your app to break eventually if you do so.
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@ -498,11 +498,14 @@ asmlinkage int arm_syscall(int no, struct pt_regs *regs)
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return 0;
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return 0;
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}
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}
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#if defined(CONFIG_CPU_32v6) && !defined(CONFIG_HAS_TLS_REG)
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#ifdef CONFIG_TLS_REG_EMUL
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/*
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/*
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* We might be running on an ARMv6+ processor which should have the TLS
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* We might be running on an ARMv6+ processor which should have the TLS
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* register, but for some reason we can't use it and have to emulate it.
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* register but for some reason we can't use it, or maybe an SMP system
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* using a pre-ARMv6 processor (there are apparently a few prototypes like
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* that in existence) and therefore access to that register must be
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* emulated.
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*/
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*/
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static int get_tp_trap(struct pt_regs *regs, unsigned int instr)
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static int get_tp_trap(struct pt_regs *regs, unsigned int instr)
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@ -410,17 +410,23 @@ config CPU_BPREDICT_DISABLE
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help
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help
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Say Y here to disable branch prediction. If unsure, say N.
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Say Y here to disable branch prediction. If unsure, say N.
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config TLS_REG_EMUL
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bool
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default y if (SMP || CPU_32v6) && (CPU_32v5 || CPU_32v4 || CPU_32v3)
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help
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We might be running on an ARMv6+ processor which should have the TLS
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register but for some reason we can't use it, or maybe an SMP system
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using a pre-ARMv6 processor (there are apparently a few prototypes
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like that in existence) and therefore access to that register must
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be emulated.
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config HAS_TLS_REG
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config HAS_TLS_REG
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bool
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bool
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depends on CPU_32v6 && !CPU_32v5 && !CPU_32v4 && !CPU_32v3
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depends on CPU_32v6
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default y
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default y if !TLS_REG_EMUL
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help
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help
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This selects support for the CP15 thread register.
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This selects support for the CP15 thread register.
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It is defined to be available on ARMv6 or later. However
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It is defined to be available on ARMv6 or later. If a particular
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if the kernel is configured to support multiple CPUs including
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ARMv6 or later CPU doesn't support it then it must omc;ide "select
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a pre-ARMv6 processors, or if a given ARMv6 processor doesn't
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TLS_REG_EMUL" along with its other caracteristics.
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implement the thread register for some reason, then access to
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this register from user space must be trapped and emulated.
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If user space is relying on the __kuser_get_tls code then
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there should not be any impact.
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