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ARM: arm-soc non-critical fixes for 3.10

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Here is a collection of fixes (and some intermixed cleanups) that were
 considered less important and thus not included in the later parts of
 the 3.9-rc cycle.
 
 It's a bit all over the map, contents wise. A series of ux500 fixes
 and cleanups, a bunch of various fixes for OMAP and tegra, and some for
 Freescale i.MX and even Qualcomm MSM.
 
 Note that there's also a patch on this branch to globally turn off
 -Wmaybe-uninitialized when building with -Os. It's been posted several
 times by Arnd and no dissent was raised, but nobody seemed interested
 to pick it up. So here it is, as the topmost patch.
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Merge tag 'fixes-nc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC non-critical fixes from Olof Johansson:
 "Here is a collection of fixes (and some intermixed cleanups) that were
  considered less important and thus not included in the later parts of
  the 3.9-rc cycle.

  It's a bit all over the map, contents wise.  A series of ux500 fixes
  and cleanups, a bunch of various fixes for OMAP and tegra, and some
  for Freescale i.MX and even Qualcomm MSM.

  Note that there's also a patch on this branch to globally turn off
  -Wmaybe-uninitialized when building with -Os.  It's been posted
  several times by Arnd and no dissent was raised, but nobody seemed
  interested to pick it up.  So here it is, as the topmost patch."

* tag 'fixes-nc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (70 commits)
  Turn off -Wmaybe-uninitialized when building with -Os
  ARM: orion5x: include linux/cpu.h
  ARM: tegra: call cpu_do_idle from C code
  ARM: u300: fix ages old copy/paste bug
  ARM: OMAP2+: add dependencies on ARCH_MULTI_V6/V7
  ARM: tegra: solve adr range issue with THUMB2_KERNEL enabled
  ARM: tegra: fix relocation truncated error when THUMB2_KERNEL enabled
  ARM: tegra: fix build error when THUMB2_KERNEL enabled
  ARM: msm: Fix uncompess.h tx underrun check
  ARM: vexpress: Remove A9 PMU compatible values for non-A9 platforms
  ARM: cpuimx27 and mbimx27: prepend CONFIG_ to Kconfig macro
  ARM: OMAP2+: fix typo "CONFIG_BRIDGE_DVFS"
  ARM: OMAP1: remove "config MACH_OMAP_HTCWIZARD"
  ARM: mach-imx: mach-imx6q: Fix sparse warnings
  ARM: mach-imx: src: Include "common.h
  ARM: mach-imx: gpc: Include "common.h"
  ARM: mach-imx: avic: Staticize *avic_base
  ARM: mach-imx: tzic: Staticize *tzic_base
  ARM: mach-imx: clk: Include "clk.h"
  ARM: mach-imx: clk-busy: Staticize clk_busy_mux_ops
  ...
This commit is contained in:
Linus Torvalds 2013-05-02 08:56:55 -07:00
commit 4d26aa3054
79 changed files with 321 additions and 279 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
Makefile
View file

@ -571,7 +571,7 @@ endif # $(dot-config)
all: vmlinux
ifdef CONFIG_CC_OPTIMIZE_FOR_SIZE
KBUILD_CFLAGS += -Os
KBUILD_CFLAGS += -Os $(call cc-disable-warning,maybe-uninitialized,)
else
KBUILD_CFLAGS += -O2
endif

7
arch/arm/boot/dts/dbx5x0.dtsi
View file

@ -191,7 +191,7 @@
prcmu: prcmu@80157000 {
compatible = "stericsson,db8500-prcmu";
reg = <0x80157000 0x1000>, <0x801b0000 0x8000>, <0x801b8000 0x1000>;
reg = <0x80157000 0x2000>, <0x801b0000 0x8000>, <0x801b8000 0x1000>;
reg-names = "prcmu", "prcmu-tcpm", "prcmu-tcdm";
interrupts = <0 47 0x4>;
#address-cells = <1>;
@ -674,10 +674,13 @@
compatible = "regulator-gpio";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2600000>;
regulator-max-microvolt = <2900000>;
regulator-name = "mmci-reg";
regulator-type = "voltage";
startup-delay-us = <100>;
enable-active-high;
states = <1800000 0x1
2900000 0x0>;

1
arch/arm/boot/dts/href.dtsi
View file

@ -87,6 +87,7 @@
mmc-cap-sd-highspeed;
mmc-cap-mmc-highspeed;
vmmc-supply = <&ab8500_ldo_aux3_reg>;
vqmmc-supply = <&vmmci>;
cd-gpios = <&tc3589x_gpio 3 0x4>;

10
arch/arm/boot/dts/hrefprev60.dts
View file

@ -25,6 +25,14 @@
};
soc-u9500 {
prcmu@80157000 {
ab8500@5 {
ab8500-gpio {
compatible = "stericsson,ab8500-gpio";
};
};
};
i2c@80004000 {
tps61052@33 {
compatible = "tps61052";
@ -40,7 +48,7 @@
vmmci: regulator-gpio {
gpios = <&tc3589x_gpio 18 0x4>;
gpio-enable = <&tc3589x_gpio 17 0x4>;
enable-gpio = <&tc3589x_gpio 17 0x4>;
status = "okay";
};

4
arch/arm/boot/dts/snowball.dts
View file

@ -299,6 +299,10 @@
};
ab8500 {
ab8500-gpio {
compatible = "stericsson,ab8500-gpio";
};
ab8500-regulators {
ab8500_ldo_aux1_reg: ab8500_ldo_aux1 {
regulator-name = "V-DISPLAY";

2
arch/arm/boot/dts/stuib.dtsi
View file

@ -15,7 +15,7 @@
stmpe1601: stmpe1601@40 {
compatible = "st,stmpe1601";
reg = <0x40>;
interrupts = <26 0x1>;
interrupts = <26 0x2>;
interrupt-parent = <&gpio6>;
interrupt-controller;

2
arch/arm/boot/dts/tegra20-colibri-512.dtsi
View file

@ -444,7 +444,7 @@
};
sdhci@c8000600 {
cd-gpios = <&gpio 23 0>; /* gpio PC7 */
cd-gpios = <&gpio 23 1>; /* gpio PC7 */
};
sound {

4
arch/arm/boot/dts/tegra20-harmony.dts
View file

@ -437,7 +437,7 @@
sdhci@c8000200 {
status = "okay";
cd-gpios = <&gpio 69 0>; /* gpio PI5 */
cd-gpios = <&gpio 69 1>; /* gpio PI5 */
wp-gpios = <&gpio 57 0>; /* gpio PH1 */
power-gpios = <&gpio 155 0>; /* gpio PT3 */
bus-width = <4>;
@ -445,7 +445,7 @@
sdhci@c8000600 {
status = "okay";
cd-gpios = <&gpio 58 0>; /* gpio PH2 */
cd-gpios = <&gpio 58 1>; /* gpio PH2 */
wp-gpios = <&gpio 59 0>; /* gpio PH3 */
power-gpios = <&gpio 70 0>; /* gpio PI6 */
bus-width = <8>;

2
arch/arm/boot/dts/tegra20-paz00.dts
View file

@ -436,7 +436,7 @@
sdhci@c8000000 {
status = "okay";
cd-gpios = <&gpio 173 0>; /* gpio PV5 */
cd-gpios = <&gpio 173 1>; /* gpio PV5 */
wp-gpios = <&gpio 57 0>; /* gpio PH1 */
power-gpios = <&gpio 169 0>; /* gpio PV1 */
bus-width = <4>;

2
arch/arm/boot/dts/tegra20-seaboard.dts
View file

@ -584,7 +584,7 @@
sdhci@c8000400 {
status = "okay";
cd-gpios = <&gpio 69 0>; /* gpio PI5 */
cd-gpios = <&gpio 69 1>; /* gpio PI5 */
wp-gpios = <&gpio 57 0>; /* gpio PH1 */
power-gpios = <&gpio 70 0>; /* gpio PI6 */
bus-width = <4>;

2
arch/arm/boot/dts/tegra20-tamonten.dtsi
View file

@ -465,7 +465,7 @@
};
sdhci@c8000600 {
cd-gpios = <&gpio 58 0>; /* gpio PH2 */
cd-gpios = <&gpio 58 1>; /* gpio PH2 */
wp-gpios = <&gpio 59 0>; /* gpio PH3 */
bus-width = <4>;
status = "okay";

2
arch/arm/boot/dts/tegra20-trimslice.dts
View file

@ -325,7 +325,7 @@
sdhci@c8000600 {
status = "okay";
cd-gpios = <&gpio 121 0>; /* gpio PP1 */
cd-gpios = <&gpio 121 1>; /* gpio PP1 */
wp-gpios = <&gpio 122 0>; /* gpio PP2 */
bus-width = <4>;
};

2
arch/arm/boot/dts/tegra20-ventana.dts
View file

@ -520,7 +520,7 @@
sdhci@c8000400 {
status = "okay";
cd-gpios = <&gpio 69 0>; /* gpio PI5 */
cd-gpios = <&gpio 69 1>; /* gpio PI5 */
wp-gpios = <&gpio 57 0>; /* gpio PH1 */
power-gpios = <&gpio 70 0>; /* gpio PI6 */
bus-width = <4>;

1
arch/arm/boot/dts/tegra20-whistler.dts
View file

@ -510,6 +510,7 @@
sdhci@c8000400 {
status = "okay";
cd-gpios = <&gpio 69 1>; /* gpio PI5 */
wp-gpios = <&gpio 173 0>; /* gpio PV5 */
bus-width = <8>;
};

2
arch/arm/boot/dts/tegra30-beaver.dts
View file

@ -257,7 +257,7 @@
sdhci@78000000 {
status = "okay";
cd-gpios = <&gpio 69 0>; /* gpio PI5 */
cd-gpios = <&gpio 69 1>; /* gpio PI5 */
wp-gpios = <&gpio 155 0>; /* gpio PT3 */
power-gpios = <&gpio 31 0>; /* gpio PD7 */
bus-width = <4>;

2
arch/arm/boot/dts/tegra30-cardhu.dtsi
View file

@ -311,7 +311,7 @@
sdhci@78000000 {
status = "okay";
cd-gpios = <&gpio 69 0>; /* gpio PI5 */
cd-gpios = <&gpio 69 1>; /* gpio PI5 */
wp-gpios = <&gpio 155 0>; /* gpio PT3 */
power-gpios = <&gpio 31 0>; /* gpio PD7 */
bus-width = <4>;

2
arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
View file

@ -117,7 +117,7 @@
};
pmu {
compatible = "arm,cortex-a15-pmu", "arm,cortex-a9-pmu";
compatible = "arm,cortex-a15-pmu";
interrupts = <0 68 4>,
<0 69 4>;
};

2
arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
View file

@ -134,7 +134,7 @@
};
pmu {
compatible = "arm,cortex-a15-pmu", "arm,cortex-a9-pmu";
compatible = "arm,cortex-a15-pmu";
interrupts = <0 68 4>,
<0 69 4>;
};

2
arch/arm/boot/dts/vexpress-v2p-ca5s.dts
View file

@ -111,7 +111,7 @@
};
pmu {
compatible = "arm,cortex-a5-pmu", "arm,cortex-a9-pmu";
compatible = "arm,cortex-a5-pmu";
interrupts = <0 68 4>,
<0 69 4>;
};

10
arch/arm/mach-cns3xxx/core.c
View file

@ -31,16 +31,6 @@ static struct map_desc cns3xxx_io_desc[] __initdata = {
.pfn = __phys_to_pfn(CNS3XXX_TIMER1_2_3_BASE),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
.virtual = CNS3XXX_GPIOA_BASE_VIRT,
.pfn = __phys_to_pfn(CNS3XXX_GPIOA_BASE),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
.virtual = CNS3XXX_GPIOB_BASE_VIRT,
.pfn = __phys_to_pfn(CNS3XXX_GPIOB_BASE),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
.virtual = CNS3XXX_MISC_BASE_VIRT,
.pfn = __phys_to_pfn(CNS3XXX_MISC_BASE),

27
arch/arm/mach-cns3xxx/include/mach/cns3xxx.h
View file

@ -20,22 +20,16 @@
#define CNS3XXX_SPI_FLASH_BASE 0x60000000 /* SPI Serial Flash Memory */
#define CNS3XXX_SWITCH_BASE 0x70000000 /* Switch and HNAT Control */
#define CNS3XXX_SWITCH_BASE_VIRT 0xFFF00000
#define CNS3XXX_PPE_BASE 0x70001000 /* HANT */
#define CNS3XXX_PPE_BASE_VIRT 0xFFF50000
#define CNS3XXX_EMBEDDED_SRAM_BASE 0x70002000 /* HANT Embedded SRAM */
#define CNS3XXX_EMBEDDED_SRAM_BASE_VIRT 0xFFF60000
#define CNS3XXX_SSP_BASE 0x71000000 /* Synchronous Serial Port - SPI/PCM/I2C */
#define CNS3XXX_SSP_BASE_VIRT 0xFFF01000
#define CNS3XXX_DMC_BASE 0x72000000 /* DMC Control (DDR2 SDRAM) */
#define CNS3XXX_DMC_BASE_VIRT 0xFFF02000
#define CNS3XXX_SMC_BASE 0x73000000 /* SMC Control */
#define CNS3XXX_SMC_BASE_VIRT 0xFFF03000
#define SMC_MEMC_STATUS_OFFSET 0x000
#define SMC_MEMIF_CFG_OFFSET 0x004
@ -74,13 +68,10 @@
#define SMC_PCELL_ID_3_OFFSET 0xFFC
#define CNS3XXX_GPIOA_BASE 0x74000000 /* GPIO port A */
#define CNS3XXX_GPIOA_BASE_VIRT 0xFFF04000
#define CNS3XXX_GPIOB_BASE 0x74800000 /* GPIO port B */
#define CNS3XXX_GPIOB_BASE_VIRT 0xFFF05000
#define CNS3XXX_RTC_BASE 0x75000000 /* Real Time Clock */
#define CNS3XXX_RTC_BASE_VIRT 0xFFF06000
#define RTC_SEC_OFFSET 0x00
#define RTC_MIN_OFFSET 0x04
@ -112,22 +103,16 @@
#define CNS3XXX_UART0_BASE_VIRT 0xFB002000
#define CNS3XXX_UART1_BASE 0x78400000 /* UART 1 */
#define CNS3XXX_UART1_BASE_VIRT 0xFFF0A000
#define CNS3XXX_UART2_BASE 0x78800000 /* UART 2 */
#define CNS3XXX_UART2_BASE_VIRT 0xFFF0B000
#define CNS3XXX_DMAC_BASE 0x79000000 /* Generic DMA Control */
#define CNS3XXX_DMAC_BASE_VIRT 0xFFF0D000
#define CNS3XXX_CORESIGHT_BASE 0x7A000000 /* CoreSight */
#define CNS3XXX_CORESIGHT_BASE_VIRT 0xFFF0E000
#define CNS3XXX_CRYPTO_BASE 0x7B000000 /* Crypto */
#define CNS3XXX_CRYPTO_BASE_VIRT 0xFFF0F000
#define CNS3XXX_I2S_BASE 0x7C000000 /* I2S */
#define CNS3XXX_I2S_BASE_VIRT 0xFFF10000
#define CNS3XXX_TIMER1_2_3_BASE 0x7C800000 /* Timer */
#define CNS3XXX_TIMER1_2_3_BASE_VIRT 0xFB003000
@ -150,42 +135,31 @@
#define TIMER_FREERUN_CONTROL_OFFSET 0x44
#define CNS3XXX_HCIE_BASE 0x7D000000 /* HCIE Control */
#define CNS3XXX_HCIE_BASE_VIRT 0xFFF30000
#define CNS3XXX_RAID_BASE 0x7E000000 /* RAID Control */
#define CNS3XXX_RAID_BASE_VIRT 0xFFF12000
#define CNS3XXX_AXI_IXC_BASE 0x7F000000 /* AXI IXC */
#define CNS3XXX_AXI_IXC_BASE_VIRT 0xFFF13000
#define CNS3XXX_CLCD_BASE 0x80000000 /* LCD Control */
#define CNS3XXX_CLCD_BASE_VIRT 0xFFF14000
#define CNS3XXX_USBOTG_BASE 0x81000000 /* USB OTG Control */
#define CNS3XXX_USBOTG_BASE_VIRT 0xFFF15000
#define CNS3XXX_USB_BASE 0x82000000 /* USB Host Control */
#define CNS3XXX_SATA2_BASE 0x83000000 /* SATA */
#define CNS3XXX_SATA2_SIZE SZ_16M
#define CNS3XXX_SATA2_BASE_VIRT 0xFFF17000
#define CNS3XXX_CAMERA_BASE 0x84000000 /* Camera Interface */
#define CNS3XXX_CAMERA_BASE_VIRT 0xFFF18000
#define CNS3XXX_SDIO_BASE 0x85000000 /* SDIO */
#define CNS3XXX_SDIO_BASE_VIRT 0xFFF19000
#define CNS3XXX_I2S_TDM_BASE 0x86000000 /* I2S TDM */
#define CNS3XXX_I2S_TDM_BASE_VIRT 0xFFF1A000
#define CNS3XXX_2DG_BASE 0x87000000 /* 2D Graphic Control */
#define CNS3XXX_2DG_BASE_VIRT 0xFFF1B000
#define CNS3XXX_USB_OHCI_BASE 0x88000000 /* USB OHCI */
#define CNS3XXX_L2C_BASE 0x92000000 /* L2 Cache Control */
#define CNS3XXX_L2C_BASE_VIRT 0xFFF27000
#define CNS3XXX_PCIE0_MEM_BASE 0xA0000000 /* PCIe Port 0 IO/Memory Space */
#define CNS3XXX_PCIE0_MEM_BASE_VIRT 0xE0000000
@ -239,7 +213,6 @@
#define CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT (CNS3XXX_TC11MP_SCU_BASE_VIRT + 0x1000)
#define CNS3XXX_TC11MP_L220_BASE 0x92002000 /* L220 registers */
#define CNS3XXX_TC11MP_L220_BASE_VIRT 0xFF002000
/*
* Misc block

2
arch/arm/mach-imx/avic.c
View file

@ -51,7 +51,7 @@
#define AVIC_NUM_IRQS 64
void __iomem *avic_base;
static void __iomem *avic_base;
static struct irq_domain *domain;
static u32 avic_saved_mask_reg[2];

2
arch/arm/mach-imx/clk-busy.c
View file

@ -147,7 +147,7 @@ static int clk_busy_mux_set_parent(struct clk_hw *hw, u8 index)
return ret;
}
struct clk_ops clk_busy_mux_ops = {
static struct clk_ops clk_busy_mux_ops = {
.get_parent = clk_busy_mux_get_parent,
.set_parent = clk_busy_mux_set_parent,
};

1
arch/arm/mach-imx/clk-gate2.c
View file

@ -15,6 +15,7 @@
#include <linux/io.h>
#include <linux/err.h>
#include <linux/string.h>
#include "clk.h"
/**
* DOC: basic gatable clock which can gate and ungate it's ouput

2
arch/arm/mach-imx/clk-pllv1.c
View file

@ -78,7 +78,7 @@ static unsigned long clk_pllv1_recalc_rate(struct clk_hw *hw,
return ll;
}
struct clk_ops clk_pllv1_ops = {
static struct clk_ops clk_pllv1_ops = {
.recalc_rate = clk_pllv1_recalc_rate,
};

2
arch/arm/mach-imx/clk-pllv2.c
View file

@ -229,7 +229,7 @@ static void clk_pllv2_unprepare(struct clk_hw *hw)
__raw_writel(reg, pllbase + MXC_PLL_DP_CTL);
}
struct clk_ops clk_pllv2_ops = {
static struct clk_ops clk_pllv2_ops = {
.prepare = clk_pllv2_prepare,
.unprepare = clk_pllv2_unprepare,
.recalc_rate = clk_pllv2_recalc_rate,

1
arch/arm/mach-imx/clk.c
View file

@ -1,3 +1,4 @@
#include <linux/spinlock.h>
#include "clk.h"
DEFINE_SPINLOCK(imx_ccm_lock);

1
arch/arm/mach-imx/cpu-imx5.c
View file

@ -18,6 +18,7 @@
#include <linux/io.h>
#include "hardware.h"
#include "common.h"
static int mx5_cpu_rev = -1;

1
arch/arm/mach-imx/cpu.c
View file

@ -3,6 +3,7 @@
#include <linux/io.h>
#include "hardware.h"
#include "common.h"
unsigned int __mxc_cpu_type;
EXPORT_SYMBOL(__mxc_cpu_type);

4
arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
View file

@ -46,7 +46,7 @@ static const int eukrea_mbimx27_pins[] __initconst = {
PE10_PF_UART3_CTS,
PE11_PF_UART3_RTS,
/* UART4 */
#if !defined(MACH_EUKREA_CPUIMX27_USEUART4)
#if !defined(CONFIG_MACH_EUKREA_CPUIMX27_USEUART4)
PB26_AF_UART4_RTS,
PB28_AF_UART4_TXD,
PB29_AF_UART4_CTS,
@ -306,7 +306,7 @@ void __init eukrea_mbimx27_baseboard_init(void)
imx27_add_imx_uart1(&uart_pdata);
imx27_add_imx_uart2(&uart_pdata);
#if !defined(MACH_EUKREA_CPUIMX27_USEUART4)
#if !defined(CONFIG_MACH_EUKREA_CPUIMX27_USEUART4)
imx27_add_imx_uart3(&uart_pdata);
#endif

1
arch/arm/mach-imx/gpc.c
View file

@ -16,6 +16,7 @@
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/irqchip/arm-gic.h>
#include "common.h"
#define GPC_IMR1 0x008
#define GPC_PGC_CPU_PDN 0x2a0

2
arch/arm/mach-imx/iomux-imx31.c
View file

@ -40,7 +40,7 @@ static DEFINE_SPINLOCK(gpio_mux_lock);
#define IOMUX_REG_MASK (IOMUX_PADNUM_MASK & ~0x3)
unsigned long mxc_pin_alloc_map[NB_PORTS * 32 / BITS_PER_LONG];
static unsigned long mxc_pin_alloc_map[NB_PORTS * 32 / BITS_PER_LONG];
/*
* set the mode for a IOMUX pin.
*/

19
arch/arm/mach-imx/irq-common.c
View file

@ -21,25 +21,6 @@
#include "irq-common.h"
int imx_irq_set_priority(unsigned char irq, unsigned char prio)
{
struct irq_chip_generic *gc;
struct mxc_extra_irq *exirq;
int ret;
ret = -ENOSYS;
gc = irq_get_chip_data(irq);
if (gc && gc->private) {
exirq = gc->private;
if (exirq->set_priority)
ret = exirq->set_priority(irq, prio);
}
return ret;
}
EXPORT_SYMBOL(imx_irq_set_priority);
int mxc_set_irq_fiq(unsigned int irq, unsigned int type)
{
struct irq_chip_generic *gc;

4
arch/arm/mach-imx/mach-cpuimx27.c
View file

@ -48,7 +48,7 @@ static const int eukrea_cpuimx27_pins[] __initconst = {
PE14_PF_UART1_CTS,
PE15_PF_UART1_RTS,
/* UART4 */
#if defined(MACH_EUKREA_CPUIMX27_USEUART4)
#if defined(CONFIG_MACH_EUKREA_CPUIMX27_USEUART4)
PB26_AF_UART4_RTS,
PB28_AF_UART4_TXD,
PB29_AF_UART4_CTS,
@ -272,7 +272,7 @@ static void __init eukrea_cpuimx27_init(void)
/* SDHC2 can be used for Wifi */
imx27_add_mxc_mmc(1, NULL);
#endif
#if defined(MACH_EUKREA_CPUIMX27_USEUART4)
#if defined(CONFIG_MACH_EUKREA_CPUIMX27_USEUART4)
/* in which case UART4 is also used for Bluetooth */
imx27_add_imx_uart3(&uart_pdata);
#endif

4
arch/arm/mach-imx/mach-imx6q.c
View file

@ -73,7 +73,7 @@ static int imx6q_revision(void)
}
}
void imx6q_restart(char mode, const char *cmd)
static void imx6q_restart(char mode, const char *cmd)
{
struct device_node *np;
void __iomem *wdog_base;
@ -256,7 +256,7 @@ put_node:
of_node_put(np);
}
struct platform_device imx6q_cpufreq_pdev = {
static struct platform_device imx6q_cpufreq_pdev = {
.name = "imx6q-cpufreq",
};

2
arch/arm/mach-imx/mm-imx3.c
View file

@ -82,7 +82,7 @@ static void __iomem *imx3_ioremap_caller(unsigned long phys_addr, size_t size,
return __arm_ioremap_caller(phys_addr, size, mtype, caller);
}
void __init imx3_init_l2x0(void)
static void __init imx3_init_l2x0(void)
{
#ifdef CONFIG_CACHE_L2X0
void __iomem *l2x0_base;

1
arch/arm/mach-imx/src.c
View file

@ -16,6 +16,7 @@
#include <linux/of_address.h>
#include <linux/smp.h>
#include <asm/smp_plat.h>
#include "common.h"
#define SRC_SCR 0x000
#define SRC_GPR1 0x020

2
arch/arm/mach-imx/tzic.c
View file

@ -49,7 +49,7 @@
#define TZIC_SWINT 0x0F00 /* Software Interrupt Rigger Register */
#define TZIC_ID0 0x0FD0 /* Indentification Register 0 */
void __iomem *tzic_base; /* Used as irq controller base in entry-macro.S */
static void __iomem *tzic_base;
static struct irq_domain *domain;
#define TZIC_NUM_IRQS 128

2
arch/arm/mach-msm/include/mach/uncompress.h
View file

@ -37,7 +37,7 @@ static void putc(int c)
* Wait for TX_READY to be set; but skip it if we have a
* TX underrun.
*/
if (UART_DM_SR & 0x08)
if (!(UART_DM_SR & 0x08))
while (!(UART_DM_ISR & 0x80))
cpu_relax();

6
arch/arm/mach-omap1/Kconfig
View file

@ -55,12 +55,6 @@ config MACH_OMAP_H3
TI OMAP 1710 H3 board support. Say Y here if you have such
a board.
config MACH_OMAP_HTCWIZARD
bool "HTC Wizard"
depends on ARCH_OMAP850
help
HTC Wizard smartphone support (AKA QTEK 9100, ...)
config MACH_HERALD
bool "HTC Herald"
depends on ARCH_OMAP850

7
arch/arm/mach-omap2/Kconfig
View file

@ -55,6 +55,7 @@ config SOC_HAS_REALTIME_COUNTER
config ARCH_OMAP2
bool "TI OMAP2"
depends on ARCH_OMAP2PLUS
depends on ARCH_MULTI_V6
default y
select CPU_V6
select MULTI_IRQ_HANDLER
@ -64,6 +65,7 @@ config ARCH_OMAP2
config ARCH_OMAP3
bool "TI OMAP3"
depends on ARCH_OMAP2PLUS
depends on ARCH_MULTI_V7
default y
select ARCH_HAS_OPP
select ARM_CPU_SUSPEND if PM
@ -80,6 +82,7 @@ config ARCH_OMAP4
bool "TI OMAP4"
default y
depends on ARCH_OMAP2PLUS
depends on ARCH_MULTI_V7
select ARCH_HAS_OPP
select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP
select ARM_CPU_SUSPEND if PM
@ -99,6 +102,7 @@ config ARCH_OMAP4
config SOC_OMAP5
bool "TI OMAP5"
depends on ARCH_MULTI_V7
select ARM_CPU_SUSPEND if PM
select ARM_GIC
select CPU_V7
@ -135,6 +139,7 @@ config SOC_TI81XX
config SOC_AM33XX
bool "AM33XX support"
depends on ARCH_MULTI_V7
default y
select ARM_CPU_SUSPEND if PM
select CPU_V7
@ -408,7 +413,7 @@ config OMAP3_SDRC_AC_TIMING
config OMAP4_ERRATA_I688
bool "OMAP4 errata: Async Bridge Corruption"
depends on ARCH_OMAP4 && !ARCH_MULTIPLATFORM
depends on (ARCH_OMAP4 || SOC_OMAP5) && !ARCH_MULTIPLATFORM
select ARCH_HAS_BARRIERS
help
If a data is stalled inside asynchronous bridge because of back

2
arch/arm/mach-omap2/board-2430sdp.c
View file

@ -166,7 +166,7 @@ static void __init sdp2430_display_init(void)
omap_display_init(&sdp2430_dss_data);
}
#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91x_MODULE)
#if IS_ENABLED(CONFIG_SMC91X)
static struct omap_smc91x_platform_data board_smc91x_data = {
.cs = 5,

2
arch/arm/mach-omap2/board-h4.c
View file

@ -246,7 +246,7 @@ static u32 is_gpmc_muxed(void)
return 0;
}
#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91x_MODULE)
#if IS_ENABLED(CONFIG_SMC91X)
static struct omap_smc91x_platform_data board_smc91x_data = {
.cs = 1,

8
arch/arm/mach-omap2/cclock33xx_data.c
View file

@ -958,6 +958,14 @@ int __init am33xx_clk_init(void)
clk_set_parent(&timer3_fck, &sys_clkin_ck);
clk_set_parent(&timer6_fck, &sys_clkin_ck);
/*
* The On-Chip 32K RC Osc clock is not an accurate clock-source as per
* the design/spec, so as a result, for example, timer which supposed
* to get expired @60Sec, but will expire somewhere ~@40Sec, which is
* not expected by any use-case, so change WDT1 clock source to PRCM
* 32KHz clock.
*/
clk_set_parent(&wdt1_fck, &clkdiv32k_ick);
return 0;
}

30
arch/arm/mach-omap2/dpll3xxx.c
View file

@ -307,10 +307,10 @@ static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 freqsel)
_omap3_noncore_dpll_bypass(clk);
/*
* Set jitter correction. No jitter correction for OMAP4 and 3630
* since freqsel field is no longer present
* Set jitter correction. Jitter correction applicable for OMAP343X
* only since freqsel field is no longer present on other devices.
*/
if (!soc_is_am33xx() && !cpu_is_omap44xx() && !cpu_is_omap3630()) {
if (cpu_is_omap343x()) {
v = __raw_readl(dd->control_reg);
v &= ~dd->freqsel_mask;
v |= freqsel << __ffs(dd->freqsel_mask);
@ -480,29 +480,30 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
if (!dd)
return -EINVAL;
__clk_prepare(dd->clk_bypass);
clk_enable(dd->clk_bypass);
__clk_prepare(dd->clk_ref);
clk_enable(dd->clk_ref);
if (__clk_get_rate(dd->clk_bypass) == rate &&
(dd->modes & (1 << DPLL_LOW_POWER_BYPASS))) {
pr_debug("%s: %s: set rate: entering bypass.\n",
__func__, __clk_get_name(hw->clk));
__clk_prepare(dd->clk_bypass);
clk_enable(dd->clk_bypass);
ret = _omap3_noncore_dpll_bypass(clk);
if (!ret)
new_parent = dd->clk_bypass;
clk_disable(dd->clk_bypass);
__clk_unprepare(dd->clk_bypass);
} else {
__clk_prepare(dd->clk_ref);
clk_enable(dd->clk_ref);
if (dd->last_rounded_rate != rate)
rate = __clk_round_rate(hw->clk, rate);
if (dd->last_rounded_rate == 0)
return -EINVAL;
/* No freqsel on AM335x, OMAP4 and OMAP3630 */
if (!soc_is_am33xx() && !cpu_is_omap44xx() &&
!cpu_is_omap3630()) {
/* Freqsel is available only on OMAP343X devices */
if (cpu_is_omap343x()) {
freqsel = _omap3_dpll_compute_freqsel(clk,
dd->last_rounded_n);
WARN_ON(!freqsel);
@ -514,6 +515,8 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
ret = omap3_noncore_dpll_program(clk, freqsel);
if (!ret)
new_parent = dd->clk_ref;
clk_disable(dd->clk_ref);
__clk_unprepare(dd->clk_ref);
}
/*
* FIXME - this is all wrong. common code handles reparenting and
@ -525,11 +528,6 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
if (!ret)
__clk_reparent(hw->clk, new_parent);
clk_disable(dd->clk_ref);
__clk_unprepare(dd->clk_ref);
clk_disable(dd->clk_bypass);
__clk_unprepare(dd->clk_bypass);
return 0;
}

4
arch/arm/mach-omap2/dsp.c
View file

@ -26,7 +26,7 @@
#include "control.h"
#include "cm2xxx_3xxx.h"
#include "prm2xxx_3xxx.h"
#ifdef CONFIG_BRIDGE_DVFS
#ifdef CONFIG_TIDSPBRIDGE_DVFS
#include "omap-pm.h"
#endif
@ -35,7 +35,7 @@
static struct platform_device *omap_dsp_pdev;
static struct omap_dsp_platform_data omap_dsp_pdata __initdata = {
#ifdef CONFIG_BRIDGE_DVFS
#ifdef CONFIG_TIDSPBRIDGE_DVFS
.dsp_set_min_opp = omap_pm_dsp_set_min_opp,
.dsp_get_opp = omap_pm_dsp_get_opp,
.cpu_set_freq = omap_pm_cpu_set_freq,

12
arch/arm/mach-omap2/id.c
View file

@ -529,22 +529,28 @@ void __init omap5xxx_check_revision(void)
case 0xb942:
switch (rev) {
case 0:
default:
omap_revision = OMAP5430_REV_ES1_0;
break;
case 1:
default:
omap_revision = OMAP5430_REV_ES2_0;
}
break;
case 0xb998:
switch (rev) {
case 0:
default:
omap_revision = OMAP5432_REV_ES1_0;
break;
case 1:
default:
omap_revision = OMAP5432_REV_ES2_0;
}
break;
default:
/* Unknown default to latest silicon rev as default*/
omap_revision = OMAP5430_REV_ES1_0;
omap_revision = OMAP5430_REV_ES2_0;
}
pr_info("OMAP%04x ES%d.0\n",

9
arch/arm/mach-omap2/io.c
View file

@ -277,6 +277,14 @@ static struct map_desc omap54xx_io_desc[] __initdata = {
.length = L4_PER_54XX_SIZE,
.type = MT_DEVICE,
},
#ifdef CONFIG_OMAP4_ERRATA_I688
{
.virtual = OMAP4_SRAM_VA,
.pfn = __phys_to_pfn(OMAP4_SRAM_PA),
.length = PAGE_SIZE,
.type = MT_MEMORY_SO,
},
#endif
};
#endif
@ -329,6 +337,7 @@ void __init omap4_map_io(void)
void __init omap5_map_io(void)
{
iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc));
omap_barriers_init();
}
#endif
/*

10
arch/arm/mach-omap2/omap4-common.c
View file

@ -240,15 +240,21 @@ void __iomem *omap4_get_sar_ram_base(void)
*/
static int __init omap4_sar_ram_init(void)
{
unsigned long sar_base;
/*
* To avoid code running on other OMAPs in
* multi-omap builds
*/
if (!cpu_is_omap44xx())
if (cpu_is_omap44xx())
sar_base = OMAP44XX_SAR_RAM_BASE;
else if (soc_is_omap54xx())
sar_base = OMAP54XX_SAR_RAM_BASE;
else
return -ENOMEM;
/* Static mapping, never released */
sar_ram_base = ioremap(OMAP44XX_SAR_RAM_BASE, SZ_16K);
sar_ram_base = ioremap(sar_base, SZ_16K);
if (WARN_ON(!sar_ram_base))
return -ENOMEM;

14
arch/arm/mach-omap2/omap4-sar-layout.h
View file

@ -48,13 +48,13 @@
#define SAR_BACKUP_STATUS_WAKEUPGEN 0x10
/* WakeUpGen save restore offset from OMAP54XX_SAR_RAM_BASE */
#define OMAP5_WAKEUPGENENB_OFFSET_CPU0 (SAR_BANK3_OFFSET + 0x8d4)
#define OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU0 (SAR_BANK3_OFFSET + 0x8e8)
#define OMAP5_WAKEUPGENENB_OFFSET_CPU1 (SAR_BANK3_OFFSET + 0x8fc)
#define OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU1 (SAR_BANK3_OFFSET + 0x910)
#define OMAP5_AUXCOREBOOT0_OFFSET (SAR_BANK3_OFFSET + 0x924)
#define OMAP5_AUXCOREBOOT1_OFFSET (SAR_BANK3_OFFSET + 0x928)
#define OMAP5_AMBA_IF_MODE_OFFSET (SAR_BANK3_OFFSET + 0x92c)
#define OMAP5_WAKEUPGENENB_OFFSET_CPU0 (SAR_BANK3_OFFSET + 0x9dc)
#define OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU0 (SAR_BANK3_OFFSET + 0x9f0)
#define OMAP5_WAKEUPGENENB_OFFSET_CPU1 (SAR_BANK3_OFFSET + 0xa04)
#define OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU1 (SAR_BANK3_OFFSET + 0xa18)
#define OMAP5_AUXCOREBOOT0_OFFSET (SAR_BANK3_OFFSET + 0xa2c)
#define OMAP5_AUXCOREBOOT1_OFFSET (SAR_BANK3_OFFSET + 0x930)
#define OMAP5_AMBA_IF_MODE_OFFSET (SAR_BANK3_OFFSET + 0xa34)
#define OMAP5_SAR_BACKUP_STATUS_OFFSET (SAR_BANK3_OFFSET + 0x800)
#endif

1
arch/arm/mach-omap2/omap54xx.h
View file

@ -28,5 +28,6 @@
#define OMAP54XX_PRCM_MPU_BASE 0x48243000
#define OMAP54XX_SCM_BASE 0x4a002000
#define OMAP54XX_CTRL_BASE 0x4a002800
#define OMAP54XX_SAR_RAM_BASE 0x4ae26000
#endif /* __ASM_SOC_OMAP555554XX_H */

4
arch/arm/mach-omap2/omap_hwmod.c
View file

@ -611,8 +611,6 @@ static int _enable_wakeup(struct omap_hwmod *oh, u32 *v)
/* XXX test pwrdm_get_wken for this hwmod's subsystem */
oh->_int_flags |= _HWMOD_WAKEUP_ENABLED;
return 0;
}
@ -646,8 +644,6 @@ static int _disable_wakeup(struct omap_hwmod *oh, u32 *v)
/* XXX test pwrdm_get_wken for this hwmod's subsystem */
oh->_int_flags &= ~_HWMOD_WAKEUP_ENABLED;
return 0;
}

6
arch/arm/mach-omap2/omap_hwmod.h
View file

@ -482,15 +482,13 @@ struct omap_hwmod_omap4_prcm {
* These are for internal use only and are managed by the omap_hwmod code.
*
* _HWMOD_NO_MPU_PORT: no path exists for the MPU to write to this module
* _HWMOD_WAKEUP_ENABLED: set when the omap_hwmod code has enabled ENAWAKEUP
* _HWMOD_SYSCONFIG_LOADED: set when the OCP_SYSCONFIG value has been cached
* _HWMOD_SKIP_ENABLE: set if hwmod enabled during init (HWMOD_INIT_NO_IDLE) -
* causes the first call to _enable() to only update the pinmux
*/
#define _HWMOD_NO_MPU_PORT (1 << 0)
#define _HWMOD_WAKEUP_ENABLED (1 << 1)
#define _HWMOD_SYSCONFIG_LOADED (1 << 2)
#define _HWMOD_SKIP_ENABLE (1 << 3)
#define _HWMOD_SYSCONFIG_LOADED (1 << 1)
#define _HWMOD_SKIP_ENABLE (1 << 2)
/*
* omap_hwmod._state definitions

15
arch/arm/mach-omap2/omap_hwmod_33xx_data.c
View file

@ -28,6 +28,7 @@
#include "prm-regbits-33xx.h"
#include "i2c.h"
#include "mmc.h"
#include "wd_timer.h"
/*
* IP blocks
@ -2087,8 +2088,21 @@ static struct omap_hwmod am33xx_uart6_hwmod = {
};
/* 'wd_timer' class */
static struct omap_hwmod_class_sysconfig wdt_sysc = {
.rev_offs = 0x0,
.sysc_offs = 0x10,
.syss_offs = 0x14,
.sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
SIDLE_SMART_WKUP),
.sysc_fields = &omap_hwmod_sysc_type1,
};
static struct omap_hwmod_class am33xx_wd_timer_hwmod_class = {
.name = "wd_timer",
.sysc = &wdt_sysc,
.pre_shutdown = &omap2_wd_timer_disable,
};
/*
@ -2099,6 +2113,7 @@ static struct omap_hwmod am33xx_wd_timer1_hwmod = {
.name = "wd_timer2",
.class = &am33xx_wd_timer_hwmod_class,
.clkdm_name = "l4_wkup_clkdm",
.flags = HWMOD_SWSUP_SIDLE,
.main_clk = "wdt1_fck",
.prcm = {
.omap4 = {

18
arch/arm/mach-omap2/powerdomain.c
View file

@ -52,7 +52,6 @@ enum {
#define ALREADYACTIVE_SWITCH 0
#define FORCEWAKEUP_SWITCH 1
#define LOWPOWERSTATE_SWITCH 2
#define ERROR_SWITCH 3
/* pwrdm_list contains all registered struct powerdomains */
static LIST_HEAD(pwrdm_list);
@ -233,10 +232,7 @@ static u8 _pwrdm_save_clkdm_state_and_activate(struct powerdomain *pwrdm,
{
u8 sleep_switch;
if (curr_pwrst < 0) {
WARN_ON(1);
sleep_switch = ERROR_SWITCH;
} else if (curr_pwrst < PWRDM_POWER_ON) {
if (curr_pwrst < PWRDM_POWER_ON) {
if (curr_pwrst > pwrst &&
pwrdm->flags & PWRDM_HAS_LOWPOWERSTATECHANGE &&
arch_pwrdm->pwrdm_set_lowpwrstchange) {
@ -1091,7 +1087,8 @@ int pwrdm_post_transition(struct powerdomain *pwrdm)
*/
int omap_set_pwrdm_state(struct powerdomain *pwrdm, u8 pwrst)
{
u8 curr_pwrst, next_pwrst, sleep_switch;
u8 next_pwrst, sleep_switch;
int curr_pwrst;
int ret = 0;
bool hwsup = false;
@ -1107,16 +1104,17 @@ int omap_set_pwrdm_state(struct powerdomain *pwrdm, u8 pwrst)
pwrdm_lock(pwrdm);
curr_pwrst = pwrdm_read_pwrst(pwrdm);
if (curr_pwrst < 0) {
ret = -EINVAL;
goto osps_out;
}
next_pwrst = pwrdm_read_next_pwrst(pwrdm);
if (curr_pwrst == pwrst && next_pwrst == pwrst)
goto osps_out;
sleep_switch = _pwrdm_save_clkdm_state_and_activate(pwrdm, curr_pwrst,
pwrst, &hwsup);
if (sleep_switch == ERROR_SWITCH) {
ret = -EINVAL;
goto osps_out;
}
ret = pwrdm_set_next_pwrst(pwrdm, pwrst);
if (ret)

6
arch/arm/mach-omap2/prm44xx.c
View file

@ -81,13 +81,13 @@ static struct prm_reset_src_map omap44xx_prm_reset_src_map[] = {
/* Read a register in a CM/PRM instance in the PRM module */
u32 omap4_prm_read_inst_reg(s16 inst, u16 reg)
{
return __raw_readl(OMAP44XX_PRM_REGADDR(inst, reg));
return __raw_readl(prm_base + inst + reg);
}
/* Write into a register in a CM/PRM instance in the PRM module */
void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 reg)
{
__raw_writel(val, OMAP44XX_PRM_REGADDR(inst, reg));
__raw_writel(val, prm_base + inst + reg);
}
/* Read-modify-write a register in a PRM module. Caller must lock */
@ -650,7 +650,7 @@ static struct prm_ll_data omap44xx_prm_ll_data = {
int __init omap44xx_prm_init(void)
{
if (!cpu_is_omap44xx())
if (!cpu_is_omap44xx() && !soc_is_omap54xx())
return 0;
return prm_register(&omap44xx_prm_ll_data);

2
arch/arm/mach-omap2/soc.h
View file

@ -413,7 +413,9 @@ IS_OMAP_TYPE(3430, 0x3430)
#define OMAP54XX_CLASS 0x54000054
#define OMAP5430_REV_ES1_0 (OMAP54XX_CLASS | (0x30 << 16) | (0x10 << 8))
#define OMAP5430_REV_ES2_0 (OMAP54XX_CLASS | (0x30 << 16) | (0x20 << 8))
#define OMAP5432_REV_ES1_0 (OMAP54XX_CLASS | (0x32 << 16) | (0x10 << 8))
#define OMAP5432_REV_ES2_0 (OMAP54XX_CLASS | (0x32 << 16) | (0x20 << 8))
void omap2xxx_check_revision(void);
void omap3xxx_check_revision(void);

5
arch/arm/mach-omap2/timer.c
View file

@ -62,6 +62,7 @@
#define OMAP2_MPU_SOURCE "sys_ck"
#define OMAP3_MPU_SOURCE OMAP2_MPU_SOURCE
#define OMAP4_MPU_SOURCE "sys_clkin_ck"
#define OMAP5_MPU_SOURCE "sys_clkin"
#define OMAP2_32K_SOURCE "func_32k_ck"
#define OMAP3_32K_SOURCE "omap_32k_fck"
#define OMAP4_32K_SOURCE "sys_32k_ck"
@ -487,7 +488,7 @@ static void __init realtime_counter_init(void)
pr_err("%s: ioremap failed\n", __func__);
return;
}
sys_clk = clk_get(NULL, "sys_clkin_ck");
sys_clk = clk_get(NULL, OMAP5_MPU_SOURCE);
if (IS_ERR(sys_clk)) {
pr_err("%s: failed to get system clock handle\n", __func__);
iounmap(base);
@ -620,7 +621,7 @@ void __init omap4_local_timer_init(void)
#ifdef CONFIG_SOC_OMAP5
OMAP_SYS_32K_TIMER_INIT(5, 1, OMAP4_32K_SOURCE, "ti,timer-alwon",
2, OMAP4_MPU_SOURCE);
2, OMAP5_MPU_SOURCE);
void __init omap5_realtime_timer_init(void)
{
int err;

1
arch/arm/mach-orion5x/common.c
View file

@ -19,6 +19,7 @@
#include <linux/ata_platform.h>
#include <linux/delay.h>
#include <linux/clk-provider.h>
#include <linux/cpu.h>
#include <net/dsa.h>
#include <asm/page.h>
#include <asm/setup.h>

7
arch/arm/mach-tegra/board-harmony-pcie.c
View file

@ -62,7 +62,11 @@ int __init harmony_pcie_init(void)
goto err_reg;
}
regulator_enable(regulator);
err = regulator_enable(regulator);
if (err) {
pr_err("%s: regulator_enable failed: %d\n", __func__, err);
goto err_en;
}
err = tegra_pcie_init(true, true);
if (err) {
@ -74,6 +78,7 @@ int __init harmony_pcie_init(void)
err_pcie:
regulator_disable(regulator);
err_en:
regulator_put(regulator);
err_reg:
gpio_free(en_vdd_1v05);

4
arch/arm/mach-tegra/cpuidle-tegra30.c
View file

@ -99,12 +99,8 @@ static bool tegra30_cpu_core_power_down(struct cpuidle_device *dev,
smp_wmb();
save_cpu_arch_register();
cpu_suspend(0, tegra30_sleep_cpu_secondary_finish);
restore_cpu_arch_register();
clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu);
return true;

3
arch/arm/mach-tegra/headsmp.S
View file

@ -7,8 +7,5 @@
ENTRY(tegra_secondary_startup)
bl v7_invalidate_l1
/* Enable coresight */
mov32 r0, 0xC5ACCE55
mcr p14, 0, r0, c7, c12, 6
b secondary_startup
ENDPROC(tegra_secondary_startup)

5
arch/arm/mach-tegra/platsmp.c
View file

@ -91,7 +91,7 @@ static int tegra30_power_up_cpu(unsigned int cpu)
if (cpumask_test_cpu(cpu, &tegra_cpu_init_mask)) {
timeout = jiffies + msecs_to_jiffies(50);
do {
if (!tegra_powergate_is_powered(pwrgateid))
if (tegra_powergate_is_powered(pwrgateid))
goto remove_clamps;
udelay(10);
} while (time_before(jiffies, timeout));
@ -124,6 +124,9 @@ remove_clamps:
/* Remove I/O clamps. */
ret = tegra_powergate_remove_clamping(pwrgateid);
if (ret)
return ret;
udelay(10);
/* Clear flow controller CSR. */

24
arch/arm/mach-tegra/pm.c
View file

@ -46,26 +46,11 @@
#define PMC_CPUPWROFF_TIMER 0xcc
#ifdef CONFIG_PM_SLEEP
static unsigned int g_diag_reg;
static DEFINE_SPINLOCK(tegra_lp2_lock);
static void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
static struct clk *tegra_pclk;
void (*tegra_tear_down_cpu)(void);
void save_cpu_arch_register(void)
{
/* read diagnostic register */
asm("mrc p15, 0, %0, c15, c0, 1" : "=r"(g_diag_reg) : : "cc");
return;
}
void restore_cpu_arch_register(void)
{
/* write diagnostic register */
asm("mcr p15, 0, %0, c15, c0, 1" : : "r"(g_diag_reg) : "cc");
return;
}
static void set_power_timers(unsigned long us_on, unsigned long us_off)
{
unsigned long long ticks;
@ -119,8 +104,6 @@ static void restore_cpu_complex(void)
tegra_cpu_clock_resume();
flowctrl_cpu_suspend_exit(cpu);
restore_cpu_arch_register();
}
/*
@ -145,8 +128,6 @@ static void suspend_cpu_complex(void)
tegra_cpu_clock_suspend();
flowctrl_cpu_suspend_enter(cpu);
save_cpu_arch_register();
}
void tegra_clear_cpu_in_lp2(int phy_cpu_id)
@ -181,6 +162,11 @@ bool tegra_set_cpu_in_lp2(int phy_cpu_id)
return last_cpu;
}
int tegra_cpu_do_idle(void)
{
return cpu_do_idle();
}
static int tegra_sleep_cpu(unsigned long v2p)
{
/* Switch to the identity mapping. */

4
arch/arm/mach-tegra/powergate.c
View file

@ -22,6 +22,7 @@
#include <linux/debugfs.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/export.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/seq_file.h>
@ -75,7 +76,7 @@ static int tegra_powergate_set(int id, bool new_state)
if (status == new_state) {
spin_unlock_irqrestore(&tegra_powergate_lock, flags);
return -EINVAL;
return 0;
}
pmc_write(PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE);
@ -168,6 +169,7 @@ err_clk:
err_power:
return ret;
}
EXPORT_SYMBOL(tegra_powergate_sequence_power_up);
int tegra_cpu_powergate_id(int cpuid)
{

49
arch/arm/mach-tegra/reset-handler.S
View file

@ -41,12 +41,10 @@
*/
ENTRY(tegra_resume)
bl v7_invalidate_l1
/* Enable coresight */
mov32 r0, 0xC5ACCE55
mcr p14, 0, r0, c7, c12, 6
cpu_id r0
cmp r0, #0 @ CPU0?
THUMB( it ne )
bne cpu_resume @ no
#ifdef CONFIG_ARCH_TEGRA_3x_SOC
@ -99,6 +97,8 @@ ENTRY(__tegra_cpu_reset_handler_start)
*
* Register usage within the reset handler:
*
* Others: scratch
* R6 = SoC ID << 8
* R7 = CPU present (to the OS) mask
* R8 = CPU in LP1 state mask
* R9 = CPU in LP2 state mask
@ -114,6 +114,40 @@ ENTRY(__tegra_cpu_reset_handler_start)
ENTRY(__tegra_cpu_reset_handler)
cpsid aif, 0x13 @ SVC mode, interrupts disabled
mov32 r6, TEGRA_APB_MISC_BASE
ldr r6, [r6, #APB_MISC_GP_HIDREV]
and r6, r6, #0xff00
#ifdef CONFIG_ARCH_TEGRA_2x_SOC
t20_check:
cmp r6, #(0x20 << 8)
bne after_t20_check
t20_errata:
# Tegra20 is a Cortex-A9 r1p1
mrc p15, 0, r0, c1, c0, 0 @ read system control register
orr r0, r0, #1 << 14 @ erratum 716044
mcr p15, 0, r0, c1, c0, 0 @ write system control register
mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
orr r0, r0, #1 << 4 @ erratum 742230
orr r0, r0, #1 << 11 @ erratum 751472
mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
b after_errata
after_t20_check:
#endif
#ifdef CONFIG_ARCH_TEGRA_3x_SOC
t30_check:
cmp r6, #(0x30 << 8)
bne after_t30_check
t30_errata:
# Tegra30 is a Cortex-A9 r2p9
mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
orr r0, r0, #1 << 6 @ erratum 743622
orr r0, r0, #1 << 11 @ erratum 751472
mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
b after_errata
after_t30_check:
#endif
after_errata:
mrc p15, 0, r10, c0, c0, 5 @ MPIDR
and r10, r10, #0x3 @ R10 = CPU number
mov r11, #1
@ -129,16 +163,13 @@ ENTRY(__tegra_cpu_reset_handler)
#ifdef CONFIG_ARCH_TEGRA_2x_SOC
/* Are we on Tegra20? */
mov32 r6, TEGRA_APB_MISC_BASE
ldr r0, [r6, #APB_MISC_GP_HIDREV]
and r0, r0, #0xff00
cmp r0, #(0x20 << 8)
cmp r6, #(0x20 << 8)
bne 1f
/* If not CPU0, don't let CPU0 reset CPU1 now that CPU1 is coming up. */
mov32 r6, TEGRA_PMC_BASE
mov32 r5, TEGRA_PMC_BASE
mov r0, #0
cmp r10, #0
strne r0, [r6, #PMC_SCRATCH41]
strne r0, [r5, #PMC_SCRATCH41]
1:
#endif

2
arch/arm/mach-tegra/sleep-tegra20.S
View file

@ -197,7 +197,7 @@ ENTRY(tegra20_sleep_cpu_secondary_finish)
mov r3, #CPU_RESETTABLE
str r3, [r0]
bl cpu_do_idle
bl tegra_cpu_do_idle
/*
* cpu may be reset while in wfi, which will return through

4
arch/arm/mach-tegra/sleep-tegra30.S
View file

@ -66,7 +66,9 @@ ENTRY(tegra30_cpu_shutdown)
FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG | \
FLOW_CTRL_CSR_ENABLE
mov r4, #(1 << 4)
orr r12, r12, r4, lsl r3
ARM( orr r12, r12, r4, lsl r3 )
THUMB( lsl r4, r4, r3 )
THUMB( orr r12, r12, r4 )
str r12, [r1]
/* Halt this CPU. */

2
arch/arm/mach-tegra/sleep.h
View file

@ -92,7 +92,7 @@
#ifdef CONFIG_CACHE_L2X0
.macro l2_cache_resume, tmp1, tmp2, tmp3, phys_l2x0_saved_regs
adr \tmp1, \phys_l2x0_saved_regs
W(adr) \tmp1, \phys_l2x0_saved_regs
ldr \tmp1, [\tmp1]
ldr \tmp2, [\tmp1, #L2X0_R_PHY_BASE]
ldr \tmp3, [\tmp2, #L2X0_CTRL]

2
arch/arm/mach-u300/include/mach/u300-regs.h
View file

@ -95,7 +95,7 @@
#define U300_SPI_BASE (U300_FAST_PER_PHYS_BASE+0x6000)
/* Fast UART1 on U335 only */
#define U300_UART1_BASE (U300_SLOW_PER_PHYS_BASE+0x7000)
#define U300_UART1_BASE (U300_FAST_PER_PHYS_BASE+0x7000)
/*
* SLOW peripherals

14
arch/arm/mach-ux500/board-mop500-regulators.c
View file

@ -30,6 +30,20 @@ struct regulator_init_data gpio_en_3v3_regulator = {
.consumer_supplies = gpio_en_3v3_consumers,
};
static struct regulator_consumer_supply sdi0_reg_consumers[] = {
REGULATOR_SUPPLY("vqmmc", "sdi0"),
};
struct regulator_init_data sdi0_reg_init_data = {
.constraints = {
.min_uV = 1800000,
.max_uV = 2900000,
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE|REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = ARRAY_SIZE(sdi0_reg_consumers),
.consumer_supplies = sdi0_reg_consumers,
};
/*
* TPS61052 regulator
*/

1
arch/arm/mach-ux500/board-mop500-regulators.h
View file

@ -18,6 +18,7 @@ extern struct ab8500_regulator_platform_data ab8500_regulator_plat_data;
extern struct ab8500_regulator_platform_data ab8505_regulator_plat_data;
extern struct regulator_init_data tps61052_regulator;
extern struct regulator_init_data gpio_en_3v3_regulator;
extern struct regulator_init_data sdi0_reg_init_data;
void mop500_regulator_init(void);

51
arch/arm/mach-ux500/board-mop500-sdi.c
View file

@ -31,35 +31,6 @@
* SDI 0 (MicroSD slot)
*/
/* GPIO pins used by the sdi0 level shifter */
static int sdi0_en = -1;
static int sdi0_vsel = -1;
static int mop500_sdi0_ios_handler(struct device *dev, struct mmc_ios *ios)
{
switch (ios->power_mode) {
case MMC_POWER_UP:
case MMC_POWER_ON:
/*
* Level shifter voltage should depend on vdd to when deciding
* on either 1.8V or 2.9V. Once the decision has been made the
* level shifter must be disabled and re-enabled with a changed
* select signal in order to switch the voltage. Since there is
* no framework support yet for indicating 1.8V in vdd, use the
* default 2.9V.
*/
gpio_direction_output(sdi0_vsel, 0);
gpio_direction_output(sdi0_en, 1);
break;
case MMC_POWER_OFF:
gpio_direction_output(sdi0_vsel, 0);
gpio_direction_output(sdi0_en, 0);
break;
}
return 0;
}
#ifdef CONFIG_STE_DMA40
struct stedma40_chan_cfg mop500_sdi0_dma_cfg_rx = {
.mode = STEDMA40_MODE_LOGICAL,
@ -100,22 +71,6 @@ struct mmci_platform_data mop500_sdi0_data = {
static void sdi0_configure(struct device *parent)
{
int ret;
ret = gpio_request(sdi0_en, "level shifter enable");
if (!ret)
ret = gpio_request(sdi0_vsel,
"level shifter 1v8-3v select");
if (ret) {
pr_warning("unable to config sdi0 gpios for level shifter.\n");
return;
}
/* Select the default 2.9V and enable level shifter */
gpio_direction_output(sdi0_vsel, 0);
gpio_direction_output(sdi0_en, 1);
/* Add the device, force v2 to subrevision 1 */
db8500_add_sdi0(parent, &mop500_sdi0_data, U8500_SDI_V2_PERIPHID);
}
@ -123,8 +78,6 @@ static void sdi0_configure(struct device *parent)
void mop500_sdi_tc35892_init(struct device *parent)
{
mop500_sdi0_data.gpio_cd = GPIO_SDMMC_CD;
sdi0_en = GPIO_SDMMC_EN;
sdi0_vsel = GPIO_SDMMC_1V8_3V_SEL;
sdi0_configure(parent);
}
@ -263,8 +216,6 @@ void __init snowball_sdi_init(struct device *parent)
/* External Micro SD slot */
mop500_sdi0_data.gpio_cd = SNOWBALL_SDMMC_CD_GPIO;
mop500_sdi0_data.cd_invert = true;
sdi0_en = SNOWBALL_SDMMC_EN_GPIO;
sdi0_vsel = SNOWBALL_SDMMC_1V8_3V_GPIO;
sdi0_configure(parent);
}
@ -276,8 +227,6 @@ void __init hrefv60_sdi_init(struct device *parent)
db8500_add_sdi4(parent, &mop500_sdi4_data, U8500_SDI_V2_PERIPHID);
/* External Micro SD slot */
mop500_sdi0_data.gpio_cd = HREFV60_SDMMC_CD_GPIO;
sdi0_en = HREFV60_SDMMC_EN_GPIO;
sdi0_vsel = HREFV60_SDMMC_1V8_3V_GPIO;
sdi0_configure(parent);
/* WLAN SDIO channel */
db8500_add_sdi1(parent, &mop500_sdi1_data, U8500_SDI_V2_PERIPHID);

45
arch/arm/mach-ux500/board-mop500.c
View file

@ -25,6 +25,8 @@
#include <linux/mfd/abx500/ab8500.h>
#include <linux/regulator/ab8500.h>
#include <linux/regulator/fixed.h>
#include <linux/regulator/driver.h>
#include <linux/regulator/gpio-regulator.h>
#include <linux/mfd/tc3589x.h>
#include <linux/mfd/tps6105x.h>
#include <linux/mfd/abx500/ab8500-gpio.h>
@ -90,6 +92,37 @@ static struct platform_device snowball_gpio_en_3v3_regulator_dev = {
},
};
/* Dynamically populated. */
static struct gpio sdi0_reg_gpios[] = {
{ 0, GPIOF_OUT_INIT_LOW, "mmci_vsel" },
};
static struct gpio_regulator_state sdi0_reg_states[] = {
{ .value = 2900000, .gpios = (0 << 0) },
{ .value = 1800000, .gpios = (1 << 0) },
};
static struct gpio_regulator_config sdi0_reg_info = {
.supply_name = "ext-mmc-level-shifter",
.gpios = sdi0_reg_gpios,
.nr_gpios = ARRAY_SIZE(sdi0_reg_gpios),
.states = sdi0_reg_states,
.nr_states = ARRAY_SIZE(sdi0_reg_states),
.type = REGULATOR_VOLTAGE,
.enable_high = 1,
.enabled_at_boot = 0,
.init_data = &sdi0_reg_init_data,
.startup_delay = 100,
};
static struct platform_device sdi0_regulator = {
.name = "gpio-regulator",
.id = -1,
.dev = {
.platform_data = &sdi0_reg_info,
},
};
static struct abx500_gpio_platform_data ab8500_gpio_pdata = {
.gpio_base = MOP500_AB8500_PIN_GPIO(1),
};
@ -488,6 +521,7 @@ static struct hash_platform_data u8500_hash1_platform_data = {
/* add any platform devices here - TODO */
static struct platform_device *mop500_platform_devs[] __initdata = {
&mop500_gpio_keys_device,
&sdi0_regulator,
};
#ifdef CONFIG_STE_DMA40
@ -631,6 +665,7 @@ static struct platform_device *snowball_platform_devs[] __initdata = {
&snowball_gpio_en_3v3_regulator_dev,
&u8500_thsens_device,
&u8500_cpufreq_cooling_device,
&sdi0_regulator,
};
static void __init mop500_init_machine(void)
@ -642,6 +677,9 @@ static void __init mop500_init_machine(void)
platform_device_register(&db8500_prcmu_device);
mop500_gpio_keys[0].gpio = GPIO_PROX_SENSOR;
sdi0_reg_info.enable_gpio = GPIO_SDMMC_EN;
sdi0_reg_info.gpios[0].gpio = GPIO_SDMMC_1V8_3V_SEL;
mop500_pinmaps_init();
parent = u8500_init_devices(&ab8500_platdata);
@ -675,6 +713,10 @@ static void __init snowball_init_machine(void)
int i;
platform_device_register(&db8500_prcmu_device);
sdi0_reg_info.enable_gpio = SNOWBALL_SDMMC_EN_GPIO;
sdi0_reg_info.gpios[0].gpio = SNOWBALL_SDMMC_1V8_3V_GPIO;
snowball_pinmaps_init();
parent = u8500_init_devices(&ab8500_platdata);
@ -710,6 +752,9 @@ static void __init hrefv60_init_machine(void)
*/
mop500_gpio_keys[0].gpio = HREFV60_PROX_SENSE_GPIO;
sdi0_reg_info.enable_gpio = HREFV60_SDMMC_EN_GPIO;
sdi0_reg_info.gpios[0].gpio = HREFV60_SDMMC_1V8_3V_GPIO;
hrefv60_pinmaps_init();
parent = u8500_init_devices(&ab8500_platdata);

1
arch/arm/mach-ux500/cpu-db8500.c
View file

@ -282,6 +282,7 @@ static struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
OF_DEV_AUXDATA("st,nomadik-i2c", 0x8012a000, "nmk-i2c.4", NULL),
OF_DEV_AUXDATA("stericsson,db8500-prcmu", 0x80157000, "db8500-prcmu",
&db8500_prcmu_pdata),
OF_DEV_AUXDATA("smsc,lan9115", 0x50000000, "smsc911x", NULL),
/* Requires device name bindings. */
OF_DEV_AUXDATA("stericsson,nmk-pinctrl", U8500_PRCMU_BASE,
"pinctrl-db8500", NULL),

36
drivers/clk/tegra/clk-tegra20.c
View file

@ -711,8 +711,8 @@ static void tegra20_pll_init(void)
}
static const char *cclk_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
"pll_p_cclk", "pll_p_out4_cclk",
"pll_p_out3_cclk", "clk_d", "pll_x" };
"pll_p", "pll_p_out4",
"pll_p_out3", "clk_d", "pll_x" };
static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4",
"pll_p_out3", "pll_p_out2", "clk_d",
"clk_32k", "pll_m_out1" };
@ -721,38 +721,6 @@ static void tegra20_super_clk_init(void)
{
struct clk *clk;
/*
* DIV_U71 dividers for CCLK, these dividers are used only
* if parent clock is fixed rate.
*/
/*
* Clock input to cclk divided from pll_p using
* U71 divider of cclk.
*/
clk = tegra_clk_register_divider("pll_p_cclk", "pll_p",
clk_base + SUPER_CCLK_DIVIDER, 0,
TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
clk_register_clkdev(clk, "pll_p_cclk", NULL);
/*
* Clock input to cclk divided from pll_p_out3 using
* U71 divider of cclk.
*/
clk = tegra_clk_register_divider("pll_p_out3_cclk", "pll_p_out3",
clk_base + SUPER_CCLK_DIVIDER, 0,
TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
clk_register_clkdev(clk, "pll_p_out3_cclk", NULL);
/*
* Clock input to cclk divided from pll_p_out4 using
* U71 divider of cclk.
*/
clk = tegra_clk_register_divider("pll_p_out4_cclk", "pll_p_out4",
clk_base + SUPER_CCLK_DIVIDER, 0,
TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
clk_register_clkdev(clk, "pll_p_out4_cclk", NULL);
/* CCLK */
clk = tegra_clk_register_super_mux("cclk", cclk_parents,
ARRAY_SIZE(cclk_parents), CLK_SET_RATE_PARENT,

3
drivers/clk/ux500/u8500_clk.c
View file

@ -324,7 +324,8 @@ void u8500_clk_init(void)
clk = clk_reg_prcc_pclk("p3_pclk0", "per3clk", U8500_CLKRST3_BASE,
BIT(0), 0);
clk_register_clkdev(clk, NULL, "fsmc");
clk_register_clkdev(clk, "fsmc", NULL);
clk_register_clkdev(clk, NULL, "smsc911x");
clk = clk_reg_prcc_pclk("p3_pclk1", "per3clk", U8500_CLKRST3_BASE,
BIT(1), 0);

9
drivers/mmc/host/mmci.c
View file

@ -1141,6 +1141,11 @@ static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
case MMC_POWER_OFF:
if (!IS_ERR(mmc->supply.vmmc))
mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
if (!IS_ERR(mmc->supply.vqmmc) &&
regulator_is_enabled(mmc->supply.vqmmc))
regulator_disable(mmc->supply.vqmmc);
break;
case MMC_POWER_UP:
if (!IS_ERR(mmc->supply.vmmc))
@ -1155,6 +1160,10 @@ static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
break;
case MMC_POWER_ON:
if (!IS_ERR(mmc->supply.vqmmc) &&
!regulator_is_enabled(mmc->supply.vqmmc))
regulator_enable(mmc->supply.vqmmc);
pwr |= MCI_PWR_ON;
break;
}

29
drivers/net/ethernet/smsc/smsc911x.c
View file

@ -33,6 +33,7 @@
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/crc32.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/etherdevice.h>
@ -144,6 +145,9 @@ struct smsc911x_data {
/* regulators */
struct regulator_bulk_data supplies[SMSC911X_NUM_SUPPLIES];
/* clock */
struct clk *clk;
};
/* Easy access to information */
@ -369,7 +373,7 @@ out:
}
/*
* enable resources, currently just regulators.
* enable regulator and clock resources.
*/
static int smsc911x_enable_resources(struct platform_device *pdev)
{
@ -382,6 +386,13 @@ static int smsc911x_enable_resources(struct platform_device *pdev)
if (ret)
netdev_err(ndev, "failed to enable regulators %d\n",
ret);
if (!IS_ERR(pdata->clk)) {
ret = clk_prepare_enable(pdata->clk);
if (ret < 0)
netdev_err(ndev, "failed to enable clock %d\n", ret);
}
return ret;
}
@ -396,6 +407,10 @@ static int smsc911x_disable_resources(struct platform_device *pdev)
ret = regulator_bulk_disable(ARRAY_SIZE(pdata->supplies),
pdata->supplies);
if (!IS_ERR(pdata->clk))
clk_disable_unprepare(pdata->clk);
return ret;
}
@ -421,6 +436,12 @@ static int smsc911x_request_resources(struct platform_device *pdev)
if (ret)
netdev_err(ndev, "couldn't get regulators %d\n",
ret);
/* Request clock */
pdata->clk = clk_get(&pdev->dev, NULL);
if (IS_ERR(pdata->clk))
netdev_warn(ndev, "couldn't get clock %li\n", PTR_ERR(pdata->clk));
return ret;
}
@ -436,6 +457,12 @@ static void smsc911x_free_resources(struct platform_device *pdev)
/* Free regulators */
regulator_bulk_free(ARRAY_SIZE(pdata->supplies),
pdata->supplies);
/* Free clock */
if (!IS_ERR(pdata->clk)) {
clk_put(pdata->clk);
pdata->clk = NULL;
}
}
/* waits for MAC not busy, with timeout. Only called by smsc911x_mac_read