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ARM: tegra: device tree changes

Browse source 
This branch contains the majority of the device tree changes for Tegra.
 Highlights include:
 
 * Many changes for Tegra114, and the Dalmore board, to enable pinctrl,
   SDHCI/MMC, PWM, DMA, I2C, KBC, SPI, battery, regulators.
 * Adding or enabling suspend wakeup sources on many boards, and adding
   suspend timing parameters, to support the system suspend patches.
 * Adding clocks to the audio-related nodes, so that in 3.11, the audio
   driver can pull these clocks from device tree rather than hard-coding
   clock names.
 * Some small DT fixes/cleanup.
 
 This branch is based on the previous clk pull request.
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Merge tag 'tegra-for-3.10-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/dt2

From Stephen Warren <swarren@wwwdotorg.org>:

ARM: tegra: device tree changes

This branch contains the majority of the device tree changes for Tegra.
Highlights include:

* Many changes for Tegra114, and the Dalmore board, to enable pinctrl,
  SDHCI/MMC, PWM, DMA, I2C, KBC, SPI, battery, regulators.
* Adding or enabling suspend wakeup sources on many boards, and adding
  suspend timing parameters, to support the system suspend patches.
* Adding clocks to the audio-related nodes, so that in 3.11, the audio
  driver can pull these clocks from device tree rather than hard-coding
  clock names.
* Some small DT fixes/cleanup.

This branch is based on the previous clk pull request.

* tag 'tegra-for-3.10-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra: (25 commits)
  clk: tegra: Fix cdev1 and cdev2 IDs
  ARM: dts: tegra: add the PM configurations of PMC
  ARM: tegra: add non-removable and keep-power-in-suspend property for MMC
  ARM: tegra: whistler: add wakeup source for KBC
  ARM: tegra: add power gpio keys to DT
  ARM: tegra: keep power on to SD slot on Dalmore
  ARM: tegra: add clocks property to AC'97 sound nodes
  ARM: tegra: add clocks property to sound nodes
  ARM: tegra: dalmore: add fixed regulator node
  ARM: tegra: dalmore: add TPS65090 node
  ARM: tegra: dalmore: add cpu regulator node
  ARM: tegra: Add sbs-battery node to Dalmore
  ARM: tegra: add DT binding for i2c-tegra
  ARM: tegra: add SPI nodes to Tegra114 DT
  ARM: tegra: add KBC nodes to Tegra114 DT
  ARM: tegra: add aliases and DMA requestor for serial nodes of Tegra114
  ARM: tegra: add I2C nodes to Tegra114 DT
  ARM: tegra: add APB DMA nodes to Tegra114 DT
  ARM: tegra: add PWM nodes to Tegra114 DT
  ARM: tegra: fix the status of PWM DT nodes
  ...

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2013-04-09 17:53:08 +02:00
commit 535409d9b3
25 changed files with 1405 additions and 30 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

60
Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.txt Normal file
View file

@ -0,0 +1,60 @@
NVIDIA Tegra20/Tegra30/Tegra114 I2C controller driver.
Required properties:
- compatible : should be:
"nvidia,tegra114-i2c"
"nvidia,tegra30-i2c"
"nvidia,tegra20-i2c"
"nvidia,tegra20-i2c-dvc"
Details of compatible are as follows:
nvidia,tegra20-i2c-dvc: Tegra20 has specific I2C controller called as DVC I2C
controller. This only support master mode of I2C communication. Register
interface/offset and interrupts handling are different than generic I2C
controller. Driver of DVC I2C controller is only compatible with
"nvidia,tegra20-i2c-dvc".
nvidia,tegra20-i2c: Tegra20 has 4 generic I2C controller. This can support
master and slave mode of I2C communication. The i2c-tegra driver only
support master mode of I2C communication. Driver of I2C controller is
only compatible with "nvidia,tegra20-i2c".
nvidia,tegra30-i2c: Tegra30 has 5 generic I2C controller. This controller is
very much similar to Tegra20 I2C controller with additional feature:
Continue Transfer Support. This feature helps to implement M_NO_START
as per I2C core API transfer flags. Driver of I2C controller is
compatible with "nvidia,tegra30-i2c" to enable the continue transfer
support. This is also compatible with "nvidia,tegra20-i2c" without
continue transfer support.
nvidia,tegra114-i2c: Tegra114 has 5 generic I2C controller. This controller is
very much similar to Tegra30 I2C controller with some hardware
modification:
- Tegra30/Tegra20 I2C controller has 2 clock source called div-clk and
fast-clk. Tegra114 has only one clock source called as div-clk and
hence clock mechanism is changed in I2C controller.
- Tegra30/Tegra20 I2C controller has enabled per packet transfer by
default and there is no way to disable it. Tegra114 has this
interrupt disable by default and SW need to enable explicitly.
Due to above changes, Tegra114 I2C driver makes incompatible with
previous hardware driver. Hence, tegra114 I2C controller is compatible
with "nvidia,tegra114-i2c".
- reg: Should contain I2C controller registers physical address and length.
- interrupts: Should contain I2C controller interrupts.
- address-cells: Address cells for I2C device address.
- size-cells: Size of the I2C device address.
- clocks: Clock ID as per
Documentation/devicetree/bindings/clock/tegra<chip-id>.txt
for I2C controller.
- clock-names: Name of the clock:
Tegra20/Tegra30 I2C controller: "div-clk and "fast-clk".
Tegra114 I2C controller: "div-clk".
Example:
i2c@7000c000 {
compatible = "nvidia,tegra20-i2c";
reg = <0x7000c000 0x100>;
interrupts = <0 38 0x04>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car 12>, <&tegra_car 124>;
clock-names = "div-clk", "fast-clk";
status = "disabled";
};

8
Documentation/devicetree/bindings/sound/nvidia,tegra-audio-alc5632.txt
View file

@ -2,6 +2,11 @@ NVIDIA Tegra audio complex
Required properties:
- compatible : "nvidia,tegra-audio-alc5632"
- clocks : Must contain an entry for each entry in clock-names.
- clock-names : Must include the following entries:
"pll_a" (The Tegra clock of that name),
"pll_a_out0" (The Tegra clock of that name),
"mclk" (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
- nvidia,model : The user-visible name of this sound complex.
- nvidia,audio-routing : A list of the connections between audio components.
Each entry is a pair of strings, the first being the connection's sink,
@ -56,4 +61,7 @@ sound {
nvidia,i2s-controller = <&tegra_i2s1>;
nvidia,audio-codec = <&alc5632>;
clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 93>;
clock-names = "pll_a", "pll_a_out0", "mclk";
};

7
Documentation/devicetree/bindings/sound/nvidia,tegra-audio-trimslice.txt
View file

@ -2,6 +2,11 @@ NVIDIA Tegra audio complex for TrimSlice
Required properties:
- compatible : "nvidia,tegra-audio-trimslice"
- clocks : Must contain an entry for each entry in clock-names.
- clock-names : Must include the following entries:
"pll_a" (The Tegra clock of that name),
"pll_a_out0" (The Tegra clock of that name),
"mclk" (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
- nvidia,i2s-controller : The phandle of the Tegra I2S1 controller
- nvidia,audio-codec : The phandle of the WM8903 audio codec
@ -11,4 +16,6 @@ sound {
compatible = "nvidia,tegra-audio-trimslice";
nvidia,i2s-controller = <&tegra_i2s1>;
nvidia,audio-codec = <&codec>;
clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 93>;
clock-names = "pll_a", "pll_a_out0", "mclk";
};

8
Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm8753.txt
View file

@ -2,6 +2,11 @@ NVIDIA Tegra audio complex
Required properties:
- compatible : "nvidia,tegra-audio-wm8753"
- clocks : Must contain an entry for each entry in clock-names.
- clock-names : Must include the following entries:
"pll_a" (The Tegra clock of that name),
"pll_a_out0" (The Tegra clock of that name),
"mclk" (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
- nvidia,model : The user-visible name of this sound complex.
- nvidia,audio-routing : A list of the connections between audio components.
Each entry is a pair of strings, the first being the connection's sink,
@ -50,5 +55,8 @@ sound {
nvidia,i2s-controller = <&i2s1>;
nvidia,audio-codec = <&wm8753>;
clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 93>;
clock-names = "pll_a", "pll_a_out0", "mclk";
};

8
Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm8903.txt
View file

@ -2,6 +2,11 @@ NVIDIA Tegra audio complex
Required properties:
- compatible : "nvidia,tegra-audio-wm8903"
- clocks : Must contain an entry for each entry in clock-names.
- clock-names : Must include the following entries:
"pll_a" (The Tegra clock of that name),
"pll_a_out0" (The Tegra clock of that name),
"mclk" (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
- nvidia,model : The user-visible name of this sound complex.
- nvidia,audio-routing : A list of the connections between audio components.
Each entry is a pair of strings, the first being the connection's sink,
@ -67,5 +72,8 @@ sound {
nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
nvidia,int-mic-en-gpios = <&gpio 184 0>; /*gpio PX0 */
nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */
clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 93>;
clock-names = "pll_a", "pll_a_out0", "mclk";
};

8
Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm9712.txt
View file

@ -2,6 +2,11 @@ NVIDIA Tegra audio complex
Required properties:
- compatible : "nvidia,tegra-audio-wm9712"
- clocks : Must contain an entry for each entry in clock-names.
- clock-names : Must include the following entries:
"pll_a" (The Tegra clock of that name),
"pll_a_out0" (The Tegra clock of that name),
"mclk" (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
- nvidia,model : The user-visible name of this sound complex.
- nvidia,audio-routing : A list of the connections between audio components.
Each entry is a pair of strings, the first being the connection's sink,
@ -48,4 +53,7 @@ sound {
"Mic", "MIC1";
nvidia,ac97-controller = <&ac97>;
clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 93>;
clock-names = "pll_a", "pll_a_out0", "mclk";
};

891
arch/arm/boot/dts/tegra114-dalmore.dts
View file

@ -10,14 +10,835 @@
reg = <0x80000000 0x40000000>;
};
pinmux {
pinctrl-names = "default";
pinctrl-0 = <&state_default>;
state_default: pinmux {
clk1_out_pw4 {
nvidia,pins = "clk1_out_pw4";
nvidia,function = "extperiph1";
nvidia,pull = <0>;
nvidia,tristate = <0>;
nvidia,enable-input = <0>;
};
dap1_din_pn1 {
nvidia,pins = "dap1_din_pn1";
nvidia,function = "i2s0";
nvidia,pull = <0>;
nvidia,tristate = <1>;
nvidia,enable-input = <1>;
};
dap1_dout_pn2 {
nvidia,pins = "dap1_dout_pn2",
"dap1_fs_pn0",
"dap1_sclk_pn3";
nvidia,function = "i2s0";
nvidia,pull = <0>;
nvidia,tristate = <0>;
nvidia,enable-input = <1>;
};
dap2_din_pa4 {
nvidia,pins = "dap2_din_pa4";
nvidia,function = "i2s1";
nvidia,pull = <0>;
nvidia,tristate = <1>;
nvidia,enable-input = <1>;
};
dap2_dout_pa5 {
nvidia,pins = "dap2_dout_pa5",
"dap2_fs_pa2",
"dap2_sclk_pa3";
nvidia,function = "i2s1";
nvidia,pull = <0>;
nvidia,tristate = <0>;
nvidia,enable-input = <1>;
};
dap4_din_pp5 {
nvidia,pins = "dap4_din_pp5",
"dap4_dout_pp6",
"dap4_fs_pp4",
"dap4_sclk_pp7";
nvidia,function = "i2s3";
nvidia,pull = <0>;
nvidia,tristate = <0>;
nvidia,enable-input = <1>;
};
dvfs_pwm_px0 {
nvidia,pins = "dvfs_pwm_px0",
"dvfs_clk_px2";
nvidia,function = "cldvfs";
nvidia,pull = <0>;
nvidia,tristate = <0>;
nvidia,enable-input = <0>;
};
ulpi_clk_py0 {
nvidia,pins = "ulpi_clk_py0",
"ulpi_data0_po1",
"ulpi_data1_po2",
"ulpi_data2_po3",
"ulpi_data3_po4",
"ulpi_data4_po5",
"ulpi_data5_po6",
"ulpi_data6_po7",
"ulpi_data7_po0";
nvidia,function = "ulpi";
nvidia,pull = <0>;
nvidia,tristate = <0>;
nvidia,enable-input = <1>;
};
ulpi_dir_py1 {
nvidia,pins = "ulpi_dir_py1",
"ulpi_nxt_py2";
nvidia,function = "ulpi";
nvidia,pull = <0>;
nvidia,tristate = <1>;
nvidia,enable-input = <1>;
};
ulpi_stp_py3 {
nvidia,pins = "ulpi_stp_py3";
nvidia,function = "ulpi";
nvidia,pull = <0>;
nvidia,tristate = <0>;
nvidia,enable-input = <0>;
};
cam_i2c_scl_pbb1 {
nvidia,pins = "cam_i2c_scl_pbb1",
"cam_i2c_sda_pbb2";
nvidia,function = "i2c3";
nvidia,pull = <0>;
nvidia,tristate = <0>;
nvidia,enable-input = <1>;
nvidia,lock = <0>;
nvidia,open-drain = <0>;
};
cam_mclk_pcc0 {
nvidia,pins = "cam_mclk_pcc0",
"pbb0";
nvidia,function = "vi_alt3";
nvidia,pull = <0>;
nvidia,tristate = <0>;
nvidia,enable-input = <0>;
nvidia,lock = <0>;
};
gen2_i2c_scl_pt5 {
nvidia,pins = "gen2_i2c_scl_pt5",
"gen2_i2c_sda_pt6";
nvidia,function = "i2c2";
nvidia,pull = <0>;
nvidia,tristate = <0>;
nvidia,enable-input = <1>;
nvidia,lock = <0>;
nvidia,open-drain = <0>;
};
gmi_a16_pj7 {
nvidia,pins = "gmi_a16_pj7";
nvidia,function = "uartd";
nvidia,pull = <0>;
nvidia,tristate = <0>;
nvidia,enable-input = <0>;
};
gmi_a17_pb0 {
nvidia,pins = "gmi_a17_pb0",
"gmi_a18_pb1";
nvidia,function = "uartd";
nvidia,pull = <0>;
nvidia,tristate = <1>;
nvidia,enable-input = <1>;
};
gmi_a19_pk7 {
nvidia,pins = "gmi_a19_pk7";
nvidia,function = "uartd";
nvidia,pull = <0>;
nvidia,tristate = <0>;
nvidia,enable-input = <0>;
};
gmi_ad5_pg5 {
nvidia,pins = "gmi_ad5_pg5",
"gmi_cs6_n_pi3",
"gmi_wr_n_pi0";
nvidia,function = "spi4";
nvidia,pull = <0>;
nvidia,tristate = <0>;
nvidia,enable-input = <1>;
};
gmi_ad6_pg6 {
nvidia,pins = "gmi_ad6_pg6",
"gmi_ad7_pg7";
nvidia,function = "spi4";
nvidia,pull = <2>;
nvidia,tristate = <0>;
nvidia,enable-input = <1>;
};
gmi_ad12_ph4 {
nvidia,pins = "gmi_ad12_ph4";
nvidia,function = "rsvd4";
nvidia,pull = <0>;
nvidia,tristate = <0>;
nvidia,enable-input = <0>;
};
gmi_ad9_ph1 {
nvidia,pins = "gmi_ad9_ph1";
nvidia,function = "pwm1";
nvidia,pull = <0>;
nvidia,tristate = <0>;
nvidia,enable-input = <0>;
};
gmi_cs1_n_pj2 {
nvidia,pins = "gmi_cs1_n_pj2",
"gmi_oe_n_pi1";
nvidia,function = "soc";
nvidia,pull = <0>;
nvidia,tristate = <1>;
nvidia,enable-input = <1>;
};
clk2_out_pw5 {
nvidia,pins = "clk2_out_pw5";
nvidia,function = "extperiph2";
nvidia,pull = <0>;
nvidia,tristate = <0>;
nvidia,enable-input = <0>;
};
sdmmc1_clk_pz0 {
nvidia,pins = "sdmmc1_clk_pz0";
nvidia,function = "sdmmc1";
nvidia,pull = <0>;
nvidia,tristate = <0>;
nvidia,enable-input = <1>;
};
sdmmc1_cmd_pz1 {
nvidia,pins = "sdmmc1_cmd_pz1",
"sdmmc1_dat0_py7",
"sdmmc1_dat1_py6",
"sdmmc1_dat2_py5",
"sdmmc1_dat3_py4";
nvidia,function = "sdmmc1";
nvidia,pull = <2>;
nvidia,tristate = <0>;
nvidia,enable-input = <1>;
};
sdmmc1_wp_n_pv3 {
nvidia,pins = "sdmmc1_wp_n_pv3";
nvidia,function = "spi4";
nvidia,pull = <2>;
nvidia,tristate = <0>;
nvidia,enable-input = <0>;
};
sdmmc3_clk_pa6 {
nvidia,pins = "sdmmc3_clk_pa6";
nvidia,function = "sdmmc3";
nvidia,pull = <0>;
nvidia,tristate = <0>;
nvidia,enable-input = <1>;
};
sdmmc3_cmd_pa7 {
nvidia,pins = "sdmmc3_cmd_pa7",
"sdmmc3_dat0_pb7",
"sdmmc3_dat1_pb6",
"sdmmc3_dat2_pb5",
"sdmmc3_dat3_pb4",
"kb_col4_pq4",
"sdmmc3_clk_lb_out_pee4",
"sdmmc3_clk_lb_in_pee5";
nvidia,function = "sdmmc3";
nvidia,pull = <2>;
nvidia,tristate = <0>;
nvidia,enable-input = <1>;
};
sdmmc4_clk_pcc4 {
nvidia,pins = "sdmmc4_clk_pcc4";
nvidia,function = "sdmmc4";
nvidia,pull = <0>;
nvidia,tristate = <0>;
nvidia,enable-input = <1>;
};
sdmmc4_cmd_pt7 {
nvidia,pins = "sdmmc4_cmd_pt7",
"sdmmc4_dat0_paa0",
"sdmmc4_dat1_paa1",
"sdmmc4_dat2_paa2",
"sdmmc4_dat3_paa3",
"sdmmc4_dat4_paa4",
"sdmmc4_dat5_paa5",
"sdmmc4_dat6_paa6",
"sdmmc4_dat7_paa7";
nvidia,function = "sdmmc4";
nvidia,pull = <2>;
nvidia,tristate = <0>;
nvidia,enable-input = <1>;
};
clk_32k_out_pa0 {
nvidia,pins = "clk_32k_out_pa0";
nvidia,function = "blink";
nvidia,pull = <0>;
nvidia,tristate = <0>;
nvidia,enable-input = <0>;
};
kb_col0_pq0 {
nvidia,pins = "kb_col0_pq0",
"kb_col1_pq1",
"kb_col2_pq2",
"kb_row0_pr0",
"kb_row1_pr1",
"kb_row2_pr2";
nvidia,function = "kbc";
nvidia,pull = <2>;
nvidia,tristate = <0>;
nvidia,enable-input = <1>;
};
dap3_din_pp1 {
nvidia,pins = "dap3_din_pp1",
"dap3_sclk_pp3";
nvidia,function = "displayb";
nvidia,pull = <0>;
nvidia,tristate = <1>;
nvidia,enable-input = <0>;
};
pv0 {
nvidia,pins = "pv0";
nvidia,function = "rsvd4";
nvidia,pull = <0>;
nvidia,tristate = <1>;
nvidia,enable-input = <0>;
};
kb_row7_pr7 {
nvidia,pins = "kb_row7_pr7";
nvidia,function = "rsvd2";
nvidia,pull = <2>;
nvidia,tristate = <0>;
nvidia,enable-input = <1>;
};
kb_row10_ps2 {
nvidia,pins = "kb_row10_ps2";
nvidia,function = "uarta";
nvidia,pull = <0>;
nvidia,tristate = <1>;
nvidia,enable-input = <1>;
};
kb_row9_ps1 {
nvidia,pins = "kb_row9_ps1";
nvidia,function = "uarta";
nvidia,pull = <0>;
nvidia,tristate = <0>;
nvidia,enable-input = <0>;
};
pwr_i2c_scl_pz6 {
nvidia,pins = "pwr_i2c_scl_pz6",
"pwr_i2c_sda_pz7";
nvidia,function = "i2cpwr";
nvidia,pull = <0>;
nvidia,tristate = <0>;
nvidia,enable-input = <1>;
nvidia,lock = <0>;
nvidia,open-drain = <0>;
};
sys_clk_req_pz5 {
nvidia,pins = "sys_clk_req_pz5";
nvidia,function = "sysclk";
nvidia,pull = <0>;
nvidia,tristate = <0>;
nvidia,enable-input = <0>;
};
core_pwr_req {
nvidia,pins = "core_pwr_req";
nvidia,function = "pwron";
nvidia,pull = <0>;
nvidia,tristate = <0>;
nvidia,enable-input = <0>;
};
cpu_pwr_req {
nvidia,pins = "cpu_pwr_req";
nvidia,function = "cpu";
nvidia,pull = <0>;
nvidia,tristate = <0>;
nvidia,enable-input = <0>;
};
pwr_int_n {
nvidia,pins = "pwr_int_n";
nvidia,function = "pmi";
nvidia,pull = <0>;
nvidia,tristate = <1>;
nvidia,enable-input = <1>;
};
reset_out_n {
nvidia,pins = "reset_out_n";
nvidia,function = "reset_out_n";
nvidia,pull = <0>;
nvidia,tristate = <0>;
nvidia,enable-input = <0>;
};
clk3_out_pee0 {
nvidia,pins = "clk3_out_pee0";
nvidia,function = "extperiph3";
nvidia,pull = <0>;
nvidia,tristate = <0>;
nvidia,enable-input = <0>;
};
gen1_i2c_scl_pc4 {
nvidia,pins = "gen1_i2c_scl_pc4",
"gen1_i2c_sda_pc5";
nvidia,function = "i2c1";
nvidia,pull = <0>;
nvidia,tristate = <0>;
nvidia,enable-input = <1>;
nvidia,lock = <0>;
nvidia,open-drain = <0>;
};
uart2_cts_n_pj5 {
nvidia,pins = "uart2_cts_n_pj5";
nvidia,function = "uartb";
nvidia,pull = <0>;
nvidia,tristate = <1>;
nvidia,enable-input = <1>;
};
uart2_rts_n_pj6 {
nvidia,pins = "uart2_rts_n_pj6";
nvidia,function = "uartb";
nvidia,pull = <0>;
nvidia,tristate = <0>;
nvidia,enable-input = <0>;
};
uart2_rxd_pc3 {
nvidia,pins = "uart2_rxd_pc3";
nvidia,function = "irda";
nvidia,pull = <0>;
nvidia,tristate = <1>;
nvidia,enable-input = <1>;
};
uart2_txd_pc2 {
nvidia,pins = "uart2_txd_pc2";
nvidia,function = "irda";
nvidia,pull = <0>;
nvidia,tristate = <0>;
nvidia,enable-input = <0>;
};
uart3_cts_n_pa1 {
nvidia,pins = "uart3_cts_n_pa1",
"uart3_rxd_pw7";
nvidia,function = "uartc";
nvidia,pull = <0>;
nvidia,tristate = <1>;
nvidia,enable-input = <1>;
};
uart3_rts_n_pc0 {
nvidia,pins = "uart3_rts_n_pc0",
"uart3_txd_pw6";
nvidia,function = "uartc";
nvidia,pull = <0>;
nvidia,tristate = <0>;
nvidia,enable-input = <0>;
};
owr {
nvidia,pins = "owr";
nvidia,function = "owr";
nvidia,pull = <0>;
nvidia,tristate = <0>;
nvidia,enable-input = <1>;
};
hdmi_cec_pee3 {
nvidia,pins = "hdmi_cec_pee3";
nvidia,function = "cec";
nvidia,pull = <0>;
nvidia,tristate = <0>;
nvidia,enable-input = <1>;
nvidia,lock = <0>;
nvidia,open-drain = <0>;
};
ddc_scl_pv4 {
nvidia,pins = "ddc_scl_pv4",
"ddc_sda_pv5";
nvidia,function = "i2c4";
nvidia,pull = <0>;
nvidia,tristate = <0>;
nvidia,enable-input = <1>;
nvidia,lock = <0>;
nvidia,rcv-sel = <1>;
};
spdif_in_pk6 {
nvidia,pins = "spdif_in_pk6";
nvidia,function = "usb";
nvidia,pull = <2>;
nvidia,tristate = <0>;
nvidia,enable-input = <1>;
nvidia,lock = <0>;
};
usb_vbus_en0_pn4 {
nvidia,pins = "usb_vbus_en0_pn4";
nvidia,function = "usb";
nvidia,pull = <2>;
nvidia,tristate = <0>;
nvidia,enable-input = <1>;
nvidia,lock = <0>;
nvidia,open-drain = <1>;
};
gpio_x6_aud_px6 {
nvidia,pins = "gpio_x6_aud_px6";
nvidia,function = "spi6";
nvidia,pull = <2>;
nvidia,tristate = <1>;
nvidia,enable-input = <1>;
};
gpio_x4_aud_px4 {
nvidia,pins = "gpio_x4_aud_px4",
"gpio_x7_aud_px7";
nvidia,function = "rsvd1";
nvidia,pull = <1>;
nvidia,tristate = <0>;
nvidia,enable-input = <0>;
};
gpio_x5_aud_px5 {
nvidia,pins = "gpio_x5_aud_px5";
nvidia,function = "rsvd1";
nvidia,pull = <2>;
nvidia,tristate = <0>;
nvidia,enable-input = <1>;
};
gpio_w2_aud_pw2 {
nvidia,pins = "gpio_w2_aud_pw2";
nvidia,function = "rsvd2";
nvidia,pull = <2>;
nvidia,tristate = <0>;
nvidia,enable-input = <1>;
};
gpio_w3_aud_pw3 {
nvidia,pins = "gpio_w3_aud_pw3";
nvidia,function = "spi6";
nvidia,pull = <2>;
nvidia,tristate = <0>;
nvidia,enable-input = <1>;
};
gpio_x1_aud_px1 {
nvidia,pins = "gpio_x1_aud_px1";
nvidia,function = "rsvd4";
nvidia,pull = <1>;
nvidia,tristate = <0>;
nvidia,enable-input = <1>;
};
gpio_x3_aud_px3 {
nvidia,pins = "gpio_x3_aud_px3";
nvidia,function = "rsvd4";
nvidia,pull = <2>;
nvidia,tristate = <0>;
nvidia,enable-input = <1>;
};
dap3_fs_pp0 {
nvidia,pins = "dap3_fs_pp0";
nvidia,function = "i2s2";
nvidia,pull = <1>;
nvidia,tristate = <0>;
nvidia,enable-input = <0>;
};
dap3_dout_pp2 {
nvidia,pins = "dap3_dout_pp2";
nvidia,function = "i2s2";
nvidia,pull = <1>;
nvidia,tristate = <0>;
nvidia,enable-input = <0>;
};
pv1 {
nvidia,pins = "pv1";
nvidia,function = "rsvd1";
nvidia,pull = <0>;
nvidia,tristate = <0>;
nvidia,enable-input = <1>;
};
pbb3 {
nvidia,pins = "pbb3",
"pbb5",
"pbb6",
"pbb7";
nvidia,function = "rsvd4";
nvidia,pull = <1>;
nvidia,tristate = <0>;
nvidia,enable-input = <0>;
};
pcc1 {
nvidia,pins = "pcc1",
"pcc2";
nvidia,function = "rsvd4";
nvidia,pull = <1>;
nvidia,tristate = <0>;
nvidia,enable-input = <1>;
};
gmi_ad0_pg0 {
nvidia,pins = "gmi_ad0_pg0",
"gmi_ad1_pg1";
nvidia,function = "gmi";
nvidia,pull = <0>;
nvidia,tristate = <0>;
nvidia,enable-input = <0>;
};
gmi_ad10_ph2 {
nvidia,pins = "gmi_ad10_ph2",
"gmi_ad11_ph3",
"gmi_ad13_ph5",
"gmi_ad8_ph0",
"gmi_clk_pk1";
nvidia,function = "gmi";
nvidia,pull = <1>;
nvidia,tristate = <0>;
nvidia,enable-input = <0>;
};
gmi_ad2_pg2 {
nvidia,pins = "gmi_ad2_pg2",
"gmi_ad3_pg3";
nvidia,function = "gmi";
nvidia,pull = <0>;
nvidia,tristate = <0>;
nvidia,enable-input = <1>;
};
gmi_adv_n_pk0 {
nvidia,pins = "gmi_adv_n_pk0",
"gmi_cs0_n_pj0",
"gmi_cs2_n_pk3",
"gmi_cs4_n_pk2",
"gmi_cs7_n_pi6",
"gmi_dqs_p_pj3",
"gmi_iordy_pi5",
"gmi_wp_n_pc7";
nvidia,function = "gmi";
nvidia,pull = <2>;
nvidia,tristate = <0>;
nvidia,enable-input = <1>;
};
gmi_cs3_n_pk4 {
nvidia,pins = "gmi_cs3_n_pk4";
nvidia,function = "gmi";
nvidia,pull = <2>;
nvidia,tristate = <0>;
nvidia,enable-input = <0>;
};
clk2_req_pcc5 {
nvidia,pins = "clk2_req_pcc5";
nvidia,function = "rsvd4";
nvidia,pull = <0>;
nvidia,tristate = <0>;
nvidia,enable-input = <0>;
};
kb_col3_pq3 {
nvidia,pins = "kb_col3_pq3",
"kb_col6_pq6",
"kb_col7_pq7";
nvidia,function = "kbc";
nvidia,pull = <2>;
nvidia,tristate = <0>;
nvidia,enable-input = <0>;
};
kb_col5_pq5 {
nvidia,pins = "kb_col5_pq5";
nvidia,function = "kbc";
nvidia,pull = <2>;
nvidia,tristate = <0>;
nvidia,enable-input = <1>;
};
kb_row3_pr3 {
nvidia,pins = "kb_row3_pr3",
"kb_row4_pr4",
"kb_row6_pr6",
"kb_row8_ps0";
nvidia,function = "kbc";
nvidia,pull = <1>;
nvidia,tristate = <0>;
nvidia,enable-input = <1>;
};
clk3_req_pee1 {
nvidia,pins = "clk3_req_pee1";
nvidia,function = "rsvd4";
nvidia,pull = <0>;
nvidia,tristate = <0>;
nvidia,enable-input = <0>;
};
pu4 {
nvidia,pins = "pu4";
nvidia,function = "displayb";
nvidia,pull = <0>;
nvidia,tristate = <0>;
nvidia,enable-input = <0>;
};
pu5 {
nvidia,pins = "pu5",
"pu6";
nvidia,function = "displayb";
nvidia,pull = <0>;
nvidia,tristate = <0>;
nvidia,enable-input = <1>;
};
hdmi_int_pn7 {
nvidia,pins = "hdmi_int_pn7";
nvidia,function = "rsvd1";
nvidia,pull = <1>;
nvidia,tristate = <0>;
nvidia,enable-input = <1>;
};
clk1_req_pee2 {
nvidia,pins = "clk1_req_pee2",
"usb_vbus_en1_pn5";
nvidia,function = "rsvd4";
nvidia,pull = <1>;
nvidia,tristate = <1>;
nvidia,enable-input = <0>;
};
drive_sdio1 {
nvidia,pins = "drive_sdio1";
nvidia,high-speed-mode = <1>;
nvidia,schmitt = <0>;
nvidia,low-power-mode = <3>;
nvidia,pull-down-strength = <36>;
nvidia,pull-up-strength = <20>;
nvidia,slew-rate-rising = <2>;
nvidia,slew-rate-falling = <2>;
};
drive_sdio3 {
nvidia,pins = "drive_sdio3";
nvidia,high-speed-mode = <1>;
nvidia,schmitt = <0>;
nvidia,low-power-mode = <3>;
nvidia,pull-down-strength = <22>;
nvidia,pull-up-strength = <36>;
nvidia,slew-rate-rising = <0>;
nvidia,slew-rate-falling = <0>;
};
drive_gma {
nvidia,pins = "drive_gma";
nvidia,high-speed-mode = <1>;
nvidia,schmitt = <0>;
nvidia,low-power-mode = <3>;
nvidia,pull-down-strength = <2>;
nvidia,pull-up-strength = <1>;
nvidia,slew-rate-rising = <0>;
nvidia,slew-rate-falling = <0>;
nvidia,drive-type = <1>;
};
};
};
serial@70006300 {
status = "okay";
};
i2c@7000c000 {
status = "okay";
clock-frequency = <100000>;
battery: smart-battery {
compatible = "ti,bq20z45", "sbs,sbs-battery";
reg = <0xb>;
battery-name = "battery";
sbs,i2c-retry-count = <2>;
sbs,poll-retry-count = <100>;
};
};
i2c@7000d000 {
status = "okay";
clock-frequency = <400000>;
tps51632 {
compatible = "ti,tps51632";
reg = <0x43>;
regulator-name = "vdd-cpu";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1520000>;
regulator-boot-on;
regulator-always-on;
};
tps65090 {
compatible = "ti,tps65090";
reg = <0x48>;
interrupt-parent = <&gpio>;
interrupts = <72 0x04>; /* gpio PJ0 */
vsys1-supply = <&vdd_ac_bat_reg>;
vsys2-supply = <&vdd_ac_bat_reg>;
vsys3-supply = <&vdd_ac_bat_reg>;
infet1-supply = <&vdd_ac_bat_reg>;
infet2-supply = <&vdd_ac_bat_reg>;
infet3-supply = <&tps65090_dcdc2_reg>;
infet4-supply = <&tps65090_dcdc2_reg>;
infet5-supply = <&tps65090_dcdc2_reg>;
infet6-supply = <&tps65090_dcdc2_reg>;
infet7-supply = <&tps65090_dcdc2_reg>;
vsys-l1-supply = <&vdd_ac_bat_reg>;
vsys-l2-supply = <&vdd_ac_bat_reg>;
regulators {
tps65090_dcdc1_reg: dcdc1 {
regulator-name = "vdd-sys-5v0";
regulator-always-on;
regulator-boot-on;
};
tps65090_dcdc2_reg: dcdc2 {
regulator-name = "vdd-sys-3v3";
regulator-always-on;
regulator-boot-on;
};
dcdc3 {
regulator-name = "vdd-ao";
regulator-always-on;
regulator-boot-on;
};
fet1 {
regulator-name = "vdd-lcd-bl";
};
fet3 {
regulator-name = "vdd-modem-3v3";
};
fet4 {
regulator-name = "avdd-lcd";
};
fet5 {
regulator-name = "vdd-lvds";
};
fet6 {
regulator-name = "vdd-sd-slot";
regulator-always-on;
regulator-boot-on;
};
fet7 {
regulator-name = "vdd-com-3v3";
};
ldo1 {
regulator-name = "vdd-sby-5v0";
regulator-always-on;
regulator-boot-on;
};
ldo2 {
regulator-name = "vdd-sby-3v3";
regulator-always-on;
regulator-boot-on;
};
};
};
};
pmc {
nvidia,invert-interrupt;
};
sdhci@78000400 {
cd-gpios = <&gpio 170 1>; /* gpio PV2 */
bus-width = <4>;
status = "okay";
};
sdhci@78000600 {
bus-width = <8>;
status = "okay";
non-removable;
};
clocks {
compatible = "simple-bus";
#address-cells = <1>;
@ -30,4 +851,74 @@
clock-frequency = <32768>;
};
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
vdd_ac_bat_reg: regulator@0 {
compatible = "regulator-fixed";
reg = <0>;
regulator-name = "vdd_ac_bat";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
};
dvdd_ts_reg: regulator@1 {
compatible = "regulator-fixed";
reg = <1>;
regulator-name = "dvdd_ts";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
enable-active-high;
gpio = <&gpio 61 0>; /* GPIO PH5 */
};
lcd_bl_en_reg: regulator@2 {
compatible = "regulator-fixed";
reg = <2>;
regulator-name = "lcd_bl_en";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
gpio = <&gpio 58 0>; /* GPIO PH2 */
};
usb1_vbus_reg: regulator@3 {
compatible = "regulator-fixed";
reg = <3>;
regulator-name = "usb1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
gpio = <&gpio 108 0>; /* GPIO PN4 */
gpio-open-drain;
vin-supply = <&tps65090_dcdc1_reg>;
};
usb3_vbus_reg: regulator@4 {
compatible = "regulator-fixed";
reg = <4>;
regulator-name = "usb2_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
gpio = <&gpio 86 0>; /* GPIO PK6 */
gpio-open-drain;
vin-supply = <&tps65090_dcdc1_reg>;
};
vdd_hdmi_reg: regulator@5 {
compatible = "regulator-fixed";
reg = <5>;
regulator-name = "vdd_hdmi_5v0";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
gpio = <&gpio 81 0>; /* GPIO PK1 */
vin-supply = <&tps65090_dcdc1_reg>;
};
};
};

240
arch/arm/boot/dts/tegra114.dtsi
View file

@ -4,6 +4,13 @@
compatible = "nvidia,tegra114";
interrupt-parent = <&gic>;
aliases {
serial0 = &uarta;
serial1 = &uartb;
serial2 = &uartc;
serial3 = &uartd;
};
gic: interrupt-controller {
compatible = "arm,cortex-a15-gic";
#interrupt-cells = <3>;
@ -33,6 +40,44 @@
#clock-cells = <1>;
};
apbdma: dma {
compatible = "nvidia,tegra114-apbdma";
reg = <0x6000a000 0x1400>;
interrupts = <0 104 0x04
0 105 0x04
0 106 0x04
0 107 0x04
0 108 0x04
0 109 0x04
0 110 0x04
0 111 0x04
0 112 0x04
0 113 0x04
0 114 0x04
0 115 0x04
0 116 0x04
0 117 0x04
0 118 0x04
0 119 0x04
0 128 0x04
0 129 0x04
0 130 0x04
0 131 0x04
0 132 0x04
0 133 0x04
0 134 0x04
0 135 0x04
0 136 0x04
0 137 0x04
0 138 0x04
0 139 0x04
0 140 0x04
0 141 0x04
0 142 0x04
0 143 0x04>;
clocks = <&tegra_car 34>;
};
ahb: ahb {
compatible = "nvidia,tegra114-ahb", "nvidia,tegra30-ahb";
reg = <0x6000c004 0x14c>;
@ -61,42 +106,189 @@
0x70003000 0x40c>; /* Mux registers */
};
serial@70006000 {
/*
* There are two serial driver i.e. 8250 based simple serial
* driver and APB DMA based serial driver for higher baudrate
* and performace. To enable the 8250 based driver, the compatible
* is "nvidia,tegra114-uart", "nvidia,tegra20-uart" and to enable
* the APB DMA based serial driver, the comptible is
* "nvidia,tegra114-hsuart", "nvidia,tegra30-hsuart".
*/
uarta: serial@70006000 {
compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
reg = <0x70006000 0x40>;
reg-shift = <2>;
interrupts = <0 36 0x04>;
nvidia,dma-request-selector = <&apbdma 8>;
status = "disabled";
clocks = <&tegra_car 6>;
};
serial@70006040 {
uartb: serial@70006040 {
compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
reg = <0x70006040 0x40>;
reg-shift = <2>;
interrupts = <0 37 0x04>;
nvidia,dma-request-selector = <&apbdma 9>;
status = "disabled";
clocks = <&tegra_car 192>;
};
serial@70006200 {
uartc: serial@70006200 {
compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
reg = <0x70006200 0x100>;
reg-shift = <2>;
interrupts = <0 46 0x04>;
nvidia,dma-request-selector = <&apbdma 10>;
status = "disabled";
clocks = <&tegra_car 55>;
};
serial@70006300 {
uartd: serial@70006300 {
compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
reg = <0x70006300 0x100>;
reg-shift = <2>;
interrupts = <0 90 0x04>;
nvidia,dma-request-selector = <&apbdma 19>;
status = "disabled";
clocks = <&tegra_car 65>;
};
pwm: pwm {
compatible = "nvidia,tegra114-pwm", "nvidia,tegra20-pwm";
reg = <0x7000a000 0x100>;
#pwm-cells = <2>;
clocks = <&tegra_car 17>;
status = "disabled";
};
i2c@7000c000 {
compatible = "nvidia,tegra114-i2c";
reg = <0x7000c000 0x100>;
interrupts = <0 38 0x04>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car 12>;
clock-names = "div-clk";
status = "disabled";
};
i2c@7000c400 {
compatible = "nvidia,tegra114-i2c";
reg = <0x7000c400 0x100>;
interrupts = <0 84 0x04>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car 54>;
clock-names = "div-clk";
status = "disabled";
};
i2c@7000c500 {
compatible = "nvidia,tegra114-i2c";
reg = <0x7000c500 0x100>;
interrupts = <0 92 0x04>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car 67>;
clock-names = "div-clk";
status = "disabled";
};
i2c@7000c700 {
compatible = "nvidia,tegra114-i2c";
reg = <0x7000c700 0x100>;
interrupts = <0 120 0x04>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car 103>;
clock-names = "div-clk";
status = "disabled";
};
i2c@7000d000 {
compatible = "nvidia,tegra114-i2c";
reg = <0x7000d000 0x100>;
interrupts = <0 53 0x04>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car 47>;
clock-names = "div-clk";
status = "disabled";
};
spi@7000d400 {
compatible = "nvidia,tegra114-spi";
reg = <0x7000d400 0x200>;
interrupts = <0 59 0x04>;
nvidia,dma-request-selector = <&apbdma 15>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car 41>;
clock-names = "spi";
status = "disabled";
};
spi@7000d600 {
compatible = "nvidia,tegra114-spi";
reg = <0x7000d600 0x200>;
interrupts = <0 82 0x04>;
nvidia,dma-request-selector = <&apbdma 16>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car 44>;
clock-names = "spi";
status = "disabled";
};
spi@7000d800 {
compatible = "nvidia,tegra114-spi";
reg = <0x7000d800 0x200>;
interrupts = <0 83 0x04>;
nvidia,dma-request-selector = <&apbdma 17>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car 46>;
clock-names = "spi";
status = "disabled";
};
spi@7000da00 {
compatible = "nvidia,tegra114-spi";
reg = <0x7000da00 0x200>;
interrupts = <0 93 0x04>;
nvidia,dma-request-selector = <&apbdma 18>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car 68>;
clock-names = "spi";
status = "disabled";
};
spi@7000dc00 {
compatible = "nvidia,tegra114-spi";
reg = <0x7000dc00 0x200>;
interrupts = <0 94 0x04>;
nvidia,dma-request-selector = <&apbdma 27>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car 104>;
clock-names = "spi";
status = "disabled";
};
spi@7000de00 {
compatible = "nvidia,tegra114-spi";
reg = <0x7000de00 0x200>;
interrupts = <0 79 0x04>;
nvidia,dma-request-selector = <&apbdma 28>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car 105>;
clock-names = "spi";
status = "disabled";
};
rtc {
compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc";
reg = <0x7000e000 0x100>;
@ -104,6 +296,14 @@
clocks = <&tegra_car 4>;
};
kbc {
compatible = "nvidia,tegra114-kbc";
reg = <0x7000e200 0x100>;
interrupts = <0 85 0x04>;
clocks = <&tegra_car 36>;
status = "disabled";
};
pmc {
compatible = "nvidia,tegra114-pmc";
reg = <0x7000e400 0x400>;
@ -122,6 +322,38 @@
nvidia,ahb = <&ahb>;
};
sdhci@78000000 {
compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
reg = <0x78000000 0x200>;
interrupts = <0 14 0x04>;
clocks = <&tegra_car 14>;
status = "disable";
};
sdhci@78000200 {
compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
reg = <0x78000200 0x200>;
interrupts = <0 15 0x04>;
clocks = <&tegra_car 9>;
status = "disable";
};
sdhci@78000400 {
compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
reg = <0x78000400 0x200>;
interrupts = <0 19 0x04>;
clocks = <&tegra_car 69>;
status = "disable";
};
sdhci@78000600 {
compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
reg = <0x78000600 0x200>;
interrupts = <0 31 0x04>;
clocks = <&tegra_car 15>;
status = "disable";
};
cpus {
#address-cells = <1>;
#size-cells = <0>;

12
arch/arm/boot/dts/tegra20-colibri-512.dtsi
View file

@ -361,6 +361,15 @@
};
};
pmc {
nvidia,suspend-mode = <2>;
nvidia,cpu-pwr-good-time = <5000>;
nvidia,cpu-pwr-off-time = <5000>;
nvidia,core-pwr-good-time = <3845 3845>;
nvidia,core-pwr-off-time = <3875>;
nvidia,sys-clock-req-active-high;
};
memory-controller@7000f400 {
emc-table@83250 {
reg = <83250>;
@ -473,6 +482,9 @@
"Mic", "MIC1";
nvidia,ac97-controller = <&ac97>;
clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>;
clock-names = "pll_a", "pll_a_out0", "mclk";
};
regulators {

20
arch/arm/boot/dts/tegra20-harmony.dts
View file

@ -416,6 +416,12 @@
pmc {
nvidia,invert-interrupt;
nvidia,suspend-mode = <2>;
nvidia,cpu-pwr-good-time = <5000>;
nvidia,cpu-pwr-off-time = <5000>;
nvidia,core-pwr-good-time = <3845 3845>;
nvidia,core-pwr-off-time = <3875>;
nvidia,sys-clock-req-active-high;
};
usb@c5000000 {
@ -464,6 +470,17 @@
};
};
gpio-keys {
compatible = "gpio-keys";
power {
label = "Power";
gpios = <&gpio 170 1>; /* gpio PV2, active low */
linux,code = <116>; /* KEY_POWER */
gpio-key,wakeup;
};
};
kbc {
status = "okay";
nvidia,debounce-delay-ms = <2>;
@ -669,5 +686,8 @@
nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
nvidia,int-mic-en-gpios = <&gpio 184 0>; /*gpio PX0 */
nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */
clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>;
clock-names = "pll_a", "pll_a_out0", "mclk";
};
};

7
arch/arm/boot/dts/tegra20-medcom-wide.dts
View file

@ -6,6 +6,10 @@
model = "Avionic Design Medcom-Wide board";
compatible = "ad,medcom-wide", "ad,tamonten", "nvidia,tegra20";
pwm {
status = "okay";
};
i2c@7000c000 {
wm8903: wm8903@1a {
compatible = "wlf,wm8903";
@ -54,5 +58,8 @@
nvidia,spkr-en-gpios = <&wm8903 2 0>;
nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>;
clock-names = "pll_a", "pll_a_out0", "mclk";
};
};

10
arch/arm/boot/dts/tegra20-paz00.dts
View file

@ -415,6 +415,12 @@
pmc {
nvidia,invert-interrupt;
nvidia,suspend-mode = <2>;
nvidia,cpu-pwr-good-time = <2000>;
nvidia,cpu-pwr-off-time = <0>;
nvidia,core-pwr-good-time = <3845 3845>;
nvidia,core-pwr-off-time = <0>;
nvidia,sys-clock-req-active-high;
};
usb@c5000000 {
@ -445,6 +451,7 @@
sdhci@c8000600 {
status = "okay";
bus-width = <8>;
non-removable;
};
clocks {
@ -514,5 +521,8 @@
nvidia,audio-codec = <&alc5632>;
nvidia,i2s-controller = <&tegra_i2s1>;
nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>;
clock-names = "pll_a", "pll_a_out0", "mclk";
};
};

3
arch/arm/boot/dts/tegra20-plutux.dts
View file

@ -52,5 +52,8 @@
nvidia,spkr-en-gpios = <&wm8903 2 0>;
nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>;
clock-names = "pll_a", "pll_a_out0", "mclk";
};
};

11
arch/arm/boot/dts/tegra20-seaboard.dts
View file

@ -517,6 +517,12 @@
pmc {
nvidia,invert-interrupt;
nvidia,suspend-mode = <2>;
nvidia,cpu-pwr-good-time = <5000>;
nvidia,cpu-pwr-off-time = <5000>;
nvidia,core-pwr-good-time = <3845 3845>;
nvidia,core-pwr-off-time = <3875>;
nvidia,sys-clock-req-active-high;
};
memory-controller@7000f400 {
@ -580,6 +586,7 @@
status = "okay";
power-gpios = <&gpio 86 0>; /* gpio PK6 */
bus-width = <4>;
keep-power-in-suspend;
};
sdhci@c8000400 {
@ -593,6 +600,7 @@
sdhci@c8000600 {
status = "okay";
bus-width = <8>;
non-removable;
};
clocks {
@ -821,5 +829,8 @@
nvidia,spkr-en-gpios = <&wm8903 2 0>;
nvidia,hp-det-gpios = <&gpio 185 0>; /* gpio PX1 */
clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>;
clock-names = "pll_a", "pll_a_out0", "mclk";
};
};

6
arch/arm/boot/dts/tegra20-tamonten.dtsi
View file

@ -458,6 +458,12 @@
pmc {
nvidia,invert-interrupt;
nvidia,suspend-mode = <2>;
nvidia,cpu-pwr-good-time = <5000>;
nvidia,cpu-pwr-off-time = <5000>;
nvidia,core-pwr-good-time = <3845 3845>;
nvidia,core-pwr-off-time = <3875>;
nvidia,sys-clock-req-active-high;
};
usb@c5008000 {

3
arch/arm/boot/dts/tegra20-tec.dts
View file

@ -52,5 +52,8 @@
nvidia,spkr-en-gpios = <&wm8903 2 0>;
nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>;
clock-names = "pll_a", "pll_a_out0", "mclk";
};
};

23
arch/arm/boot/dts/tegra20-trimslice.dts
View file

@ -300,6 +300,15 @@
};
};
pmc {
nvidia,suspend-mode = <2>;
nvidia,cpu-pwr-good-time = <5000>;
nvidia,cpu-pwr-off-time = <5000>;
nvidia,core-pwr-good-time = <3845 3845>;
nvidia,core-pwr-off-time = <3875>;
nvidia,sys-clock-req-active-high;
};
usb@c5000000 {
status = "okay";
nvidia,vbus-gpio = <&gpio 170 0>; /* gpio PV2 */
@ -343,6 +352,17 @@
};
};
gpio-keys {
compatible = "gpio-keys";
power {
label = "Power";
gpios = <&gpio 190 1>; /* gpio PX6, active low */
linux,code = <116>; /* KEY_POWER */
gpio-key,wakeup;
};
};
poweroff {
compatible = "gpio-poweroff";
gpios = <&gpio 191 1>; /* gpio PX7, active low */
@ -376,5 +396,8 @@
compatible = "nvidia,tegra-audio-trimslice";
nvidia,i2s-controller = <&tegra_i2s1>;
nvidia,audio-codec = <&codec>;
clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>;
clock-names = "pll_a", "pll_a_out0", "mclk";
};
};

22
arch/arm/boot/dts/tegra20-ventana.dts
View file

@ -493,6 +493,12 @@
pmc {
nvidia,invert-interrupt;
nvidia,suspend-mode = <2>;
nvidia,cpu-pwr-good-time = <2000>;
nvidia,cpu-pwr-off-time = <100>;
nvidia,core-pwr-good-time = <3845 3845>;
nvidia,core-pwr-off-time = <458>;
nvidia,sys-clock-req-active-high;
};
usb@c5000000 {
@ -516,6 +522,7 @@
status = "okay";
power-gpios = <&gpio 86 0>; /* gpio PK6 */
bus-width = <4>;
keep-power-in-suspend;
};
sdhci@c8000400 {
@ -529,6 +536,7 @@
sdhci@c8000600 {
status = "okay";
bus-width = <8>;
non-removable;
};
clocks {
@ -544,6 +552,17 @@
};
};
gpio-keys {
compatible = "gpio-keys";
power {
label = "Power";
gpios = <&gpio 170 1>; /* gpio PV2, active low */
linux,code = <116>; /* KEY_POWER */
gpio-key,wakeup;
};
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
@ -620,5 +639,8 @@
nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
nvidia,int-mic-en-gpios = <&gpio 184 0>; /* gpio PX0 */
nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */
clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>;
clock-names = "pll_a", "pll_a_out0", "mclk";
};
};

13
arch/arm/boot/dts/tegra20-whistler.dts
View file

@ -496,6 +496,14 @@
pmc {
nvidia,invert-interrupt;
nvidia,suspend-mode = <2>;
nvidia,cpu-pwr-good-time = <2000>;
nvidia,cpu-pwr-off-time = <1000>;
nvidia,core-pwr-good-time = <0 3845>;
nvidia,core-pwr-off-time = <93727>;
nvidia,core-power-req-active-high;
nvidia,sys-clock-req-active-high;
nvidia,combined-power-req;
};
usb@c5000000 {
@ -518,6 +526,7 @@
sdhci@c8000600 {
status = "okay";
bus-width = <8>;
non-removable;
};
clocks {
@ -539,6 +548,7 @@
nvidia,repeat-delay-ms = <160>;
nvidia,kbc-row-pins = <0 1 2>;
nvidia,kbc-col-pins = <16 17>;
nvidia,wakeup-source;
linux,keymap = <0x00000074 /* KEY_POWER */
0x01000066 /* KEY_HOME */
0x0101009E /* KEY_BACK */
@ -573,5 +583,8 @@
nvidia,i2s-controller = <&tegra_i2s1>;
nvidia,audio-codec = <&codec>;
clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>;
clock-names = "pll_a", "pll_a_out0", "mclk";
};
};

53
arch/arm/boot/dts/tegra20.dtsi
View file

@ -209,7 +209,7 @@
compatible = "nvidia,tegra20-das";
reg = <0x70000c00 0x80>;
};
tegra_ac97: ac97 {
compatible = "nvidia,tegra20-ac97";
reg = <0x70002000 0x200>;
@ -299,6 +299,7 @@
reg = <0x7000a000 0x100>;
#pwm-cells = <2>;
clocks = <&tegra_car 17>;
status = "disabled";
};
rtc {
@ -442,31 +443,6 @@
#size-cells = <0>;
};
phy1: usb-phy@c5000400 {
compatible = "nvidia,tegra20-usb-phy";
reg = <0xc5000400 0x3c00>;
phy_type = "utmi";
nvidia,has-legacy-mode;
clocks = <&tegra_car 22>, <&tegra_car 127>;
clock-names = "phy", "pll_u";
};
phy2: usb-phy@c5004400 {
compatible = "nvidia,tegra20-usb-phy";
reg = <0xc5004400 0x3c00>;
phy_type = "ulpi";
clocks = <&tegra_car 94>, <&tegra_car 127>;
clock-names = "phy", "pll_u";
};
phy3: usb-phy@c5008400 {
compatible = "nvidia,tegra20-usb-phy";
reg = <0xc5008400 0x3C00>;
phy_type = "utmi";
clocks = <&tegra_car 22>, <&tegra_car 127>;
clock-names = "phy", "pll_u";
};
usb@c5000000 {
compatible = "nvidia,tegra20-ehci", "usb-ehci";
reg = <0xc5000000 0x4000>;
@ -479,6 +455,15 @@
status = "disabled";
};
phy1: usb-phy@c5000400 {
compatible = "nvidia,tegra20-usb-phy";
reg = <0xc5000400 0x3c00>;
phy_type = "utmi";
nvidia,has-legacy-mode;
clocks = <&tegra_car 22>, <&tegra_car 127>;
clock-names = "phy", "pll_u";
};
usb@c5004000 {
compatible = "nvidia,tegra20-ehci", "usb-ehci";
reg = <0xc5004000 0x4000>;
@ -489,6 +474,14 @@
status = "disabled";
};
phy2: usb-phy@c5004400 {
compatible = "nvidia,tegra20-usb-phy";
reg = <0xc5004400 0x3c00>;
phy_type = "ulpi";
clocks = <&tegra_car 93>, <&tegra_car 127>;
clock-names = "phy", "pll_u";
};
usb@c5008000 {
compatible = "nvidia,tegra20-ehci", "usb-ehci";
reg = <0xc5008000 0x4000>;
@ -499,6 +492,14 @@
status = "disabled";
};
phy3: usb-phy@c5008400 {
compatible = "nvidia,tegra20-usb-phy";
reg = <0xc5008400 0x3c00>;
phy_type = "utmi";
clocks = <&tegra_car 22>, <&tegra_car 127>;
clock-names = "phy", "pll_u";
};
sdhci@c8000000 {
compatible = "nvidia,tegra20-sdhci";
reg = <0xc8000000 0x200>;

8
arch/arm/boot/dts/tegra30-beaver.dts
View file

@ -253,6 +253,13 @@
pmc {
status = "okay";
nvidia,invert-interrupt;
nvidia,suspend-mode = <2>;
nvidia,cpu-pwr-good-time = <2000>;
nvidia,cpu-pwr-off-time = <200>;
nvidia,core-pwr-good-time = <3845 3845>;
nvidia,core-pwr-off-time = <0>;
nvidia,core-power-req-active-high;
nvidia,sys-clock-req-active-high;
};
sdhci@78000000 {
@ -266,6 +273,7 @@
sdhci@78000600 {
status = "okay";
bus-width = <8>;
non-removable;
};
clocks {

1
arch/arm/boot/dts/tegra30-cardhu-a02.dts
View file

@ -88,6 +88,7 @@
status = "okay";
power-gpios = <&gpio 28 0>; /* gpio PD4 */
bus-width = <4>;
keep-power-in-suspend;
};
};

1
arch/arm/boot/dts/tegra30-cardhu-a04.dts
View file

@ -100,5 +100,6 @@
status = "okay";
power-gpios = <&gpio 27 0>; /* gpio PD3 */
bus-width = <4>;
keep-power-in-suspend;
};
};

11
arch/arm/boot/dts/tegra30-cardhu.dtsi
View file

@ -307,6 +307,13 @@
pmc {
status = "okay";
nvidia,invert-interrupt;
nvidia,suspend-mode = <2>;
nvidia,cpu-pwr-good-time = <2000>;
nvidia,cpu-pwr-off-time = <200>;
nvidia,core-pwr-good-time = <3845 3845>;
nvidia,core-pwr-off-time = <0>;
nvidia,core-power-req-active-high;
nvidia,sys-clock-req-active-high;
};
sdhci@78000000 {
@ -320,6 +327,7 @@
sdhci@78000600 {
status = "okay";
bus-width = <8>;
non-removable;
};
clocks {
@ -509,5 +517,8 @@
nvidia,spkr-en-gpios = <&wm8903 2 0>;
nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
clocks = <&tegra_car 184>, <&tegra_car 185>, <&tegra_car 120>;
clock-names = "pll_a", "pll_a_out0", "mclk";
};
};

1
arch/arm/boot/dts/tegra30.dtsi
View file

@ -286,6 +286,7 @@
reg = <0x7000a000 0x100>;
#pwm-cells = <2>;
clocks = <&tegra_car 17>;
status = "disabled";
};
rtc {