mv_xor: use {readl, writel}_relaxed instead of __raw_{readl, writel}
In order to support big-endian execution, the mv_xor driver is changed to use the readl_relaxed() and writel_relaxed() accessors that properly convert from the CPU endianess to the device endianess (which in the case of Marvell XOR hardware is always little-endian). Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Dan Williams <djbw@fb.com>
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1 changed files with 18 additions and 18 deletions
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@ -114,25 +114,25 @@ static void mv_desc_set_src_addr(struct mv_xor_desc_slot *desc,
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static u32 mv_chan_get_current_desc(struct mv_xor_chan *chan)
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{
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return __raw_readl(XOR_CURR_DESC(chan));
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return readl_relaxed(XOR_CURR_DESC(chan));
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}
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static void mv_chan_set_next_descriptor(struct mv_xor_chan *chan,
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u32 next_desc_addr)
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{
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__raw_writel(next_desc_addr, XOR_NEXT_DESC(chan));
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writel_relaxed(next_desc_addr, XOR_NEXT_DESC(chan));
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}
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static void mv_chan_unmask_interrupts(struct mv_xor_chan *chan)
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{
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u32 val = __raw_readl(XOR_INTR_MASK(chan));
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u32 val = readl_relaxed(XOR_INTR_MASK(chan));
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val |= XOR_INTR_MASK_VALUE << (chan->idx * 16);
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__raw_writel(val, XOR_INTR_MASK(chan));
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writel_relaxed(val, XOR_INTR_MASK(chan));
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}
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static u32 mv_chan_get_intr_cause(struct mv_xor_chan *chan)
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{
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u32 intr_cause = __raw_readl(XOR_INTR_CAUSE(chan));
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u32 intr_cause = readl_relaxed(XOR_INTR_CAUSE(chan));
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intr_cause = (intr_cause >> (chan->idx * 16)) & 0xFFFF;
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return intr_cause;
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}
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@ -149,13 +149,13 @@ static void mv_xor_device_clear_eoc_cause(struct mv_xor_chan *chan)
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{
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u32 val = ~(1 << (chan->idx * 16));
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dev_dbg(mv_chan_to_devp(chan), "%s, val 0x%08x\n", __func__, val);
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__raw_writel(val, XOR_INTR_CAUSE(chan));
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writel_relaxed(val, XOR_INTR_CAUSE(chan));
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}
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static void mv_xor_device_clear_err_status(struct mv_xor_chan *chan)
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{
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u32 val = 0xFFFF0000 >> (chan->idx * 16);
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__raw_writel(val, XOR_INTR_CAUSE(chan));
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writel_relaxed(val, XOR_INTR_CAUSE(chan));
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}
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static int mv_can_chain(struct mv_xor_desc_slot *desc)
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@ -173,7 +173,7 @@ static void mv_set_mode(struct mv_xor_chan *chan,
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enum dma_transaction_type type)
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{
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u32 op_mode;
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u32 config = __raw_readl(XOR_CONFIG(chan));
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u32 config = readl_relaxed(XOR_CONFIG(chan));
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switch (type) {
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case DMA_XOR:
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@ -192,7 +192,7 @@ static void mv_set_mode(struct mv_xor_chan *chan,
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config &= ~0x7;
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config |= op_mode;
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__raw_writel(config, XOR_CONFIG(chan));
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writel_relaxed(config, XOR_CONFIG(chan));
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chan->current_type = type;
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}
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@ -201,14 +201,14 @@ static void mv_chan_activate(struct mv_xor_chan *chan)
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u32 activation;
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dev_dbg(mv_chan_to_devp(chan), " activate chan.\n");
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activation = __raw_readl(XOR_ACTIVATION(chan));
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activation = readl_relaxed(XOR_ACTIVATION(chan));
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activation |= 0x1;
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__raw_writel(activation, XOR_ACTIVATION(chan));
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writel_relaxed(activation, XOR_ACTIVATION(chan));
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}
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static char mv_chan_is_busy(struct mv_xor_chan *chan)
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{
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u32 state = __raw_readl(XOR_ACTIVATION(chan));
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u32 state = readl_relaxed(XOR_ACTIVATION(chan));
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state = (state >> 4) & 0x3;
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@ -755,22 +755,22 @@ static void mv_dump_xor_regs(struct mv_xor_chan *chan)
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{
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u32 val;
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val = __raw_readl(XOR_CONFIG(chan));
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val = readl_relaxed(XOR_CONFIG(chan));
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dev_err(mv_chan_to_devp(chan), "config 0x%08x\n", val);
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val = __raw_readl(XOR_ACTIVATION(chan));
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val = readl_relaxed(XOR_ACTIVATION(chan));
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dev_err(mv_chan_to_devp(chan), "activation 0x%08x\n", val);
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val = __raw_readl(XOR_INTR_CAUSE(chan));
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val = readl_relaxed(XOR_INTR_CAUSE(chan));
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dev_err(mv_chan_to_devp(chan), "intr cause 0x%08x\n", val);
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val = __raw_readl(XOR_INTR_MASK(chan));
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val = readl_relaxed(XOR_INTR_MASK(chan));
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dev_err(mv_chan_to_devp(chan), "intr mask 0x%08x\n", val);
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val = __raw_readl(XOR_ERROR_CAUSE(chan));
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val = readl_relaxed(XOR_ERROR_CAUSE(chan));
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dev_err(mv_chan_to_devp(chan), "error cause 0x%08x\n", val);
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val = __raw_readl(XOR_ERROR_ADDR(chan));
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val = readl_relaxed(XOR_ERROR_ADDR(chan));
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dev_err(mv_chan_to_devp(chan), "error addr 0x%08x\n", val);
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}
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