ARM: OMAP: Timer32K: Re-organize duplicated 32k-timer code
On OMAP2/3, the gp-timer code can be used for a 32kHz timer simply by setting the source to be the 32k clock instead of sys_clk. This patch uses the mach-omap2/timer-gp.c code for 32kHz timer on OMAP2, moving the logic into mach-omap2/timer-gp.c, and not using plat-omap/timer32k.c which, for OMAP2, is redundant with the timer-gp code. Also, if CONFIG_OMAP_32K_TIMER is enabled, the gptimer-based clocksource is not used. Instead the default 32k sync counter is used as the clocksource (see the clocksource in plat-omap/common.c.) This is important for sleep/suspend so there is a valid counter during sleep. Note that the suspend/sleep code needs fixing to check for overflows of this counter. In addition, the OMAP2/3 details are removed from timer32k.c leaving that with only OMAP1 specifics. A follow-up patch will move it from plat-omap common code to mach-omap1. Signed-off-by: Kevin Hilman <khilman@mvista.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
This commit is contained in:
Kevin Hilman
Tony Lindgren
parent
225dfda1d6
commit
5a3a388fbe
4 changed files with 141 additions and 61 deletions
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@ -4,9 +4,7 @@
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# Common support
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obj-y := irq.o id.o io.o sram-fn.o memory.o prcm.o clock.o mux.o devices.o \
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serial.o gpmc.o
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obj-$(CONFIG_OMAP_MPU_TIMER) += timer-gp.o
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serial.o gpmc.o timer-gp.o
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# Power Management
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obj-$(CONFIG_PM) += pm.o pm-domain.o sleep.o
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@ -3,6 +3,11 @@
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*
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* OMAP2 GP timer support.
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*
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* Update to use new clocksource/clockevent layers
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* Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
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* Copyright (C) 2007 MontaVista Software, Inc.
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*
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* Original driver:
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* Copyright (C) 2005 Nokia Corporation
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* Author: Paul Mundt <paul.mundt@nokia.com>
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* Juha Yrjölä <juha.yrjola@nokia.com>
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@ -25,24 +30,23 @@
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/irq.h>
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#include <linux/clocksource.h>
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#include <linux/clockchips.h>
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#include <asm/mach/time.h>
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#include <asm/arch/dmtimer.h>
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static struct omap_dm_timer *gptimer;
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static inline void omap2_gp_timer_start(unsigned long load_val)
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{
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omap_dm_timer_set_load(gptimer, 1, 0xffffffff - load_val);
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omap_dm_timer_set_int_enable(gptimer, OMAP_TIMER_INT_OVERFLOW);
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omap_dm_timer_start(gptimer);
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}
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static struct clock_event_device clockevent_gpt;
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static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
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{
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omap_dm_timer_write_status(gptimer, OMAP_TIMER_INT_OVERFLOW);
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timer_tick();
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struct omap_dm_timer *gpt = (struct omap_dm_timer *)dev_id;
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struct clock_event_device *evt = &clockevent_gpt;
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omap_dm_timer_write_status(gpt, OMAP_TIMER_INT_OVERFLOW);
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evt->event_handler(evt);
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return IRQ_HANDLED;
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}
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@ -52,20 +56,138 @@ static struct irqaction omap2_gp_timer_irq = {
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.handler = omap2_gp_timer_interrupt,
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};
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static void __init omap2_gp_timer_init(void)
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static int omap2_gp_timer_set_next_event(unsigned long cycles,
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struct clock_event_device *evt)
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{
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u32 tick_period;
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omap_dm_timer_set_load(gptimer, 0, 0xffffffff - cycles);
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omap_dm_timer_start(gptimer);
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return 0;
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}
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static void omap2_gp_timer_set_mode(enum clock_event_mode mode,
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struct clock_event_device *evt)
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{
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u32 period;
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omap_dm_timer_stop(gptimer);
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switch (mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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period = clk_get_rate(omap_dm_timer_get_fclk(gptimer)) / HZ;
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period -= 1;
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omap_dm_timer_set_load(gptimer, 1, 0xffffffff - period);
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omap_dm_timer_start(gptimer);
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break;
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case CLOCK_EVT_MODE_ONESHOT:
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break;
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case CLOCK_EVT_MODE_UNUSED:
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case CLOCK_EVT_MODE_SHUTDOWN:
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case CLOCK_EVT_MODE_RESUME:
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break;
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}
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}
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static struct clock_event_device clockevent_gpt = {
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.name = "gp timer",
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.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
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.shift = 32,
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.set_next_event = omap2_gp_timer_set_next_event,
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.set_mode = omap2_gp_timer_set_mode,
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};
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static void __init omap2_gp_clockevent_init(void)
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{
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u32 tick_rate;
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omap_dm_timer_init();
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gptimer = omap_dm_timer_request_specific(1);
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BUG_ON(gptimer == NULL);
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#if defined(CONFIG_OMAP_32K_TIMER)
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omap_dm_timer_set_source(gptimer, OMAP_TIMER_SRC_32_KHZ);
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#else
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omap_dm_timer_set_source(gptimer, OMAP_TIMER_SRC_SYS_CLK);
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tick_period = clk_get_rate(omap_dm_timer_get_fclk(gptimer)) / HZ;
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tick_period -= 1;
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#endif
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tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer));
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omap2_gp_timer_irq.dev_id = (void *)gptimer;
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setup_irq(omap_dm_timer_get_irq(gptimer), &omap2_gp_timer_irq);
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omap2_gp_timer_start(tick_period);
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omap_dm_timer_set_int_enable(gptimer, OMAP_TIMER_INT_OVERFLOW);
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clockevent_gpt.mult = div_sc(tick_rate, NSEC_PER_SEC,
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clockevent_gpt.shift);
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clockevent_gpt.max_delta_ns =
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clockevent_delta2ns(0xffffffff, &clockevent_gpt);
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clockevent_gpt.min_delta_ns =
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clockevent_delta2ns(1, &clockevent_gpt);
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clockevent_gpt.cpumask = cpumask_of_cpu(0);
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clockevents_register_device(&clockevent_gpt);
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}
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#ifdef CONFIG_OMAP_32K_TIMER
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/*
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* When 32k-timer is enabled, don't use GPTimer for clocksource
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* instead, just leave default clocksource which uses the 32k
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* sync counter. See clocksource setup in see plat-omap/common.c.
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*/
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static inline void __init omap2_gp_clocksource_init(void) {}
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#else
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/*
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* clocksource
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*/
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static struct omap_dm_timer *gpt_clocksource;
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static cycle_t clocksource_read_cycles(void)
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{
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return (cycle_t)omap_dm_timer_read_counter(gpt_clocksource);
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}
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static struct clocksource clocksource_gpt = {
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.name = "gp timer",
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.rating = 300,
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.read = clocksource_read_cycles,
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.mask = CLOCKSOURCE_MASK(32),
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.shift = 24,
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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/* Setup free-running counter for clocksource */
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static void __init omap2_gp_clocksource_init(void)
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{
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static struct omap_dm_timer *gpt;
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u32 tick_rate, tick_period;
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static char err1[] __initdata = KERN_ERR
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"%s: failed to request dm-timer\n";
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static char err2[] __initdata = KERN_ERR
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"%s: can't register clocksource!\n";
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gpt = omap_dm_timer_request();
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if (!gpt)
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printk(err1, clocksource_gpt.name);
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gpt_clocksource = gpt;
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omap_dm_timer_set_source(gpt, OMAP_TIMER_SRC_SYS_CLK);
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tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gpt));
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tick_period = (tick_rate / HZ) - 1;
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omap_dm_timer_set_load(gpt, 1, 0);
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omap_dm_timer_start(gpt);
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clocksource_gpt.mult =
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clocksource_khz2mult(tick_rate/1000, clocksource_gpt.shift);
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if (clocksource_register(&clocksource_gpt))
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printk(err2, clocksource_gpt.name);
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}
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#endif
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static void __init omap2_gp_timer_init(void)
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{
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omap_dm_timer_init();
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omap2_gp_clockevent_init();
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omap2_gp_clocksource_init();
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}
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struct sys_timer omap_timer = {
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@ -9,7 +9,9 @@ obj-m :=
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obj-n :=
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obj- :=
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ifeq ($(CONFIG_ARCH_OMAP1),y)
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obj-$(CONFIG_OMAP_32K_TIMER) += timer32k.o
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endif
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# OCPI interconnect support for 1710, 1610 and 5912
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obj-$(CONFIG_ARCH_OMAP16XX) += ocpi.o
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@ -40,6 +40,7 @@
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#include <linux/interrupt.h>
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#include <linux/sched.h>
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#include <linux/spinlock.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <linux/clocksource.h>
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@ -93,8 +94,6 @@ struct sys_timer omap_timer;
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#define JIFFIES_TO_HW_TICKS(nr_jiffies, clock_rate) \
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(((nr_jiffies) * (clock_rate)) / HZ)
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#if defined(CONFIG_ARCH_OMAP1)
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static inline void omap_32k_timer_write(int val, int reg)
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{
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omap_writew(val, OMAP1_32K_TIMER_BASE + reg);
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@ -120,30 +119,6 @@ static inline void omap_32k_timer_stop(void)
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#define omap_32k_timer_ack_irq()
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#elif defined(CONFIG_ARCH_OMAP2)
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static struct omap_dm_timer *gptimer;
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static inline void omap_32k_timer_start(unsigned long load_val)
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{
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omap_dm_timer_set_load(gptimer, 1, 0xffffffff - load_val);
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omap_dm_timer_set_int_enable(gptimer, OMAP_TIMER_INT_OVERFLOW);
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omap_dm_timer_start(gptimer);
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}
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static inline void omap_32k_timer_stop(void)
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{
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omap_dm_timer_stop(gptimer);
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}
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static inline void omap_32k_timer_ack_irq(void)
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{
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u32 status = omap_dm_timer_read_status(gptimer);
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omap_dm_timer_write_status(gptimer, status);
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}
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#endif
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static void omap_32k_timer_set_mode(enum clock_event_mode mode,
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struct clock_event_device *evt)
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{
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@ -222,23 +197,6 @@ static struct irqaction omap_32k_timer_irq = {
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static __init void omap_init_32k_timer(void)
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{
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if (cpu_class_is_omap1())
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setup_irq(INT_OS_TIMER, &omap_32k_timer_irq);
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#ifdef CONFIG_ARCH_OMAP2
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/* REVISIT: Check 24xx TIOCP_CFG settings after idle works */
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if (cpu_is_omap24xx()) {
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gptimer = omap_dm_timer_request_specific(1);
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BUG_ON(gptimer == NULL);
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omap_dm_timer_set_source(gptimer, OMAP_TIMER_SRC_32_KHZ);
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setup_irq(omap_dm_timer_get_irq(gptimer), &omap_32k_timer_irq);
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omap_dm_timer_set_int_enable(gptimer,
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OMAP_TIMER_INT_CAPTURE | OMAP_TIMER_INT_OVERFLOW |
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OMAP_TIMER_INT_MATCH);
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}
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#endif
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clockevent_32k_timer.mult = div_sc(OMAP_32K_TICKS_PER_SEC,
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NSEC_PER_SEC,
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clockevent_32k_timer.shift);
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