spi: add support for SuperH SPI
The SH7757 has SPI0 module. This patch supports it.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
[grant.likely@secretlab.ca: fixed Makefile ordering, added
__dev{init,exit} annotations, removed DRIVER_VERSION (this is
mainline, the version == the kernel version) and tidied some
indentation & style stuff]
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
This commit is contained in:
Yoshihiro Shimoda
Grant Likely
parent
0ff56cd85a
commit
5c05dd0750
3 changed files with 550 additions and 0 deletions
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@ -343,6 +343,12 @@ config SPI_SH_MSIOF
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help
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SPI driver for SuperH MSIOF blocks.
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config SPI_SH
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tristate "SuperH SPI controller"
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depends on SUPERH
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help
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SPI driver for SuperH SPI blocks.
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config SPI_SH_SCI
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tristate "SuperH SCI SPI controller"
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depends on SUPERH
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@ -48,6 +48,7 @@ obj-$(CONFIG_SPI_TEGRA) += spi_tegra.o
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obj-$(CONFIG_SPI_TOPCLIFF_PCH) += spi_topcliff_pch.o
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obj-$(CONFIG_SPI_TXX9) += spi_txx9.o
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obj-$(CONFIG_SPI_XILINX) += xilinx_spi.o
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obj-$(CONFIG_SPI_SH) += spi_sh.o
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obj-$(CONFIG_SPI_SH_SCI) += spi_sh_sci.o
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obj-$(CONFIG_SPI_SH_MSIOF) += spi_sh_msiof.o
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obj-$(CONFIG_SPI_STMP3XXX) += spi_stmp.o
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543
drivers/spi/spi_sh.c
Normal file
543
drivers/spi/spi_sh.c
Normal file
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@ -0,0 +1,543 @@
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/*
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* SH SPI bus driver
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*
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* Copyright (C) 2011 Renesas Solutions Corp.
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*
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* Based on pxa2xx_spi.c:
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* Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/errno.h>
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#include <linux/timer.h>
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#include <linux/delay.h>
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#include <linux/list.h>
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#include <linux/workqueue.h>
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#include <linux/interrupt.h>
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#include <linux/platform_device.h>
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#include <linux/io.h>
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#include <linux/spi/spi.h>
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#define SPI_SH_TBR 0x00
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#define SPI_SH_RBR 0x00
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#define SPI_SH_CR1 0x08
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#define SPI_SH_CR2 0x10
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#define SPI_SH_CR3 0x18
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#define SPI_SH_CR4 0x20
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#define SPI_SH_CR5 0x28
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/* CR1 */
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#define SPI_SH_TBE 0x80
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#define SPI_SH_TBF 0x40
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#define SPI_SH_RBE 0x20
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#define SPI_SH_RBF 0x10
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#define SPI_SH_PFONRD 0x08
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#define SPI_SH_SSDB 0x04
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#define SPI_SH_SSD 0x02
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#define SPI_SH_SSA 0x01
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/* CR2 */
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#define SPI_SH_RSTF 0x80
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#define SPI_SH_LOOPBK 0x40
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#define SPI_SH_CPOL 0x20
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#define SPI_SH_CPHA 0x10
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#define SPI_SH_L1M0 0x08
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/* CR3 */
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#define SPI_SH_MAX_BYTE 0xFF
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/* CR4 */
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#define SPI_SH_TBEI 0x80
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#define SPI_SH_TBFI 0x40
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#define SPI_SH_RBEI 0x20
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#define SPI_SH_RBFI 0x10
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#define SPI_SH_WPABRT 0x04
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#define SPI_SH_SSS 0x01
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/* CR8 */
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#define SPI_SH_P1L0 0x80
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#define SPI_SH_PP1L0 0x40
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#define SPI_SH_MUXI 0x20
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#define SPI_SH_MUXIRQ 0x10
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#define SPI_SH_FIFO_SIZE 32
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#define SPI_SH_SEND_TIMEOUT (3 * HZ)
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#define SPI_SH_RECEIVE_TIMEOUT (HZ >> 3)
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#undef DEBUG
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struct spi_sh_data {
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void __iomem *addr;
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int irq;
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struct spi_master *master;
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struct list_head queue;
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struct workqueue_struct *workqueue;
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struct work_struct ws;
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unsigned long cr1;
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wait_queue_head_t wait;
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spinlock_t lock;
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};
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static void spi_sh_write(struct spi_sh_data *ss, unsigned long data,
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unsigned long offset)
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{
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writel(data, ss->addr + offset);
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}
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static unsigned long spi_sh_read(struct spi_sh_data *ss, unsigned long offset)
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{
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return readl(ss->addr + offset);
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}
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static void spi_sh_set_bit(struct spi_sh_data *ss, unsigned long val,
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unsigned long offset)
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{
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unsigned long tmp;
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tmp = spi_sh_read(ss, offset);
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tmp |= val;
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spi_sh_write(ss, tmp, offset);
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}
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static void spi_sh_clear_bit(struct spi_sh_data *ss, unsigned long val,
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unsigned long offset)
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{
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unsigned long tmp;
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tmp = spi_sh_read(ss, offset);
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tmp &= ~val;
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spi_sh_write(ss, tmp, offset);
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}
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static void clear_fifo(struct spi_sh_data *ss)
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{
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spi_sh_set_bit(ss, SPI_SH_RSTF, SPI_SH_CR2);
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spi_sh_clear_bit(ss, SPI_SH_RSTF, SPI_SH_CR2);
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}
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static int spi_sh_wait_receive_buffer(struct spi_sh_data *ss)
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{
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int timeout = 100000;
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while (spi_sh_read(ss, SPI_SH_CR1) & SPI_SH_RBE) {
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udelay(10);
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if (timeout-- < 0)
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return -ETIMEDOUT;
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}
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return 0;
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}
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static int spi_sh_wait_write_buffer_empty(struct spi_sh_data *ss)
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{
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int timeout = 100000;
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while (!(spi_sh_read(ss, SPI_SH_CR1) & SPI_SH_TBE)) {
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udelay(10);
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if (timeout-- < 0)
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return -ETIMEDOUT;
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}
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return 0;
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}
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static int spi_sh_send(struct spi_sh_data *ss, struct spi_message *mesg,
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struct spi_transfer *t)
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{
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int i, retval = 0;
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int remain = t->len;
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int cur_len;
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unsigned char *data;
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unsigned long tmp;
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long ret;
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if (t->len)
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spi_sh_set_bit(ss, SPI_SH_SSA, SPI_SH_CR1);
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data = (unsigned char *)t->tx_buf;
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while (remain > 0) {
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cur_len = min(SPI_SH_FIFO_SIZE, remain);
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for (i = 0; i < cur_len &&
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!(spi_sh_read(ss, SPI_SH_CR4) &
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SPI_SH_WPABRT) &&
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!(spi_sh_read(ss, SPI_SH_CR1) & SPI_SH_TBF);
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i++)
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spi_sh_write(ss, (unsigned long)data[i], SPI_SH_TBR);
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if (spi_sh_read(ss, SPI_SH_CR4) & SPI_SH_WPABRT) {
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/* Abort SPI operation */
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spi_sh_set_bit(ss, SPI_SH_WPABRT, SPI_SH_CR4);
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retval = -EIO;
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break;
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}
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cur_len = i;
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remain -= cur_len;
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data += cur_len;
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if (remain > 0) {
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ss->cr1 &= ~SPI_SH_TBE;
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spi_sh_set_bit(ss, SPI_SH_TBE, SPI_SH_CR4);
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ret = wait_event_interruptible_timeout(ss->wait,
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ss->cr1 & SPI_SH_TBE,
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SPI_SH_SEND_TIMEOUT);
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if (ret == 0 && !(ss->cr1 & SPI_SH_TBE)) {
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printk(KERN_ERR "%s: timeout\n", __func__);
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return -ETIMEDOUT;
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}
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}
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}
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if (list_is_last(&t->transfer_list, &mesg->transfers)) {
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tmp = spi_sh_read(ss, SPI_SH_CR1);
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tmp = tmp & ~(SPI_SH_SSD | SPI_SH_SSDB);
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spi_sh_write(ss, tmp, SPI_SH_CR1);
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spi_sh_set_bit(ss, SPI_SH_SSA, SPI_SH_CR1);
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ss->cr1 &= ~SPI_SH_TBE;
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spi_sh_set_bit(ss, SPI_SH_TBE, SPI_SH_CR4);
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ret = wait_event_interruptible_timeout(ss->wait,
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ss->cr1 & SPI_SH_TBE,
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SPI_SH_SEND_TIMEOUT);
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if (ret == 0 && (ss->cr1 & SPI_SH_TBE)) {
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printk(KERN_ERR "%s: timeout\n", __func__);
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return -ETIMEDOUT;
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}
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}
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return retval;
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}
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static int spi_sh_receive(struct spi_sh_data *ss, struct spi_message *mesg,
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struct spi_transfer *t)
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{
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int i;
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int remain = t->len;
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int cur_len;
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unsigned char *data;
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unsigned long tmp;
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long ret;
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if (t->len > SPI_SH_MAX_BYTE)
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spi_sh_write(ss, SPI_SH_MAX_BYTE, SPI_SH_CR3);
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else
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spi_sh_write(ss, t->len, SPI_SH_CR3);
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tmp = spi_sh_read(ss, SPI_SH_CR1);
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tmp = tmp & ~(SPI_SH_SSD | SPI_SH_SSDB);
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spi_sh_write(ss, tmp, SPI_SH_CR1);
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spi_sh_set_bit(ss, SPI_SH_SSA, SPI_SH_CR1);
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spi_sh_wait_write_buffer_empty(ss);
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data = (unsigned char *)t->rx_buf;
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while (remain > 0) {
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if (remain >= SPI_SH_FIFO_SIZE) {
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ss->cr1 &= ~SPI_SH_RBF;
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spi_sh_set_bit(ss, SPI_SH_RBF, SPI_SH_CR4);
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ret = wait_event_interruptible_timeout(ss->wait,
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ss->cr1 & SPI_SH_RBF,
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SPI_SH_RECEIVE_TIMEOUT);
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if (ret == 0 &&
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spi_sh_read(ss, SPI_SH_CR1) & SPI_SH_RBE) {
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printk(KERN_ERR "%s: timeout\n", __func__);
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return -ETIMEDOUT;
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}
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}
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cur_len = min(SPI_SH_FIFO_SIZE, remain);
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for (i = 0; i < cur_len; i++) {
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if (spi_sh_wait_receive_buffer(ss))
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break;
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data[i] = (unsigned char)spi_sh_read(ss, SPI_SH_RBR);
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}
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remain -= cur_len;
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data += cur_len;
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}
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/* deassert CS when SPI is receiving. */
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if (t->len > SPI_SH_MAX_BYTE) {
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clear_fifo(ss);
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spi_sh_write(ss, 1, SPI_SH_CR3);
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} else {
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spi_sh_write(ss, 0, SPI_SH_CR3);
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}
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return 0;
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}
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static void spi_sh_work(struct work_struct *work)
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{
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struct spi_sh_data *ss = container_of(work, struct spi_sh_data, ws);
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struct spi_message *mesg;
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struct spi_transfer *t;
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unsigned long flags;
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int ret;
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pr_debug("%s: enter\n", __func__);
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spin_lock_irqsave(&ss->lock, flags);
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while (!list_empty(&ss->queue)) {
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mesg = list_entry(ss->queue.next, struct spi_message, queue);
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list_del_init(&mesg->queue);
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spin_unlock_irqrestore(&ss->lock, flags);
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list_for_each_entry(t, &mesg->transfers, transfer_list) {
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pr_debug("tx_buf = %p, rx_buf = %p\n",
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t->tx_buf, t->rx_buf);
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pr_debug("len = %d, delay_usecs = %d\n",
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t->len, t->delay_usecs);
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if (t->tx_buf) {
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ret = spi_sh_send(ss, mesg, t);
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if (ret < 0)
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goto error;
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}
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if (t->rx_buf) {
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ret = spi_sh_receive(ss, mesg, t);
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if (ret < 0)
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goto error;
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}
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mesg->actual_length += t->len;
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}
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spin_lock_irqsave(&ss->lock, flags);
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mesg->status = 0;
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mesg->complete(mesg->context);
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}
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clear_fifo(ss);
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spi_sh_set_bit(ss, SPI_SH_SSD, SPI_SH_CR1);
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udelay(100);
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spi_sh_clear_bit(ss, SPI_SH_SSA | SPI_SH_SSDB | SPI_SH_SSD,
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SPI_SH_CR1);
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clear_fifo(ss);
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spin_unlock_irqrestore(&ss->lock, flags);
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return;
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error:
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mesg->status = ret;
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mesg->complete(mesg->context);
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spi_sh_clear_bit(ss, SPI_SH_SSA | SPI_SH_SSDB | SPI_SH_SSD,
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SPI_SH_CR1);
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clear_fifo(ss);
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}
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static int spi_sh_setup(struct spi_device *spi)
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{
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struct spi_sh_data *ss = spi_master_get_devdata(spi->master);
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if (!spi->bits_per_word)
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spi->bits_per_word = 8;
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pr_debug("%s: enter\n", __func__);
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spi_sh_write(ss, 0xfe, SPI_SH_CR1); /* SPI sycle stop */
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spi_sh_write(ss, 0x00, SPI_SH_CR1); /* CR1 init */
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spi_sh_write(ss, 0x00, SPI_SH_CR3); /* CR3 init */
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clear_fifo(ss);
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/* 1/8 clock */
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spi_sh_write(ss, spi_sh_read(ss, SPI_SH_CR2) | 0x07, SPI_SH_CR2);
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udelay(10);
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return 0;
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}
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static int spi_sh_transfer(struct spi_device *spi, struct spi_message *mesg)
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{
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struct spi_sh_data *ss = spi_master_get_devdata(spi->master);
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unsigned long flags;
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pr_debug("%s: enter\n", __func__);
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pr_debug("\tmode = %02x\n", spi->mode);
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spin_lock_irqsave(&ss->lock, flags);
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mesg->actual_length = 0;
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mesg->status = -EINPROGRESS;
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spi_sh_clear_bit(ss, SPI_SH_SSA, SPI_SH_CR1);
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list_add_tail(&mesg->queue, &ss->queue);
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queue_work(ss->workqueue, &ss->ws);
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spin_unlock_irqrestore(&ss->lock, flags);
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return 0;
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}
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static void spi_sh_cleanup(struct spi_device *spi)
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{
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struct spi_sh_data *ss = spi_master_get_devdata(spi->master);
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pr_debug("%s: enter\n", __func__);
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spi_sh_clear_bit(ss, SPI_SH_SSA | SPI_SH_SSDB | SPI_SH_SSD,
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SPI_SH_CR1);
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}
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static irqreturn_t spi_sh_irq(int irq, void *_ss)
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{
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struct spi_sh_data *ss = (struct spi_sh_data *)_ss;
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unsigned long cr1;
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cr1 = spi_sh_read(ss, SPI_SH_CR1);
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if (cr1 & SPI_SH_TBE)
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ss->cr1 |= SPI_SH_TBE;
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if (cr1 & SPI_SH_TBF)
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ss->cr1 |= SPI_SH_TBF;
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if (cr1 & SPI_SH_RBE)
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ss->cr1 |= SPI_SH_RBE;
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if (cr1 & SPI_SH_RBF)
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ss->cr1 |= SPI_SH_RBF;
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if (ss->cr1) {
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spi_sh_clear_bit(ss, ss->cr1, SPI_SH_CR4);
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wake_up(&ss->wait);
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}
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return IRQ_HANDLED;
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}
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static int __devexit spi_sh_remove(struct platform_device *pdev)
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{
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struct spi_sh_data *ss = dev_get_drvdata(&pdev->dev);
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destroy_workqueue(ss->workqueue);
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free_irq(ss->irq, ss);
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iounmap(ss->addr);
|
||||
spi_master_put(ss->master);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __devinit spi_sh_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct resource *res;
|
||||
struct spi_master *master;
|
||||
struct spi_sh_data *ss;
|
||||
int ret, irq;
|
||||
|
||||
/* get base addr */
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
if (unlikely(res == NULL)) {
|
||||
dev_err(&pdev->dev, "invalid resource\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
irq = platform_get_irq(pdev, 0);
|
||||
if (irq < 0) {
|
||||
dev_err(&pdev->dev, "platform_get_irq error\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
master = spi_alloc_master(&pdev->dev, sizeof(struct spi_sh_data));
|
||||
if (master == NULL) {
|
||||
dev_err(&pdev->dev, "spi_alloc_master error.\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
ss = spi_master_get_devdata(master);
|
||||
dev_set_drvdata(&pdev->dev, ss);
|
||||
|
||||
ss->irq = irq;
|
||||
ss->master = master;
|
||||
ss->addr = ioremap(res->start, resource_size(res));
|
||||
if (ss->addr == NULL) {
|
||||
dev_err(&pdev->dev, "ioremap error.\n");
|
||||
ret = -ENOMEM;
|
||||
goto error1;
|
||||
}
|
||||
INIT_LIST_HEAD(&ss->queue);
|
||||
spin_lock_init(&ss->lock);
|
||||
INIT_WORK(&ss->ws, spi_sh_work);
|
||||
init_waitqueue_head(&ss->wait);
|
||||
ss->workqueue = create_singlethread_workqueue(
|
||||
dev_name(master->dev.parent));
|
||||
if (ss->workqueue == NULL) {
|
||||
dev_err(&pdev->dev, "create workqueue error\n");
|
||||
ret = -EBUSY;
|
||||
goto error2;
|
||||
}
|
||||
|
||||
ret = request_irq(irq, spi_sh_irq, IRQF_DISABLED, "spi_sh", ss);
|
||||
if (ret < 0) {
|
||||
dev_err(&pdev->dev, "request_irq error\n");
|
||||
goto error3;
|
||||
}
|
||||
|
||||
master->num_chipselect = 2;
|
||||
master->bus_num = pdev->id;
|
||||
master->setup = spi_sh_setup;
|
||||
master->transfer = spi_sh_transfer;
|
||||
master->cleanup = spi_sh_cleanup;
|
||||
|
||||
ret = spi_register_master(master);
|
||||
if (ret < 0) {
|
||||
printk(KERN_ERR "spi_register_master error.\n");
|
||||
goto error4;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
error4:
|
||||
free_irq(irq, ss);
|
||||
error3:
|
||||
destroy_workqueue(ss->workqueue);
|
||||
error2:
|
||||
iounmap(ss->addr);
|
||||
error1:
|
||||
spi_master_put(master);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static struct platform_driver spi_sh_driver = {
|
||||
.probe = spi_sh_probe,
|
||||
.remove = __devexit_p(spi_sh_remove),
|
||||
.driver = {
|
||||
.name = "sh_spi",
|
||||
.owner = THIS_MODULE,
|
||||
},
|
||||
};
|
||||
|
||||
static int __init spi_sh_init(void)
|
||||
{
|
||||
return platform_driver_register(&spi_sh_driver);
|
||||
}
|
||||
module_init(spi_sh_init);
|
||||
|
||||
static void __exit spi_sh_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&spi_sh_driver);
|
||||
}
|
||||
module_exit(spi_sh_exit);
|
||||
|
||||
MODULE_DESCRIPTION("SH SPI bus driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
MODULE_AUTHOR("Yoshihiro Shimoda");
|
||||
MODULE_ALIAS("platform:sh_spi");
|
||||
Loading…
Reference in a new issue