drm/i915/bxt: add display initialize/uninitialize sequence (PHY)
Add PHY specific display initialization sequence as per BSpec. Note that the PHY initialization/uninitialization are done at their current place only for simplicity, in a future patch - when more of the runtime PM features will be enabled - these will be moved to power well#1 and modeset encoder enabling/disabling hooks respectively. The call to uninitialize the PHY during system/runtime suspend will be added later in this patchset. v1: Added function definitions in header files v2: Imre's review comments addressed - Moved CDCLK related definitions to i915_reg.h - Removed defintions for CDCLK frequency - Split uninit_cdclk() by adding a phy_uninit function - Calculate freq and decimal based on input frequency - Program SSA precharge based on input frequency - Use wait_for 1ms instead 200us udelay for DE PLL locking - Removed initial value for divider, freq, decimal, ratio. - Replaced polling loops with wait_for - Parameterized latency optim setting - Fix the parts where DE PLL has to be disabled. - Call CDCLK selection from mode set v3: (imre) - add note about the plan to move the cdclk/phy init to a better place - take rps.hw_lock around pcode access - fix DDI PHY timeout value - squash in Vandana's "PORT_CL2CM_DW6_A BUN fix", "DDI PHY programming register defn", "Do ddi_phy_init always", - move PHY register macros next to the corresponding CHV/VLV macros - move DE PLL register macros here from another patch since they are used here first - add BXT_ prefix to CDCLK flags - s/COMMON_RESET/COMMON_RESET_DIS/ and clarify related code comments - fix incorrect read value for the RMW of BXT_PHY_CTL_FAMILY_DDI - fix using GT_DISPLAY_EDP_POWER_ON vs. GT_DISPLAY_DDI_POWER_ON when powering on DDI ports - fix incorrect port when setting BXT_PORT_TX_DW14_LN for DDI ports - add missing masking when programming CDCLK_FREQ_DECIMAL - add missing powering on for DDI-C port, rename OCL2_LDOFUSE_PWR_EN to OCL2_LDOFUSE_PWR_DIS to reduce confusion - add note about mismatch with bspec in the PORT_REF_DW6 fields - factor out PHY init code to a new function, so we can call it for PHY1 and PHY0, instead of open-coding the same v4: (ville) - split the CDCLK/PHY parts into two patches, update commit message accordingly - use the existing dpio_phy enum instead of adding a new one for the same purpose - flip the meaning of PHYs so that PHY_A is PHY1 and PHY_BC is PHY0 to better match CHV - s/BXT_PHY/_BXT_PHY/ - use _PIPE for _BXT_PHY instead of open-coding it - drop _0_2_0_GTTMMADR suffix from BXT_P_CR_GT_DISP_PWRON - define GT_DISPLAY_POWER_ON in a more standard way - make a note that the CHV ConfigDB also disagrees about GRC_CODE field definitions - fix lane optimization refactoring fumble from v3 - add per PHY uninit functions to match the init counterparts Signed-off-by: Vandana Kannan <vandana.kannan@intel.com> (v2) Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Vandana Kannan
Daniel Vetter
parent
f8437dd1b5
commit
5c6706e564
3 changed files with 223 additions and 0 deletions
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@ -1117,6 +1117,102 @@ enum skl_disp_power_wells {
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#define DPIO_FRC_LATENCY_SHFIT 8
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#define CHV_TX_DW14(ch, lane) _TXLANE(ch, lane, 0xb8)
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#define DPIO_UPAR_SHIFT 30
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/* BXT PHY registers */
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#define _BXT_PHY(phy, a, b) _PIPE((phy), (a), (b))
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#define BXT_P_CR_GT_DISP_PWRON 0x138090
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#define GT_DISPLAY_POWER_ON(phy) (1 << (phy))
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#define _PHY_CTL_FAMILY_EDP 0x64C80
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#define _PHY_CTL_FAMILY_DDI 0x64C90
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#define COMMON_RESET_DIS (1 << 31)
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#define BXT_PHY_CTL_FAMILY(phy) _BXT_PHY((phy), _PHY_CTL_FAMILY_DDI, \
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_PHY_CTL_FAMILY_EDP)
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/* BXT PHY common lane registers */
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#define _PORT_CL1CM_DW0_A 0x162000
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#define _PORT_CL1CM_DW0_BC 0x6C000
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#define PHY_POWER_GOOD (1 << 16)
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#define BXT_PORT_CL1CM_DW0(phy) _BXT_PHY((phy), _PORT_CL1CM_DW0_BC, \
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_PORT_CL1CM_DW0_A)
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#define _PORT_CL1CM_DW9_A 0x162024
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#define _PORT_CL1CM_DW9_BC 0x6C024
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#define IREF0RC_OFFSET_SHIFT 8
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#define IREF0RC_OFFSET_MASK (0xFF << IREF0RC_OFFSET_SHIFT)
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#define BXT_PORT_CL1CM_DW9(phy) _BXT_PHY((phy), _PORT_CL1CM_DW9_BC, \
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_PORT_CL1CM_DW9_A)
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#define _PORT_CL1CM_DW10_A 0x162028
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#define _PORT_CL1CM_DW10_BC 0x6C028
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#define IREF1RC_OFFSET_SHIFT 8
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#define IREF1RC_OFFSET_MASK (0xFF << IREF1RC_OFFSET_SHIFT)
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#define BXT_PORT_CL1CM_DW10(phy) _BXT_PHY((phy), _PORT_CL1CM_DW10_BC, \
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_PORT_CL1CM_DW10_A)
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#define _PORT_CL1CM_DW28_A 0x162070
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#define _PORT_CL1CM_DW28_BC 0x6C070
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#define OCL1_POWER_DOWN_EN (1 << 23)
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#define DW28_OLDO_DYN_PWR_DOWN_EN (1 << 22)
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#define SUS_CLK_CONFIG 0x3
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#define BXT_PORT_CL1CM_DW28(phy) _BXT_PHY((phy), _PORT_CL1CM_DW28_BC, \
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_PORT_CL1CM_DW28_A)
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#define _PORT_CL1CM_DW30_A 0x162078
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#define _PORT_CL1CM_DW30_BC 0x6C078
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#define OCL2_LDOFUSE_PWR_DIS (1 << 6)
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#define BXT_PORT_CL1CM_DW30(phy) _BXT_PHY((phy), _PORT_CL1CM_DW30_BC, \
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_PORT_CL1CM_DW30_A)
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/* Defined for PHY0 only */
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#define BXT_PORT_CL2CM_DW6_BC 0x6C358
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#define DW6_OLDO_DYN_PWR_DOWN_EN (1 << 28)
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/* BXT PHY Ref registers */
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#define _PORT_REF_DW3_A 0x16218C
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#define _PORT_REF_DW3_BC 0x6C18C
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#define GRC_DONE (1 << 22)
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#define BXT_PORT_REF_DW3(phy) _BXT_PHY((phy), _PORT_REF_DW3_BC, \
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_PORT_REF_DW3_A)
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#define _PORT_REF_DW6_A 0x162198
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#define _PORT_REF_DW6_BC 0x6C198
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/*
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* FIXME: BSpec/CHV ConfigDB disagrees on the following two fields, fix them
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* after testing.
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*/
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#define GRC_CODE_SHIFT 23
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#define GRC_CODE_MASK (0x1FF << GRC_CODE_SHIFT)
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#define GRC_CODE_FAST_SHIFT 16
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#define GRC_CODE_FAST_MASK (0x7F << GRC_CODE_FAST_SHIFT)
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#define GRC_CODE_SLOW_SHIFT 8
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#define GRC_CODE_SLOW_MASK (0xFF << GRC_CODE_SLOW_SHIFT)
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#define GRC_CODE_NOM_MASK 0xFF
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#define BXT_PORT_REF_DW6(phy) _BXT_PHY((phy), _PORT_REF_DW6_BC, \
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_PORT_REF_DW6_A)
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#define _PORT_REF_DW8_A 0x1621A0
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#define _PORT_REF_DW8_BC 0x6C1A0
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#define GRC_DIS (1 << 15)
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#define GRC_RDY_OVRD (1 << 1)
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#define BXT_PORT_REF_DW8(phy) _BXT_PHY((phy), _PORT_REF_DW8_BC, \
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_PORT_REF_DW8_A)
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/* BXT PHY TX registers */
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#define _BXT_LANE_OFFSET(lane) (((lane) >> 1) * 0x200 + \
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((lane) & 1) * 0x80)
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#define _PORT_TX_DW14_LN0_A 0x162538
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#define _PORT_TX_DW14_LN0_B 0x6C538
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#define _PORT_TX_DW14_LN0_C 0x6C938
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#define LATENCY_OPTIM_SHIFT 30
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#define LATENCY_OPTIM (1 << LATENCY_OPTIM_SHIFT)
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#define BXT_PORT_TX_DW14_LN(port, lane) (_PORT3((port), _PORT_TX_DW14_LN0_A, \
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_PORT_TX_DW14_LN0_B, \
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_PORT_TX_DW14_LN0_C) + \
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_BXT_LANE_OFFSET(lane))
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/*
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* Fence registers
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*/
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@ -1864,6 +1864,130 @@ static void skl_shared_dplls_init(struct drm_i915_private *dev_priv)
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}
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}
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static void broxton_phy_init(struct drm_i915_private *dev_priv,
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enum dpio_phy phy)
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{
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enum port port;
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uint32_t val;
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val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
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val |= GT_DISPLAY_POWER_ON(phy);
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I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val);
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/* Considering 10ms timeout until BSpec is updated */
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if (wait_for(I915_READ(BXT_PORT_CL1CM_DW0(phy)) & PHY_POWER_GOOD, 10))
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DRM_ERROR("timeout during PHY%d power on\n", phy);
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for (port = (phy == DPIO_PHY0 ? PORT_B : PORT_A);
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port <= (phy == DPIO_PHY0 ? PORT_C : PORT_A); port++) {
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int lane;
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for (lane = 0; lane < 4; lane++) {
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val = I915_READ(BXT_PORT_TX_DW14_LN(port, lane));
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/*
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* Note that on CHV this flag is called UPAR, but has
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* the same function.
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*/
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val &= ~LATENCY_OPTIM;
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if (lane != 1)
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val |= LATENCY_OPTIM;
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I915_WRITE(BXT_PORT_TX_DW14_LN(port, lane), val);
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}
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}
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/* Program PLL Rcomp code offset */
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val = I915_READ(BXT_PORT_CL1CM_DW9(phy));
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val &= ~IREF0RC_OFFSET_MASK;
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val |= 0xE4 << IREF0RC_OFFSET_SHIFT;
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I915_WRITE(BXT_PORT_CL1CM_DW9(phy), val);
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val = I915_READ(BXT_PORT_CL1CM_DW10(phy));
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val &= ~IREF1RC_OFFSET_MASK;
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val |= 0xE4 << IREF1RC_OFFSET_SHIFT;
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I915_WRITE(BXT_PORT_CL1CM_DW10(phy), val);
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/* Program power gating */
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val = I915_READ(BXT_PORT_CL1CM_DW28(phy));
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val |= OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN |
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SUS_CLK_CONFIG;
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I915_WRITE(BXT_PORT_CL1CM_DW28(phy), val);
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if (phy == DPIO_PHY0) {
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val = I915_READ(BXT_PORT_CL2CM_DW6_BC);
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val |= DW6_OLDO_DYN_PWR_DOWN_EN;
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I915_WRITE(BXT_PORT_CL2CM_DW6_BC, val);
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}
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val = I915_READ(BXT_PORT_CL1CM_DW30(phy));
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val &= ~OCL2_LDOFUSE_PWR_DIS;
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/*
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* On PHY1 disable power on the second channel, since no port is
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* connected there. On PHY0 both channels have a port, so leave it
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* enabled.
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* TODO: port C is only connected on BXT-P, so on BXT0/1 we should
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* power down the second channel on PHY0 as well.
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*/
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if (phy == DPIO_PHY1)
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val |= OCL2_LDOFUSE_PWR_DIS;
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I915_WRITE(BXT_PORT_CL1CM_DW30(phy), val);
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if (phy == DPIO_PHY0) {
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uint32_t grc_code;
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/*
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* PHY0 isn't connected to an RCOMP resistor so copy over
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* the corresponding calibrated value from PHY1, and disable
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* the automatic calibration on PHY0.
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*/
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if (wait_for(I915_READ(BXT_PORT_REF_DW3(DPIO_PHY1)) & GRC_DONE,
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10))
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DRM_ERROR("timeout waiting for PHY1 GRC\n");
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val = I915_READ(BXT_PORT_REF_DW6(DPIO_PHY1));
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val = (val & GRC_CODE_MASK) >> GRC_CODE_SHIFT;
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grc_code = val << GRC_CODE_FAST_SHIFT |
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val << GRC_CODE_SLOW_SHIFT |
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val;
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I915_WRITE(BXT_PORT_REF_DW6(DPIO_PHY0), grc_code);
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val = I915_READ(BXT_PORT_REF_DW8(DPIO_PHY0));
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val |= GRC_DIS | GRC_RDY_OVRD;
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I915_WRITE(BXT_PORT_REF_DW8(DPIO_PHY0), val);
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}
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val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
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val |= COMMON_RESET_DIS;
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I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
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}
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void broxton_ddi_phy_init(struct drm_device *dev)
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{
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/* Enable PHY1 first since it provides Rcomp for PHY0 */
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broxton_phy_init(dev->dev_private, DPIO_PHY1);
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broxton_phy_init(dev->dev_private, DPIO_PHY0);
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}
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static void broxton_phy_uninit(struct drm_i915_private *dev_priv,
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enum dpio_phy phy)
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{
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uint32_t val;
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val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
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val &= ~COMMON_RESET_DIS;
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I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
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}
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void broxton_ddi_phy_uninit(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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broxton_phy_uninit(dev_priv, DPIO_PHY1);
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broxton_phy_uninit(dev_priv, DPIO_PHY0);
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/* FIXME: do this in broxton_phy_uninit per phy */
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I915_WRITE(BXT_P_CR_GT_DISP_PWRON, 0);
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}
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void intel_ddi_pll_init(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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@ -1882,6 +2006,7 @@ void intel_ddi_pll_init(struct drm_device *dev)
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DRM_ERROR("LCPLL1 is disabled\n");
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} else if (IS_BROXTON(dev)) {
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broxton_init_cdclk(dev);
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broxton_ddi_phy_init(dev);
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} else {
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/*
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* The LCPLL register should be turned on by the BIOS. For now
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@ -1115,6 +1115,8 @@ void hsw_disable_pc8(struct drm_i915_private *dev_priv);
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void broxton_init_cdclk(struct drm_device *dev);
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void broxton_uninit_cdclk(struct drm_device *dev);
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void broxton_set_cdclk(struct drm_device *dev, int frequency);
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void broxton_ddi_phy_init(struct drm_device *dev);
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void broxton_ddi_phy_uninit(struct drm_device *dev);
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void intel_dp_get_m_n(struct intel_crtc *crtc,
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struct intel_crtc_state *pipe_config);
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void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
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