Aliasing VIPT dcache support for ARC
I'm satisified with testing, specially with fuse which has historically given grief to VIPT arches (ARM/PARISC...) -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIcBAABAgAGBQJRjPVlAAoJEGnX8d3iisJeF60P/36JELOrdTOJB8GDn/i22yu4 zxFrroH4EpXCobe4JzrmhXU0vdMKmyhaRsdmQt2pV474LX1ajQeoRi6n7xuiYymr p0H8/jde7ZDHGxJRP9OIuIIU57N+sVwQvrXvfnz/dc4c92MD9EWEwvoytnCVuKSx k/YIQ5oDj6hFH13V68eXXs+KBrXyPiYO9UIWYmwRZv/0Bm6P1EpXQSMWzeCP0X/y FHVEc4i92bIkqpOadUnhCBHGZqjkrhwFL2FCI35/12TgSwjPU1Q6IJCtH7Lg9ygI oFqut5wN+dhkxlfiyvgTXErmnvhDOHLbMQJYC9svHin8TtfznQhJDAWYeSH/6Mde /hE/bXV55ucdJ48ZT6JRvxHeJQgTAvbXDIIQYe/wAJEvXidWEo4Y/qRTIXP03Ixm Ie69d9WSmUlx4FmYxBQodDQFK9slnc+0UfsWcCG+OrT0wwrKBRr3To2WYEFowQer fpIk6/68+LiQK+IzFAhPtBppSgcQoEBsXAD/MDKsQcRk84W1nKPt6SiT/wCAzOZ7 ezTL1eSlfzWXNbtohdm8xN8frt/4fZLZTaZkqtnMPBi0iIC5DAsJy27YlBQDaRd/ Hzd0y6bJQDcsjjWmZuUkFZVbCyYlE0CIW6sbHC91i51egKReYHy7T6Ef/n+qn+ho jxohq5/JvG+0Vha0Q2h6 =r4lw -----END PGP SIGNATURE----- Merge tag 'arc-v3.10-rc1-part2' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc Pull second set of arc arch updates from Vineet Gupta: "Aliasing VIPT dcache support for ARC I'm satisified with testing, specially with fuse which has historically given grief to VIPT arches (ARM/PARISC...)" * tag 'arc-v3.10-rc1-part2' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc: ARC: [TB10x] Remove GENERIC_GPIO ARC: [mm] Aliasing VIPT dcache support 4/4 ARC: [mm] Aliasing VIPT dcache support 3/4 ARC: [mm] Aliasing VIPT dcache support 2/4 ARC: [mm] Aliasing VIPT dcache support 1/4 ARC: [mm] refactor the core (i|d)cache line ops loops ARC: [mm] serious bug in vaddr based icache flush
This commit is contained in:
Linus Torvalds
commit
6019958d14
13 changed files with 377 additions and 74 deletions
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@ -182,6 +182,10 @@ config ARC_CACHE_PAGES
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Note that Global I/D ENABLE + Per Page DISABLE works but corollary
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Global DISABLE + Per Page ENABLE won't work
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config ARC_CACHE_VIPT_ALIASING
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bool "Support VIPT Aliasing D$"
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default n
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endif #ARC_CACHE
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config ARC_HAS_ICCM
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@ -32,7 +32,6 @@ generic-y += resource.h
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generic-y += scatterlist.h
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generic-y += sembuf.h
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generic-y += shmbuf.h
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generic-y += shmparam.h
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generic-y += siginfo.h
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generic-y += socket.h
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generic-y += sockios.h
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@ -55,9 +55,6 @@
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: "r"(data), "r"(ptr)); \
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})
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/* used to give SHMLBA a value to avoid Cache Aliasing */
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extern unsigned int ARC_shmlba;
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#define ARCH_DMA_MINALIGN L1_CACHE_BYTES
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/*
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@ -19,6 +19,7 @@
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#define _ASM_CACHEFLUSH_H
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#include <linux/mm.h>
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#include <asm/shmparam.h>
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/*
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* Semantically we need this because icache doesn't snoop dcache/dma.
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@ -33,7 +34,9 @@ void flush_cache_all(void);
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void flush_icache_range(unsigned long start, unsigned long end);
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void __sync_icache_dcache(unsigned long paddr, unsigned long vaddr, int len);
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void __inv_icache_page(unsigned long paddr, unsigned long vaddr);
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void __flush_dcache_page(unsigned long paddr);
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void ___flush_dcache_page(unsigned long paddr, unsigned long vaddr);
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#define __flush_dcache_page(p, v) \
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___flush_dcache_page((unsigned long)p, (unsigned long)v)
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#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
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@ -50,18 +53,55 @@ void dma_cache_wback(unsigned long start, unsigned long sz);
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#define flush_cache_vmap(start, end) flush_cache_all()
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#define flush_cache_vunmap(start, end) flush_cache_all()
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/*
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* VM callbacks when entire/range of user-space V-P mappings are
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* torn-down/get-invalidated
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*
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* Currently we don't support D$ aliasing configs for our VIPT caches
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* NOPS for VIPT Cache with non-aliasing D$ configurations only
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*/
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#define flush_cache_dup_mm(mm) /* called on fork */
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#define flush_cache_dup_mm(mm) /* called on fork (VIVT only) */
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#ifndef CONFIG_ARC_CACHE_VIPT_ALIASING
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#define flush_cache_mm(mm) /* called on munmap/exit */
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#define flush_cache_range(mm, u_vstart, u_vend)
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#define flush_cache_page(vma, u_vaddr, pfn) /* PF handling/COW-break */
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#else /* VIPT aliasing dcache */
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/* To clear out stale userspace mappings */
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void flush_cache_mm(struct mm_struct *mm);
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void flush_cache_range(struct vm_area_struct *vma,
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unsigned long start,unsigned long end);
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void flush_cache_page(struct vm_area_struct *vma,
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unsigned long user_addr, unsigned long page);
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/*
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* To make sure that userspace mapping is flushed to memory before
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* get_user_pages() uses a kernel mapping to access the page
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*/
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#define ARCH_HAS_FLUSH_ANON_PAGE
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void flush_anon_page(struct vm_area_struct *vma,
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struct page *page, unsigned long u_vaddr);
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#endif /* CONFIG_ARC_CACHE_VIPT_ALIASING */
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/*
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* Simple wrapper over config option
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* Bootup code ensures that hardware matches kernel configuration
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*/
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static inline int cache_is_vipt_aliasing(void)
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{
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#ifdef CONFIG_ARC_CACHE_VIPT_ALIASING
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return 1;
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#else
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return 0;
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#endif
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}
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#define CACHE_COLOR(addr) (((unsigned long)(addr) >> (PAGE_SHIFT)) & 3)
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/*
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* checks if two addresses (after page aligning) index into same cache set
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*/
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#define addr_not_cache_congruent(addr1, addr2) \
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cache_is_vipt_aliasing() ? \
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(CACHE_COLOR(addr1) != CACHE_COLOR(addr2)) : 0 \
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#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
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do { \
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memcpy(dst, src, len); \
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@ -16,13 +16,27 @@
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#define get_user_page(vaddr) __get_free_page(GFP_KERNEL)
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#define free_user_page(page, addr) free_page(addr)
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/* TBD: for now don't worry about VIPT D$ aliasing */
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#define clear_page(paddr) memset((paddr), 0, PAGE_SIZE)
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#define copy_page(to, from) memcpy((to), (from), PAGE_SIZE)
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#ifndef CONFIG_ARC_CACHE_VIPT_ALIASING
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#define clear_user_page(addr, vaddr, pg) clear_page(addr)
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#define copy_user_page(vto, vfrom, vaddr, pg) copy_page(vto, vfrom)
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#else /* VIPT aliasing dcache */
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struct vm_area_struct;
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struct page;
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#define __HAVE_ARCH_COPY_USER_HIGHPAGE
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void copy_user_highpage(struct page *to, struct page *from,
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unsigned long u_vaddr, struct vm_area_struct *vma);
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void clear_user_page(void *to, unsigned long u_vaddr, struct page *page);
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#endif /* CONFIG_ARC_CACHE_VIPT_ALIASING */
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#undef STRICT_MM_TYPECHECKS
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#ifdef STRICT_MM_TYPECHECKS
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@ -395,6 +395,9 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned long address,
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#include <asm-generic/pgtable.h>
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/* to cope with aliasing VIPT cache */
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#define HAVE_ARCH_UNMAPPED_AREA
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/*
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* No page table caches to initialise
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*/
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18
arch/arc/include/asm/shmparam.h
Normal file
18
arch/arc/include/asm/shmparam.h
Normal file
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@ -0,0 +1,18 @@
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/*
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* Copyright (C) 2013 Synopsys, Inc. (www.synopsys.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ARC_ASM_SHMPARAM_H
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#define __ARC_ASM_SHMPARAM_H
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/* Handle upto 2 cache bins */
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#define SHMLBA (2 * PAGE_SIZE)
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/* Enforce SHMLBA in shmat */
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#define __ARCH_FORCE_SHMLBA
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#endif
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@ -30,13 +30,20 @@ do { \
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/*
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* This pair is called at time of munmap/exit to flush cache and TLB entries
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* for mappings being torn down.
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* 1) cache-flush part -implemented via tlb_start_vma( ) can be NOP (for now)
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* as we don't support aliasing configs in our VIPT D$.
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* 1) cache-flush part -implemented via tlb_start_vma( ) for VIPT aliasing D$
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* 2) tlb-flush part - implemted via tlb_end_vma( ) flushes the TLB range
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*
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* Note, read http://lkml.org/lkml/2004/1/15/6
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*/
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#ifndef CONFIG_ARC_CACHE_VIPT_ALIASING
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#define tlb_start_vma(tlb, vma)
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#else
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#define tlb_start_vma(tlb, vma) \
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do { \
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if (!tlb->fullmm) \
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flush_cache_range(vma, vma->vm_start, vma->vm_end); \
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} while(0)
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#endif
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#define tlb_end_vma(tlb, vma) \
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do { \
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@ -7,4 +7,4 @@
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#
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obj-y := extable.o ioremap.o dma.o fault.o init.o
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obj-y += tlb.o tlbex.o cache_arc700.o
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obj-y += tlb.o tlbex.o cache_arc700.o mmap.o
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@ -68,6 +68,7 @@
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#include <linux/mmu_context.h>
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#include <linux/syscalls.h>
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#include <linux/uaccess.h>
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#include <linux/pagemap.h>
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#include <asm/cacheflush.h>
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#include <asm/cachectl.h>
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#include <asm/setup.h>
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@ -138,6 +139,7 @@ void __cpuinit arc_cache_init(void)
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struct cpuinfo_arc_cache *ic = &cpuinfo_arc700[cpu].icache;
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struct cpuinfo_arc_cache *dc = &cpuinfo_arc700[cpu].dcache;
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int way_pg_ratio = way_pg_ratio;
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int dcache_does_alias;
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char str[256];
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printk(arc_cache_mumbojumbo(0, str, sizeof(str)));
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@ -184,9 +186,13 @@ chk_dc:
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panic("Cache H/W doesn't match kernel Config");
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}
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dcache_does_alias = (dc->sz / ARC_DCACHE_WAYS) > PAGE_SIZE;
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/* check for D-Cache aliasing */
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if ((dc->sz / ARC_DCACHE_WAYS) > PAGE_SIZE)
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panic("D$ aliasing not handled right now\n");
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if (dcache_does_alias && !cache_is_vipt_aliasing())
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panic("Enable CONFIG_ARC_CACHE_VIPT_ALIASING\n");
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else if (!dcache_does_alias && cache_is_vipt_aliasing())
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panic("Don't need CONFIG_ARC_CACHE_VIPT_ALIASING\n");
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#endif
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/* Set the default Invalidate Mode to "simpy discard dirty lines"
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@ -269,47 +275,57 @@ static inline void __dc_entire_op(const int cacheop)
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* Per Line Operation on D-Cache
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* Doesn't deal with type-of-op/IRQ-disabling/waiting-for-flush-to-complete
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* It's sole purpose is to help gcc generate ZOL
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* (aliasing VIPT dcache flushing needs both vaddr and paddr)
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*/
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static inline void __dc_line_loop(unsigned long start, unsigned long sz,
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int aux_reg)
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static inline void __dc_line_loop(unsigned long paddr, unsigned long vaddr,
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unsigned long sz, const int aux_reg)
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{
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int num_lines, slack;
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int num_lines;
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/* Ensure we properly floor/ceil the non-line aligned/sized requests
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* and have @start - aligned to cache line and integral @num_lines.
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* and have @paddr - aligned to cache line and integral @num_lines.
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* This however can be avoided for page sized since:
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* -@start will be cache-line aligned already (being page aligned)
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* -@paddr will be cache-line aligned already (being page aligned)
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* -@sz will be integral multiple of line size (being page sized).
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*/
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if (!(__builtin_constant_p(sz) && sz == PAGE_SIZE)) {
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slack = start & ~DCACHE_LINE_MASK;
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sz += slack;
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start -= slack;
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sz += paddr & ~DCACHE_LINE_MASK;
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paddr &= DCACHE_LINE_MASK;
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vaddr &= DCACHE_LINE_MASK;
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}
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num_lines = DIV_ROUND_UP(sz, ARC_DCACHE_LINE_LEN);
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#if (CONFIG_ARC_MMU_VER <= 2)
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paddr |= (vaddr >> PAGE_SHIFT) & 0x1F;
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#endif
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while (num_lines-- > 0) {
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#if (CONFIG_ARC_MMU_VER > 2)
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/*
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* Just as for I$, in MMU v3, D$ ops also require
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* "tag" bits in DC_PTAG, "index" bits in FLDL,IVDL ops
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* But we pass phy addr for both. This works since Linux
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* doesn't support aliasing configs for D$, yet.
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* Thus paddr is enough to provide both tag and index.
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*/
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write_aux_reg(ARC_REG_DC_PTAG, start);
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write_aux_reg(ARC_REG_DC_PTAG, paddr);
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write_aux_reg(aux_reg, vaddr);
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vaddr += ARC_DCACHE_LINE_LEN;
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#else
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/* paddr contains stuffed vaddrs bits */
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write_aux_reg(aux_reg, paddr);
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#endif
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write_aux_reg(aux_reg, start);
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start += ARC_DCACHE_LINE_LEN;
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paddr += ARC_DCACHE_LINE_LEN;
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}
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}
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/* For kernel mappings cache operation: index is same as paddr */
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#define __dc_line_op_k(p, sz, op) __dc_line_op(p, p, sz, op)
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/*
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* D-Cache : Per Line INV (discard or wback+discard) or FLUSH (wback)
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*/
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static inline void __dc_line_op(unsigned long start, unsigned long sz,
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const int cacheop)
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static inline void __dc_line_op(unsigned long paddr, unsigned long vaddr,
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unsigned long sz, const int cacheop)
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{
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unsigned long flags, tmp = tmp;
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int aux;
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@ -332,7 +348,7 @@ static inline void __dc_line_op(unsigned long start, unsigned long sz,
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else
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aux = ARC_REG_DC_FLDL;
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__dc_line_loop(start, sz, aux);
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__dc_line_loop(paddr, vaddr, sz, aux);
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if (cacheop & OP_FLUSH) /* flush / flush-n-inv both wait */
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wait_for_flush();
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@ -347,7 +363,8 @@ static inline void __dc_line_op(unsigned long start, unsigned long sz,
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#else
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#define __dc_entire_op(cacheop)
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#define __dc_line_op(start, sz, cacheop)
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#define __dc_line_op(paddr, vaddr, sz, cacheop)
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#define __dc_line_op_k(paddr, sz, cacheop)
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#endif /* CONFIG_ARC_HAS_DCACHE */
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@ -399,49 +416,45 @@ static inline void __dc_line_op(unsigned long start, unsigned long sz,
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/***********************************************************
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* Machine specific helper for per line I-Cache invalidate.
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*/
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static void __ic_line_inv_vaddr(unsigned long phy_start, unsigned long vaddr,
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static void __ic_line_inv_vaddr(unsigned long paddr, unsigned long vaddr,
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unsigned long sz)
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{
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unsigned long flags;
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int num_lines, slack;
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unsigned int addr;
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int num_lines;
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/*
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* Ensure we properly floor/ceil the non-line aligned/sized requests:
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* However page sized flushes can be compile time optimised.
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* -@phy_start will be cache-line aligned already (being page aligned)
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* -@paddr will be cache-line aligned already (being page aligned)
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* -@sz will be integral multiple of line size (being page sized).
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*/
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if (!(__builtin_constant_p(sz) && sz == PAGE_SIZE)) {
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slack = phy_start & ~ICACHE_LINE_MASK;
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sz += slack;
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phy_start -= slack;
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sz += paddr & ~ICACHE_LINE_MASK;
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paddr &= ICACHE_LINE_MASK;
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vaddr &= ICACHE_LINE_MASK;
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}
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num_lines = DIV_ROUND_UP(sz, ARC_ICACHE_LINE_LEN);
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#if (CONFIG_ARC_MMU_VER > 2)
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vaddr &= ~ICACHE_LINE_MASK;
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addr = phy_start;
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#else
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#if (CONFIG_ARC_MMU_VER <= 2)
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/* bits 17:13 of vaddr go as bits 4:0 of paddr */
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addr = phy_start | ((vaddr >> 13) & 0x1F);
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paddr |= (vaddr >> PAGE_SHIFT) & 0x1F;
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#endif
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local_irq_save(flags);
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while (num_lines-- > 0) {
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#if (CONFIG_ARC_MMU_VER > 2)
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/* tag comes from phy addr */
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write_aux_reg(ARC_REG_IC_PTAG, addr);
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write_aux_reg(ARC_REG_IC_PTAG, paddr);
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/* index bits come from vaddr */
|
||||
write_aux_reg(ARC_REG_IC_IVIL, vaddr);
|
||||
vaddr += ARC_ICACHE_LINE_LEN;
|
||||
#else
|
||||
/* paddr contains stuffed vaddrs bits */
|
||||
write_aux_reg(ARC_REG_IC_IVIL, addr);
|
||||
write_aux_reg(ARC_REG_IC_IVIL, paddr);
|
||||
#endif
|
||||
addr += ARC_ICACHE_LINE_LEN;
|
||||
paddr += ARC_ICACHE_LINE_LEN;
|
||||
}
|
||||
local_irq_restore(flags);
|
||||
}
|
||||
|
|
@ -457,29 +470,66 @@ static void __ic_line_inv_vaddr(unsigned long phy_start, unsigned long vaddr,
|
|||
* Exported APIs
|
||||
*/
|
||||
|
||||
/*
|
||||
* Handle cache congruency of kernel and userspace mappings of page when kernel
|
||||
* writes-to/reads-from
|
||||
*
|
||||
* The idea is to defer flushing of kernel mapping after a WRITE, possible if:
|
||||
* -dcache is NOT aliasing, hence any U/K-mappings of page are congruent
|
||||
* -U-mapping doesn't exist yet for page (finalised in update_mmu_cache)
|
||||
* -In SMP, if hardware caches are coherent
|
||||
*
|
||||
* There's a corollary case, where kernel READs from a userspace mapped page.
|
||||
* If the U-mapping is not congruent to to K-mapping, former needs flushing.
|
||||
*/
|
||||
void flush_dcache_page(struct page *page)
|
||||
{
|
||||
/* Make a note that dcache is not yet flushed for this page */
|
||||
set_bit(PG_arch_1, &page->flags);
|
||||
struct address_space *mapping;
|
||||
|
||||
if (!cache_is_vipt_aliasing()) {
|
||||
set_bit(PG_arch_1, &page->flags);
|
||||
return;
|
||||
}
|
||||
|
||||
/* don't handle anon pages here */
|
||||
mapping = page_mapping(page);
|
||||
if (!mapping)
|
||||
return;
|
||||
|
||||
/*
|
||||
* pagecache page, file not yet mapped to userspace
|
||||
* Make a note that K-mapping is dirty
|
||||
*/
|
||||
if (!mapping_mapped(mapping)) {
|
||||
set_bit(PG_arch_1, &page->flags);
|
||||
} else if (page_mapped(page)) {
|
||||
|
||||
/* kernel reading from page with U-mapping */
|
||||
void *paddr = page_address(page);
|
||||
unsigned long vaddr = page->index << PAGE_CACHE_SHIFT;
|
||||
|
||||
if (addr_not_cache_congruent(paddr, vaddr))
|
||||
__flush_dcache_page(paddr, vaddr);
|
||||
}
|
||||
}
|
||||
EXPORT_SYMBOL(flush_dcache_page);
|
||||
|
||||
|
||||
void dma_cache_wback_inv(unsigned long start, unsigned long sz)
|
||||
{
|
||||
__dc_line_op(start, sz, OP_FLUSH_N_INV);
|
||||
__dc_line_op_k(start, sz, OP_FLUSH_N_INV);
|
||||
}
|
||||
EXPORT_SYMBOL(dma_cache_wback_inv);
|
||||
|
||||
void dma_cache_inv(unsigned long start, unsigned long sz)
|
||||
{
|
||||
__dc_line_op(start, sz, OP_INV);
|
||||
__dc_line_op_k(start, sz, OP_INV);
|
||||
}
|
||||
EXPORT_SYMBOL(dma_cache_inv);
|
||||
|
||||
void dma_cache_wback(unsigned long start, unsigned long sz)
|
||||
{
|
||||
__dc_line_op(start, sz, OP_FLUSH);
|
||||
__dc_line_op_k(start, sz, OP_FLUSH);
|
||||
}
|
||||
EXPORT_SYMBOL(dma_cache_wback);
|
||||
|
||||
|
|
@ -560,7 +610,7 @@ void __sync_icache_dcache(unsigned long paddr, unsigned long vaddr, int len)
|
|||
|
||||
local_irq_save(flags);
|
||||
__ic_line_inv_vaddr(paddr, vaddr, len);
|
||||
__dc_line_op(paddr, len, OP_FLUSH);
|
||||
__dc_line_op(paddr, vaddr, len, OP_FLUSH);
|
||||
local_irq_restore(flags);
|
||||
}
|
||||
|
||||
|
|
@ -570,9 +620,13 @@ void __inv_icache_page(unsigned long paddr, unsigned long vaddr)
|
|||
__ic_line_inv_vaddr(paddr, vaddr, PAGE_SIZE);
|
||||
}
|
||||
|
||||
void __flush_dcache_page(unsigned long paddr)
|
||||
/*
|
||||
* wrapper to clearout kernel or userspace mappings of a page
|
||||
* For kernel mappings @vaddr == @paddr
|
||||
*/
|
||||
void ___flush_dcache_page(unsigned long paddr, unsigned long vaddr)
|
||||
{
|
||||
__dc_line_op(paddr, PAGE_SIZE, OP_FLUSH_N_INV);
|
||||
__dc_line_op(paddr, vaddr & PAGE_MASK, PAGE_SIZE, OP_FLUSH_N_INV);
|
||||
}
|
||||
|
||||
void flush_icache_all(void)
|
||||
|
|
@ -601,6 +655,87 @@ noinline void flush_cache_all(void)
|
|||
|
||||
}
|
||||
|
||||
#ifdef CONFIG_ARC_CACHE_VIPT_ALIASING
|
||||
|
||||
void flush_cache_mm(struct mm_struct *mm)
|
||||
{
|
||||
flush_cache_all();
|
||||
}
|
||||
|
||||
void flush_cache_page(struct vm_area_struct *vma, unsigned long u_vaddr,
|
||||
unsigned long pfn)
|
||||
{
|
||||
unsigned int paddr = pfn << PAGE_SHIFT;
|
||||
|
||||
__sync_icache_dcache(paddr, u_vaddr, PAGE_SIZE);
|
||||
}
|
||||
|
||||
void flush_cache_range(struct vm_area_struct *vma, unsigned long start,
|
||||
unsigned long end)
|
||||
{
|
||||
flush_cache_all();
|
||||
}
|
||||
|
||||
void copy_user_highpage(struct page *to, struct page *from,
|
||||
unsigned long u_vaddr, struct vm_area_struct *vma)
|
||||
{
|
||||
void *kfrom = page_address(from);
|
||||
void *kto = page_address(to);
|
||||
int clean_src_k_mappings = 0;
|
||||
|
||||
/*
|
||||
* If SRC page was already mapped in userspace AND it's U-mapping is
|
||||
* not congruent with K-mapping, sync former to physical page so that
|
||||
* K-mapping in memcpy below, sees the right data
|
||||
*
|
||||
* Note that while @u_vaddr refers to DST page's userspace vaddr, it is
|
||||
* equally valid for SRC page as well
|
||||
*/
|
||||
if (page_mapped(from) && addr_not_cache_congruent(kfrom, u_vaddr)) {
|
||||
__flush_dcache_page(kfrom, u_vaddr);
|
||||
clean_src_k_mappings = 1;
|
||||
}
|
||||
|
||||
copy_page(kto, kfrom);
|
||||
|
||||
/*
|
||||
* Mark DST page K-mapping as dirty for a later finalization by
|
||||
* update_mmu_cache(). Although the finalization could have been done
|
||||
* here as well (given that both vaddr/paddr are available).
|
||||
* But update_mmu_cache() already has code to do that for other
|
||||
* non copied user pages (e.g. read faults which wire in pagecache page
|
||||
* directly).
|
||||
*/
|
||||
set_bit(PG_arch_1, &to->flags);
|
||||
|
||||
/*
|
||||
* if SRC was already usermapped and non-congruent to kernel mapping
|
||||
* sync the kernel mapping back to physical page
|
||||
*/
|
||||
if (clean_src_k_mappings) {
|
||||
__flush_dcache_page(kfrom, kfrom);
|
||||
} else {
|
||||
set_bit(PG_arch_1, &from->flags);
|
||||
}
|
||||
}
|
||||
|
||||
void clear_user_page(void *to, unsigned long u_vaddr, struct page *page)
|
||||
{
|
||||
clear_page(to);
|
||||
set_bit(PG_arch_1, &page->flags);
|
||||
}
|
||||
|
||||
void flush_anon_page(struct vm_area_struct *vma, struct page *page,
|
||||
unsigned long u_vaddr)
|
||||
{
|
||||
/* TBD: do we really need to clear the kernel mapping */
|
||||
__flush_dcache_page(page_address(page), u_vaddr);
|
||||
__flush_dcache_page(page_address(page), page_address(page));
|
||||
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
/**********************************************************************
|
||||
* Explicit Cache flush request from user space via syscall
|
||||
* Needed for JITs which generate code on the fly
|
||||
|
|
|
|||
78
arch/arc/mm/mmap.c
Normal file
78
arch/arc/mm/mmap.c
Normal file
|
|
@ -0,0 +1,78 @@
|
|||
/*
|
||||
* ARC700 mmap
|
||||
*
|
||||
* (started from arm version - for VIPT alias handling)
|
||||
*
|
||||
* Copyright (C) 2013 Synopsys, Inc. (www.synopsys.com)
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/fs.h>
|
||||
#include <linux/mm.h>
|
||||
#include <linux/mman.h>
|
||||
#include <linux/sched.h>
|
||||
#include <asm/cacheflush.h>
|
||||
|
||||
#define COLOUR_ALIGN(addr, pgoff) \
|
||||
((((addr) + SHMLBA - 1) & ~(SHMLBA - 1)) + \
|
||||
(((pgoff) << PAGE_SHIFT) & (SHMLBA - 1)))
|
||||
|
||||
/*
|
||||
* Ensure that shared mappings are correctly aligned to
|
||||
* avoid aliasing issues with VIPT caches.
|
||||
* We need to ensure that
|
||||
* a specific page of an object is always mapped at a multiple of
|
||||
* SHMLBA bytes.
|
||||
*/
|
||||
unsigned long
|
||||
arch_get_unmapped_area(struct file *filp, unsigned long addr,
|
||||
unsigned long len, unsigned long pgoff, unsigned long flags)
|
||||
{
|
||||
struct mm_struct *mm = current->mm;
|
||||
struct vm_area_struct *vma;
|
||||
int do_align = 0;
|
||||
int aliasing = cache_is_vipt_aliasing();
|
||||
struct vm_unmapped_area_info info;
|
||||
|
||||
/*
|
||||
* We only need to do colour alignment if D cache aliases.
|
||||
*/
|
||||
if (aliasing)
|
||||
do_align = filp || (flags & MAP_SHARED);
|
||||
|
||||
/*
|
||||
* We enforce the MAP_FIXED case.
|
||||
*/
|
||||
if (flags & MAP_FIXED) {
|
||||
if (aliasing && flags & MAP_SHARED &&
|
||||
(addr - (pgoff << PAGE_SHIFT)) & (SHMLBA - 1))
|
||||
return -EINVAL;
|
||||
return addr;
|
||||
}
|
||||
|
||||
if (len > TASK_SIZE)
|
||||
return -ENOMEM;
|
||||
|
||||
if (addr) {
|
||||
if (do_align)
|
||||
addr = COLOUR_ALIGN(addr, pgoff);
|
||||
else
|
||||
addr = PAGE_ALIGN(addr);
|
||||
|
||||
vma = find_vma(mm, addr);
|
||||
if (TASK_SIZE - len >= addr &&
|
||||
(!vma || addr + len <= vma->vm_start))
|
||||
return addr;
|
||||
}
|
||||
|
||||
info.flags = 0;
|
||||
info.length = len;
|
||||
info.low_limit = mm->mmap_base;
|
||||
info.high_limit = TASK_SIZE;
|
||||
info.align_mask = do_align ? (PAGE_MASK & (SHMLBA - 1)) : 0;
|
||||
info.align_offset = pgoff << PAGE_SHIFT;
|
||||
return vm_unmapped_area(&info);
|
||||
}
|
||||
|
|
@ -421,25 +421,40 @@ void create_tlb(struct vm_area_struct *vma, unsigned long address, pte_t *ptep)
|
|||
/*
|
||||
* Called at the end of pagefault, for a userspace mapped page
|
||||
* -pre-install the corresponding TLB entry into MMU
|
||||
* -Finalize the delayed D-cache flush (wback+inv kernel mapping)
|
||||
* -Finalize the delayed D-cache flush of kernel mapping of page due to
|
||||
* flush_dcache_page(), copy_user_page()
|
||||
*
|
||||
* Note that flush (when done) involves both WBACK - so physical page is
|
||||
* in sync as well as INV - so any non-congruent aliases don't remain
|
||||
*/
|
||||
void update_mmu_cache(struct vm_area_struct *vma, unsigned long vaddr_unaligned,
|
||||
pte_t *ptep)
|
||||
{
|
||||
unsigned long vaddr = vaddr_unaligned & PAGE_MASK;
|
||||
unsigned long paddr = pte_val(*ptep) & PAGE_MASK;
|
||||
|
||||
create_tlb(vma, vaddr, ptep);
|
||||
|
||||
/* icache doesn't snoop dcache, thus needs to be made coherent here */
|
||||
if (vma->vm_flags & VM_EXEC) {
|
||||
/*
|
||||
* Exec page : Independent of aliasing/page-color considerations,
|
||||
* since icache doesn't snoop dcache on ARC, any dirty
|
||||
* K-mapping of a code page needs to be wback+inv so that
|
||||
* icache fetch by userspace sees code correctly.
|
||||
* !EXEC page: If K-mapping is NOT congruent to U-mapping, flush it
|
||||
* so userspace sees the right data.
|
||||
* (Avoids the flush for Non-exec + congruent mapping case)
|
||||
*/
|
||||
if (vma->vm_flags & VM_EXEC || addr_not_cache_congruent(paddr, vaddr)) {
|
||||
struct page *page = pfn_to_page(pte_pfn(*ptep));
|
||||
|
||||
/* if page was dcache dirty, flush now */
|
||||
int dirty = test_and_clear_bit(PG_arch_1, &page->flags);
|
||||
if (dirty) {
|
||||
unsigned long paddr = pte_val(*ptep) & PAGE_MASK;
|
||||
__flush_dcache_page(paddr);
|
||||
__inv_icache_page(paddr, vaddr);
|
||||
/* wback + inv dcache lines */
|
||||
__flush_dcache_page(paddr, paddr);
|
||||
|
||||
/* invalidate any existing icache lines */
|
||||
if (vma->vm_flags & VM_EXEC)
|
||||
__inv_icache_page(paddr, vaddr);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -27,10 +27,3 @@ menuconfig ARC_PLAT_TB10X
|
|||
Abilis Systems. TB10x is based on the ARC700 CPU architecture.
|
||||
Say Y if you are building a kernel for one of the SOCs in this
|
||||
series (e.g. TB100 or TB101). If in doubt say N.
|
||||
|
||||
if ARC_PLAT_TB10X
|
||||
|
||||
config GENERIC_GPIO
|
||||
def_bool y
|
||||
|
||||
endif
|
||||
|
|
|
|||
Loading…
Reference in a new issue