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parisc: Initialize PCI bridge cache line and default latency

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PCI controllers and pci-pci bridges may have not been fully initialized
regarding cache line and defaul latency.

This partly reverts
commit 5f0e9b4 ("parisc: Remove unused pcibios_init_bus()")

Signed-off-by: Helge Deller <deller@gmx.de>
This commit is contained in:
Helge Deller 2015-12-21 10:00:49 +01:00
parent afd2ff9b7e
commit 602c9c9a01
4 changed files with 33 additions and 2 deletions
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1
arch/parisc/include/asm/pci.h
View file

@ -167,6 +167,7 @@ static inline void pcibios_register_hba(struct pci_hba_data *x)
{
}
#endif
extern void pcibios_init_bridge(struct pci_dev *);
/*
* pcibios_assign_all_busses() is used in drivers/pci/pci.c:pci_do_scan_bus()

26
arch/parisc/kernel/pci.c
View file

@ -170,6 +170,32 @@ void pcibios_set_master(struct pci_dev *dev)
(0x80 << 8) | pci_cache_line_size);
}
/*
* pcibios_init_bridge() initializes cache line and default latency
* for pci controllers and pci-pci bridges
*/
void __init pcibios_init_bridge(struct pci_dev *dev)
{
unsigned short bridge_ctl, bridge_ctl_new;
/* We deal only with pci controllers and pci-pci bridges. */
if (!dev || (dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
return;
/* PCI-PCI bridge - set the cache line and default latency
* (32) for primary and secondary buses.
*/
pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER, 32);
pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bridge_ctl);
bridge_ctl_new = bridge_ctl | PCI_BRIDGE_CTL_PARITY |
PCI_BRIDGE_CTL_SERR | PCI_BRIDGE_CTL_MASTER_ABORT;
dev_info(&dev->dev, "Changing bridge control from 0x%08x to 0x%08x\n",
bridge_ctl, bridge_ctl_new);
pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bridge_ctl_new);
}
/*
* pcibios align resources() is called every time generic PCI code

4
drivers/parisc/dino.c
View file

@ -599,8 +599,10 @@ dino_fixup_bus(struct pci_bus *bus)
** P2PB's only have 2 BARs, no IRQs.
** I'd like to just ignore them for now.
*/
if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI)
if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
pcibios_init_bridge(dev);
continue;
}
/* null out the ROM resource if there is one (we don't
* care about an expansion rom on parisc, since it

4
drivers/parisc/lba_pci.c
View file

@ -790,8 +790,10 @@ lba_fixup_bus(struct pci_bus *bus)
/*
** P2PB's have no IRQs. ignore them.
*/
if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI)
if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
pcibios_init_bridge(dev);
continue;
}
/* Adjust INTERRUPT_LINE for this dev */
iosapic_fixup_irq(ldev->iosapic_obj, dev);