ALSA: PCI168 snd-azt3328: some more fixups
- fix problem with codec register 0x6a being write-only by adding a software shadow register (caused annoying noise after module loading due to _toggling_ between gameport and audio bits instead of configuring them properly) - rename several "Wave" mixer controls to "PCM", since this is what Wine and several other apps are looking for (IOW, _requiring_) and this is what AC97 specs use as naming, too, thus I'd guess it's what these controls are - cleanup, small optimizations Signed-off-by: Andreas Mohr <andi@lisas.de> Signed-off-by: Takashi Iwai <tiwai@suse.de> Signed-off-by: Jaroslav Kysela <perex@perex.cz>
This commit is contained in:
Andreas Mohr
Jaroslav Kysela
parent
981bcead3f
commit
627d3e7abc
2 changed files with 76 additions and 49 deletions
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@ -289,6 +289,12 @@ struct snd_azf3328 {
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struct pci_dev *pci;
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int irq;
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/* register 0x6a is write-only, thus need to remember setting.
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* If we need to add more registers here, then we might try to fold this
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* into some transparent combined shadow register handling with
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* CONFIG_PM register storage below, but that's slightly difficult. */
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u16 shadow_reg_codec_6AH;
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#ifdef CONFIG_PM
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/* register value containers for power management
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* Note: not always full I/O range preserved (just like Win driver!) */
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@ -324,21 +330,6 @@ snd_azf3328_io_reg_setb(unsigned reg, u8 mask, int do_set)
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return 0;
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}
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static int
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snd_azf3328_io_reg_setw(unsigned reg, u16 mask, int do_set)
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{
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u16 prev = inw(reg), new;
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new = (do_set) ? (prev|mask) : (prev & ~mask);
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/* we need to always write the new value no matter whether it differs
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* or not, since some register bits don't indicate their setting */
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outw(new, reg);
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if (new != prev)
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return 1;
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return 0;
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}
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static inline void
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snd_azf3328_codec_outb(const struct snd_azf3328 *chip, unsigned reg, u8 value)
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{
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@ -662,7 +653,7 @@ snd_azf3328_info_mixer_enum(struct snd_kcontrol *kcontrol,
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"pre 3D", "post 3D"
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};
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struct azf3328_mixer_reg reg;
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const char *p = NULL;
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const char * const *p = NULL;
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snd_azf3328_mixer_reg_decode(®, kcontrol->private_value);
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uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
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@ -673,20 +664,20 @@ snd_azf3328_info_mixer_enum(struct snd_kcontrol *kcontrol,
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if (reg.reg == IDX_MIXER_ADVCTL2) {
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switch(reg.lchan_shift) {
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case 8: /* modem out sel */
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p = texts1[uinfo->value.enumerated.item];
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p = texts1;
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break;
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case 9: /* mono sel source */
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p = texts2[uinfo->value.enumerated.item];
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p = texts2;
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break;
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case 15: /* PCM Out Path */
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p = texts4[uinfo->value.enumerated.item];
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p = texts4;
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break;
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}
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} else
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if (reg.reg == IDX_MIXER_REC_SELECT)
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p = texts3[uinfo->value.enumerated.item];
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p = texts3;
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strcpy(uinfo->value.enumerated.name, p);
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strcpy(uinfo->value.enumerated.name, p[uinfo->value.enumerated.item]);
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return 0;
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}
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@ -745,9 +736,11 @@ snd_azf3328_put_mixer_enum(struct snd_kcontrol *kcontrol,
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static struct snd_kcontrol_new snd_azf3328_mixer_controls[] __devinitdata = {
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AZF3328_MIXER_SWITCH("Master Playback Switch", IDX_MIXER_PLAY_MASTER, 15, 1),
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AZF3328_MIXER_VOL_STEREO("Master Playback Volume", IDX_MIXER_PLAY_MASTER, 0x1f, 1),
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AZF3328_MIXER_SWITCH("Wave Playback Switch", IDX_MIXER_WAVEOUT, 15, 1),
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AZF3328_MIXER_VOL_STEREO("Wave Playback Volume", IDX_MIXER_WAVEOUT, 0x1f, 1),
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AZF3328_MIXER_SWITCH("Wave 3D Bypass Playback Switch", IDX_MIXER_ADVCTL2, 7, 1),
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AZF3328_MIXER_SWITCH("PCM Playback Switch", IDX_MIXER_WAVEOUT, 15, 1),
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AZF3328_MIXER_VOL_STEREO("PCM Playback Volume",
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IDX_MIXER_WAVEOUT, 0x1f, 1),
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AZF3328_MIXER_SWITCH("PCM 3D Bypass Playback Switch",
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IDX_MIXER_ADVCTL2, 7, 1),
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AZF3328_MIXER_SWITCH("FM Playback Switch", IDX_MIXER_FMSYNTH, 15, 1),
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AZF3328_MIXER_VOL_STEREO("FM Playback Volume", IDX_MIXER_FMSYNTH, 0x1f, 1),
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AZF3328_MIXER_SWITCH("CD Playback Switch", IDX_MIXER_CDAUDIO, 15, 1),
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@ -874,7 +867,7 @@ snd_azf3328_hw_free(struct snd_pcm_substream *substream)
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static void
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snd_azf3328_codec_setfmt(struct snd_azf3328 *chip,
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unsigned reg,
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unsigned int bitrate,
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enum azf_freq_t bitrate,
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unsigned int format_width,
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unsigned int channels
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)
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@ -958,15 +951,29 @@ snd_azf3328_codec_setfmt_lowpower(struct snd_azf3328 *chip,
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snd_azf3328_codec_setfmt(chip, reg, AZF_FREQ_4000, 8, 1);
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}
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static void
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snd_azf3328_codec_reg_6AH_update(struct snd_azf3328 *chip,
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unsigned bitmask,
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int enable
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)
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{
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if (enable)
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chip->shadow_reg_codec_6AH &= ~bitmask;
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else
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chip->shadow_reg_codec_6AH |= bitmask;
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snd_azf3328_dbgplay("6AH_update mask 0x%04x enable %d: val 0x%04x\n",
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bitmask, enable, chip->shadow_reg_codec_6AH);
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snd_azf3328_codec_outw(chip, IDX_IO_6AH, chip->shadow_reg_codec_6AH);
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}
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static inline void
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snd_azf3328_codec_enable(struct snd_azf3328 *chip, int enable)
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{
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snd_azf3328_dbgplay("codec_enable %d\n", enable);
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/* no idea what exactly is being done here, but I strongly assume it's
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* PM related */
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snd_azf3328_io_reg_setw(
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chip->codec_io+IDX_IO_6AH,
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IO_6A_PAUSE_PLAYBACK_BIT8,
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!enable
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snd_azf3328_codec_reg_6AH_update(
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chip, IO_6A_PAUSE_PLAYBACK_BIT8, enable
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);
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}
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@ -1404,10 +1411,8 @@ snd_azf3328_gameport_legacy_address_enable(struct snd_azf3328 *chip, int enable)
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static inline void
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snd_azf3328_gameport_axis_circuit_enable(struct snd_azf3328 *chip, int enable)
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{
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snd_azf3328_io_reg_setw(
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chip->codec_io+IDX_IO_6AH,
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IO_6A_SOMETHING2_GAMEPORT,
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!enable
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snd_azf3328_codec_reg_6AH_update(
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chip, IO_6A_SOMETHING2_GAMEPORT, enable
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);
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}
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@ -1525,8 +1530,6 @@ snd_azf3328_gameport(struct snd_azf3328 *chip, int dev)
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{
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struct gameport *gp;
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int io_port = chip->game_io;
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chip->gameport = gp = gameport_allocate_port();
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if (!gp) {
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printk(KERN_ERR "azt3328: cannot alloc memory for gameport\n");
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@ -1536,7 +1539,7 @@ snd_azf3328_gameport(struct snd_azf3328 *chip, int dev)
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gameport_set_name(gp, "AZF3328 Gameport");
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gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci));
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gameport_set_dev_parent(gp, &chip->pci->dev);
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gp->io = io_port;
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gp->io = chip->game_io;
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gameport_set_port_data(gp, chip);
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gp->open = snd_azf3328_gameport_open;
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@ -1577,6 +1580,15 @@ snd_azf3328_gameport_interrupt(struct snd_azf3328 *chip)
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/******************************************************************/
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static inline void
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snd_azf3328_irq_log_unknown_type(u8 which)
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{
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snd_azf3328_dbgplay(
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"azt3328: unknown IRQ type (%x) occurred, please report!\n",
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which
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);
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}
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static irqreturn_t
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snd_azf3328_interrupt(int irq, void *dev_id)
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{
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@ -1594,11 +1606,14 @@ snd_azf3328_interrupt(int irq, void *dev_id)
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))
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return IRQ_NONE; /* must be interrupt for another device */
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snd_azf3328_dbgplay("Interrupt %ld!\nIDX_IO_PLAY_FLAGS %04x, IDX_IO_PLAY_IRQTYPE %04x, IDX_IO_IRQSTATUS %04x\n",
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irq_count++ /* debug-only */,
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snd_azf3328_codec_inw(chip, IDX_IO_PLAY_FLAGS),
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snd_azf3328_codec_inw(chip, IDX_IO_PLAY_IRQTYPE),
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status);
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snd_azf3328_dbgplay(
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"irq_count %ld! IDX_IO_PLAY_FLAGS %04x, "
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"IDX_IO_PLAY_IRQTYPE %04x, IDX_IO_IRQSTATUS %04x\n",
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irq_count++ /* debug-only */,
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snd_azf3328_codec_inw(chip, IDX_IO_PLAY_FLAGS),
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snd_azf3328_codec_inw(chip, IDX_IO_PLAY_IRQTYPE),
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status
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);
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if (status & IRQ_TIMER) {
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/* snd_azf3328_dbgplay("timer %ld\n",
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@ -1631,9 +1646,9 @@ snd_azf3328_interrupt(int irq, void *dev_id)
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)
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);
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} else
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snd_azf3328_dbgplay("azt3328: ouch, irq handler problem!\n");
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printk(KERN_WARNING "azt3328: irq handler problem!\n");
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if (which & IRQ_PLAY_SOMETHING)
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snd_azf3328_dbgplay("azt3328: unknown play IRQ type occurred, please report!\n");
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snd_azf3328_irq_log_unknown_type(which);
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}
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if (status & IRQ_RECORDING) {
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spin_lock(&chip->reg_lock);
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@ -1653,9 +1668,9 @@ snd_azf3328_interrupt(int irq, void *dev_id)
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)
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);
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} else
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snd_azf3328_dbgplay("azt3328: ouch, irq handler problem!\n");
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printk(KERN_WARNING "azt3328: irq handler problem!\n");
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if (which & IRQ_REC_SOMETHING)
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snd_azf3328_dbgplay("azt3328: unknown rec IRQ type occurred, please report!\n");
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snd_azf3328_irq_log_unknown_type(which);
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}
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if (status & IRQ_GAMEPORT)
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snd_azf3328_gameport_interrupt(chip);
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@ -2311,6 +2326,10 @@ snd_azf3328_suspend(struct pci_dev *pci, pm_message_t state)
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for (reg = 0; reg < AZF_IO_SIZE_CODEC_PM / 2; ++reg)
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chip->saved_regs_codec[reg] = inw(chip->codec_io + reg * 2);
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/* manually store the one currently relevant write-only reg, too */
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chip->saved_regs_codec[IDX_IO_6AH / 2] = chip->shadow_reg_codec_6AH;
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for (reg = 0; reg < AZF_IO_SIZE_GAME_PM / 2; ++reg)
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chip->saved_regs_game[reg] = inw(chip->game_io + reg * 2);
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for (reg = 0; reg < AZF_IO_SIZE_MPU_PM / 2; ++reg)
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@ -1,7 +1,8 @@
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#ifndef __SOUND_AZT3328_H
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#define __SOUND_AZT3328_H
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/* "PU" == "power-up value", as tested on PCI168 PCI rev. 10 */
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/* "PU" == "power-up value", as tested on PCI168 PCI rev. 10
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* "WRITE_ONLY" == register does not indicate actual bit values */
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/*** main I/O area port indices ***/
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/* (only 0x70 of 0x80 bytes saved/restored by Windows driver) */
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@ -76,7 +77,7 @@
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#define SOUNDFORMAT_FLAG_2CHANNELS 0x0020
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/* define frequency helpers, for maximum value safety */
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enum {
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enum azf_freq_t {
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#define AZF_FREQ(rate) AZF_FREQ_##rate = rate
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AZF_FREQ(4000),
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AZF_FREQ(4800),
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@ -150,11 +151,18 @@ enum {
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#define IO_68_RANDOM_TOGGLE1 0x0100 /* toggles randomly */
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#define IO_68_RANDOM_TOGGLE2 0x0200 /* toggles randomly */
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/* umm, nope, behaviour of these bits changes depending on what we wrote
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* to 0x6b!! */
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* to 0x6b!!
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* And they change upon playback/stop, too:
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* Writing a value to 0x68 will display this exact value during playback,
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* too but when stopped it can fall back to a rather different
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* seemingly random value). Hmm, possibly this is a register which
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* has a remote shadow which needs proper device supply which only exists
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* in case playback is active? Or is this driver-induced?
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*/
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/* this WORD can be set to have bits 0x0028 activated (FIXME: correct??);
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* actually inhibits PCM playback!!! maybe power management??: */
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#define IDX_IO_6AH 0x6A
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#define IDX_IO_6AH 0x6A /* WRITE_ONLY! */
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/* bit 5: enabling this will activate permanent counting of bytes 2/3
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* at gameport I/O (0xb402/3) (equal values each) and cause
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* gameport legacy I/O at 0x0200 to be _DISABLED_!
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