clk: hisilicon: add hi3620_mmc_clks
Suggest by Arnd: abstract mmc tuning as clock behavior, also because different soc have different tuning method and registers. hi3620_mmc_clks is added to handle mmc clock specifically on hi3620. Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
This commit is contained in:
Zhangfei Gao
Mike Turquette
parent
b89cd950cb
commit
62ac983b61
4 changed files with 294 additions and 0 deletions
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@ -30,3 +30,17 @@ Example:
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resume-offset = <0x308>;
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reboot-offset = <0x4>;
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};
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PCTRL: Peripheral misc control register
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Required Properties:
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- compatible: "hisilicon,pctrl"
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- reg: Address and size of pctrl.
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Example:
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/* for Hi3620 */
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pctrl: pctrl@fca09000 {
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compatible = "hisilicon,pctrl";
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reg = <0xfca09000 0x1000>;
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};
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@ -7,6 +7,7 @@ Required Properties:
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- compatible: should be one of the following.
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- "hisilicon,hi3620-clock" - controller compatible with Hi3620 SoC.
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- "hisilicon,hi3620-mmc-clock" - controller specific for Hi3620 mmc.
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- reg: physical base address of the controller and length of memory mapped
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region.
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@ -240,3 +240,277 @@ static void __init hi3620_clk_init(struct device_node *np)
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base);
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}
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CLK_OF_DECLARE(hi3620_clk, "hisilicon,hi3620-clock", hi3620_clk_init);
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struct hisi_mmc_clock {
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unsigned int id;
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const char *name;
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const char *parent_name;
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unsigned long flags;
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u32 clken_reg;
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u32 clken_bit;
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u32 div_reg;
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u32 div_off;
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u32 div_bits;
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u32 drv_reg;
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u32 drv_off;
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u32 drv_bits;
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u32 sam_reg;
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u32 sam_off;
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u32 sam_bits;
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};
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struct clk_mmc {
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struct clk_hw hw;
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u32 id;
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void __iomem *clken_reg;
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u32 clken_bit;
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void __iomem *div_reg;
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u32 div_off;
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u32 div_bits;
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void __iomem *drv_reg;
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u32 drv_off;
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u32 drv_bits;
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void __iomem *sam_reg;
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u32 sam_off;
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u32 sam_bits;
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};
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#define to_mmc(_hw) container_of(_hw, struct clk_mmc, hw)
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static struct hisi_mmc_clock hi3620_mmc_clks[] __initdata = {
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{ HI3620_SD_CIUCLK, "sd_bclk1", "sd_clk", CLK_SET_RATE_PARENT, 0x1f8, 0, 0x1f8, 1, 3, 0x1f8, 4, 4, 0x1f8, 8, 4},
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{ HI3620_MMC_CIUCLK1, "mmc_bclk1", "mmc_clk1", CLK_SET_RATE_PARENT, 0x1f8, 12, 0x1f8, 13, 3, 0x1f8, 16, 4, 0x1f8, 20, 4},
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{ HI3620_MMC_CIUCLK2, "mmc_bclk2", "mmc_clk2", CLK_SET_RATE_PARENT, 0x1f8, 24, 0x1f8, 25, 3, 0x1f8, 28, 4, 0x1fc, 0, 4},
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{ HI3620_MMC_CIUCLK3, "mmc_bclk3", "mmc_clk3", CLK_SET_RATE_PARENT, 0x1fc, 4, 0x1fc, 5, 3, 0x1fc, 8, 4, 0x1fc, 12, 4},
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};
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static unsigned long mmc_clk_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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switch (parent_rate) {
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case 26000000:
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return 13000000;
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case 180000000:
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return 25000000;
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case 360000000:
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return 50000000;
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case 720000000:
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return 100000000;
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case 1440000000:
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return 180000000;
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default:
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return parent_rate;
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}
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}
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static long mmc_clk_determine_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *best_parent_rate,
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struct clk **best_parent_p)
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{
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struct clk_mmc *mclk = to_mmc(hw);
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unsigned long best = 0;
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if ((rate <= 13000000) && (mclk->id == HI3620_MMC_CIUCLK1)) {
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rate = 13000000;
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best = 26000000;
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} else if (rate <= 26000000) {
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rate = 25000000;
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best = 180000000;
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} else if (rate <= 52000000) {
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rate = 50000000;
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best = 360000000;
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} else if (rate <= 100000000) {
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rate = 100000000;
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best = 720000000;
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} else {
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/* max is 180M */
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rate = 180000000;
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best = 1440000000;
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}
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*best_parent_rate = best;
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return rate;
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}
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static u32 mmc_clk_delay(u32 val, u32 para, u32 off, u32 len)
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{
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u32 i;
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if (para >= 0) {
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for (i = 0; i < len; i++) {
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if (para % 2)
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val |= 1 << (off + i);
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else
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val &= ~(1 << (off + i));
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para = para >> 1;
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}
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}
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return val;
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}
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static int mmc_clk_set_timing(struct clk_hw *hw, unsigned long rate)
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{
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struct clk_mmc *mclk = to_mmc(hw);
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unsigned long flags;
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u32 sam, drv, div, val;
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static DEFINE_SPINLOCK(mmc_clk_lock);
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switch (rate) {
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case 13000000:
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sam = 3;
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drv = 1;
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div = 1;
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break;
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case 25000000:
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sam = 13;
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drv = 6;
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div = 6;
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break;
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case 50000000:
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sam = 3;
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drv = 6;
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div = 6;
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break;
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case 100000000:
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sam = 6;
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drv = 4;
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div = 6;
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break;
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case 180000000:
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sam = 6;
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drv = 4;
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div = 7;
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break;
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default:
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return -EINVAL;
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}
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spin_lock_irqsave(&mmc_clk_lock, flags);
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val = readl_relaxed(mclk->clken_reg);
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val &= ~(1 << mclk->clken_bit);
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writel_relaxed(val, mclk->clken_reg);
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val = readl_relaxed(mclk->sam_reg);
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val = mmc_clk_delay(val, sam, mclk->sam_off, mclk->sam_bits);
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writel_relaxed(val, mclk->sam_reg);
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val = readl_relaxed(mclk->drv_reg);
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val = mmc_clk_delay(val, drv, mclk->drv_off, mclk->drv_bits);
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writel_relaxed(val, mclk->drv_reg);
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val = readl_relaxed(mclk->div_reg);
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val = mmc_clk_delay(val, div, mclk->div_off, mclk->div_bits);
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writel_relaxed(val, mclk->div_reg);
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val = readl_relaxed(mclk->clken_reg);
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val |= 1 << mclk->clken_bit;
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writel_relaxed(val, mclk->clken_reg);
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spin_unlock_irqrestore(&mmc_clk_lock, flags);
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return 0;
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}
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static int mmc_clk_prepare(struct clk_hw *hw)
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{
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struct clk_mmc *mclk = to_mmc(hw);
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unsigned long rate;
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if (mclk->id == HI3620_MMC_CIUCLK1)
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rate = 13000000;
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else
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rate = 25000000;
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return mmc_clk_set_timing(hw, rate);
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}
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static int mmc_clk_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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return mmc_clk_set_timing(hw, rate);
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}
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static struct clk_ops clk_mmc_ops = {
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.prepare = mmc_clk_prepare,
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.determine_rate = mmc_clk_determine_rate,
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.set_rate = mmc_clk_set_rate,
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.recalc_rate = mmc_clk_recalc_rate,
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};
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static struct clk *hisi_register_clk_mmc(struct hisi_mmc_clock *mmc_clk,
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void __iomem *base, struct device_node *np)
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{
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struct clk_mmc *mclk;
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struct clk *clk;
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struct clk_init_data init;
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mclk = kzalloc(sizeof(*mclk), GFP_KERNEL);
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if (!mclk) {
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pr_err("%s: fail to allocate mmc clk\n", __func__);
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return ERR_PTR(-ENOMEM);
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}
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init.name = mmc_clk->name;
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init.ops = &clk_mmc_ops;
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init.flags = mmc_clk->flags | CLK_IS_BASIC;
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init.parent_names = (mmc_clk->parent_name ? &mmc_clk->parent_name : NULL);
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init.num_parents = (mmc_clk->parent_name ? 1 : 0);
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mclk->hw.init = &init;
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mclk->id = mmc_clk->id;
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mclk->clken_reg = base + mmc_clk->clken_reg;
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mclk->clken_bit = mmc_clk->clken_bit;
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mclk->div_reg = base + mmc_clk->div_reg;
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mclk->div_off = mmc_clk->div_off;
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mclk->div_bits = mmc_clk->div_bits;
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mclk->drv_reg = base + mmc_clk->drv_reg;
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mclk->drv_off = mmc_clk->drv_off;
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mclk->drv_bits = mmc_clk->drv_bits;
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mclk->sam_reg = base + mmc_clk->sam_reg;
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mclk->sam_off = mmc_clk->sam_off;
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mclk->sam_bits = mmc_clk->sam_bits;
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clk = clk_register(NULL, &mclk->hw);
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if (WARN_ON(IS_ERR(clk)))
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kfree(mclk);
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return clk;
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}
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static void __init hi3620_mmc_clk_init(struct device_node *node)
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{
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void __iomem *base;
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int i, num = ARRAY_SIZE(hi3620_mmc_clks);
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struct clk_onecell_data *clk_data;
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if (!node) {
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pr_err("failed to find pctrl node in DTS\n");
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return;
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}
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base = of_iomap(node, 0);
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if (!base) {
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pr_err("failed to map pctrl\n");
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return;
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}
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clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
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if (WARN_ON(!clk_data))
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return;
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clk_data->clks = kzalloc(sizeof(struct clk *) * num, GFP_KERNEL);
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if (!clk_data->clks) {
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pr_err("%s: fail to allocate mmc clk\n", __func__);
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return;
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}
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for (i = 0; i < num; i++) {
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struct hisi_mmc_clock *mmc_clk = &hi3620_mmc_clks[i];
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clk_data->clks[mmc_clk->id] =
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hisi_register_clk_mmc(mmc_clk, base, node);
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}
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clk_data->clk_num = num;
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of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
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}
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CLK_OF_DECLARE(hi3620_mmc_clk, "hisilicon,hi3620-mmc-clock", hi3620_mmc_clk_init);
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@ -147,6 +147,11 @@
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#define HI3620_MMC_CLK3 217
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#define HI3620_MCU_CLK 218
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#define HI3620_SD_CIUCLK 0
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#define HI3620_MMC_CIUCLK1 1
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#define HI3620_MMC_CIUCLK2 2
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#define HI3620_MMC_CIUCLK3 3
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#define HI3620_NR_CLKS 219
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#endif /* __DTS_HI3620_CLOCK_H */
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