drm/amdgpu: add an INFO query for monitoring VRAM CPU page faults
v2: bump the DRM version Signed-off-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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5 changed files with 9 additions and 1 deletions
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@ -1529,6 +1529,7 @@ struct amdgpu_device {
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atomic64_t gtt_usage;
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atomic64_t num_bytes_moved;
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atomic64_t num_evictions;
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atomic64_t num_vram_cpu_page_faults;
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atomic_t gpu_reset_counter;
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atomic_t vram_lost_counter;
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@ -66,9 +66,10 @@
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* - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality
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* - 3.15.0 - Export more gpu info for gfx9
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* - 3.16.0 - Add reserved vmid support
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* - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS.
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*/
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#define KMS_DRIVER_MAJOR 3
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#define KMS_DRIVER_MINOR 16
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#define KMS_DRIVER_MINOR 17
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#define KMS_DRIVER_PATCHLEVEL 0
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int amdgpu_vram_limit = 0;
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@ -417,6 +417,9 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
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case AMDGPU_INFO_NUM_EVICTIONS:
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ui64 = atomic64_read(&adev->num_evictions);
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return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
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case AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS:
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ui64 = atomic64_read(&adev->num_vram_cpu_page_faults);
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return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
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case AMDGPU_INFO_VRAM_USAGE:
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ui64 = atomic64_read(&adev->vram_usage);
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return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
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@ -960,6 +960,7 @@ int amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
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return -EINVAL;
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/* hurrah the memory is not visible ! */
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atomic64_inc(&adev->num_vram_cpu_page_faults);
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amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM);
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lpfn = adev->mc.visible_vram_size >> PAGE_SHIFT;
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for (i = 0; i < abo->placement.num_placement; i++) {
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@ -603,6 +603,8 @@ struct drm_amdgpu_cs_chunk_data {
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#define AMDGPU_INFO_SENSOR_VDDNB 0x6
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/* Subquery id: Query graphics voltage */
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#define AMDGPU_INFO_SENSOR_VDDGFX 0x7
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/* Number of VRAM page faults on CPU access. */
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#define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E
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#define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0
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#define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff
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