mmc: dw_mmc: exynos: configure SMU in exynos5420
Exynos5420 Mobile Storage Host controller has Security Management Unit (SMU) for channel 0 and channel 1 (mainly for eMMC). This time, SMU configuration is set for non-encryption mode. Signed-off-by: Yuvaraj Kumar C D <yuvaraj.cd@samsung.com> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Tested-by: Jaehoon Chung <jh80.chung@samsung.com> Acked-by: Seungwon Jeon <tgih.jun@samsung.com> Signed-off-by: Chris Ball <cjb@laptop.org>
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1 changed files with 37 additions and 1 deletions
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@ -35,12 +35,32 @@
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#define EXYNOS4210_FIXED_CIU_CLK_DIV 2
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#define EXYNOS4210_FIXED_CIU_CLK_DIV 2
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#define EXYNOS4412_FIXED_CIU_CLK_DIV 4
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#define EXYNOS4412_FIXED_CIU_CLK_DIV 4
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/* Block number in eMMC */
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#define DWMCI_BLOCK_NUM 0xFFFFFFFF
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#define SDMMC_EMMCP_BASE 0x1000
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#define SDMMC_MPSECURITY (SDMMC_EMMCP_BASE + 0x0010)
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#define SDMMC_MPSBEGIN0 (SDMMC_EMMCP_BASE + 0x0200)
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#define SDMMC_MPSEND0 (SDMMC_EMMCP_BASE + 0x0204)
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#define SDMMC_MPSCTRL0 (SDMMC_EMMCP_BASE + 0x020C)
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/* SMU control bits */
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#define DWMCI_MPSCTRL_SECURE_READ_BIT BIT(7)
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#define DWMCI_MPSCTRL_SECURE_WRITE_BIT BIT(6)
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#define DWMCI_MPSCTRL_NON_SECURE_READ_BIT BIT(5)
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#define DWMCI_MPSCTRL_NON_SECURE_WRITE_BIT BIT(4)
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#define DWMCI_MPSCTRL_USE_FUSE_KEY BIT(3)
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#define DWMCI_MPSCTRL_ECB_MODE BIT(2)
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#define DWMCI_MPSCTRL_ENCRYPTION BIT(1)
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#define DWMCI_MPSCTRL_VALID BIT(0)
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/* Variations in Exynos specific dw-mshc controller */
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/* Variations in Exynos specific dw-mshc controller */
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enum dw_mci_exynos_type {
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enum dw_mci_exynos_type {
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DW_MCI_TYPE_EXYNOS4210,
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DW_MCI_TYPE_EXYNOS4210,
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DW_MCI_TYPE_EXYNOS4412,
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DW_MCI_TYPE_EXYNOS4412,
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DW_MCI_TYPE_EXYNOS5250,
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DW_MCI_TYPE_EXYNOS5250,
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DW_MCI_TYPE_EXYNOS5420,
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DW_MCI_TYPE_EXYNOS5420,
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DW_MCI_TYPE_EXYNOS5420_SMU,
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};
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};
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/* Exynos implementation specific driver private data */
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/* Exynos implementation specific driver private data */
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@ -67,6 +87,9 @@ static struct dw_mci_exynos_compatible {
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}, {
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}, {
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.compatible = "samsung,exynos5420-dw-mshc",
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.compatible = "samsung,exynos5420-dw-mshc",
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.ctrl_type = DW_MCI_TYPE_EXYNOS5420,
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.ctrl_type = DW_MCI_TYPE_EXYNOS5420,
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}, {
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.compatible = "samsung,exynos5420-dw-mshc-smu",
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.ctrl_type = DW_MCI_TYPE_EXYNOS5420_SMU,
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},
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},
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};
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};
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@ -74,6 +97,15 @@ static int dw_mci_exynos_priv_init(struct dw_mci *host)
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{
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{
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struct dw_mci_exynos_priv_data *priv = host->priv;
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struct dw_mci_exynos_priv_data *priv = host->priv;
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if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS5420_SMU) {
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mci_writel(host, MPSBEGIN0, 0);
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mci_writel(host, MPSEND0, DWMCI_BLOCK_NUM);
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mci_writel(host, MPSCTRL0, DWMCI_MPSCTRL_SECURE_WRITE_BIT |
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DWMCI_MPSCTRL_NON_SECURE_READ_BIT |
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DWMCI_MPSCTRL_VALID |
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DWMCI_MPSCTRL_NON_SECURE_WRITE_BIT);
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}
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return 0;
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return 0;
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}
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}
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@ -82,7 +114,8 @@ static int dw_mci_exynos_setup_clock(struct dw_mci *host)
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struct dw_mci_exynos_priv_data *priv = host->priv;
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struct dw_mci_exynos_priv_data *priv = host->priv;
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if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS5250 ||
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if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS5250 ||
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priv->ctrl_type == DW_MCI_TYPE_EXYNOS5420)
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priv->ctrl_type == DW_MCI_TYPE_EXYNOS5420 ||
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priv->ctrl_type == DW_MCI_TYPE_EXYNOS5420_SMU)
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host->bus_hz /= (priv->ciu_div + 1);
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host->bus_hz /= (priv->ciu_div + 1);
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else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4412)
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else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4412)
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host->bus_hz /= EXYNOS4412_FIXED_CIU_CLK_DIV;
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host->bus_hz /= EXYNOS4412_FIXED_CIU_CLK_DIV;
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@ -104,6 +137,7 @@ static int dw_mci_exynos_resume(struct device *dev)
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{
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{
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struct dw_mci *host = dev_get_drvdata(dev);
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struct dw_mci *host = dev_get_drvdata(dev);
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dw_mci_exynos_priv_init(host);
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return dw_mci_resume(host);
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return dw_mci_resume(host);
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}
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}
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@ -222,6 +256,8 @@ static const struct of_device_id dw_mci_exynos_match[] = {
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.data = &exynos_drv_data, },
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.data = &exynos_drv_data, },
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{ .compatible = "samsung,exynos5420-dw-mshc",
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{ .compatible = "samsung,exynos5420-dw-mshc",
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.data = &exynos_drv_data, },
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.data = &exynos_drv_data, },
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{ .compatible = "samsung,exynos5420-dw-mshc-smu",
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.data = &exynos_drv_data, },
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{},
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{},
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};
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};
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MODULE_DEVICE_TABLE(of, dw_mci_exynos_match);
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MODULE_DEVICE_TABLE(of, dw_mci_exynos_match);
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