staging: ft1000: Fix line over 80 characters.
Fix checkpatch.pl issues with line over 80 characters in ft1000.h Signed-off-by: Gulsah Kose <gulsah.1004@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Gulsah Kose
Greg Kroah-Hartman
parent
8e3a3ce66e
commit
6d56be08f7
1 changed files with 117 additions and 39 deletions
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@ -21,34 +21,64 @@
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#define FT1000_REG_SUP_CTRL 0x0020 /* HCTR - Host Control Register */
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#define FT1000_REG_SUP_STAT 0x0022 /* HSTAT - Host Status Register */
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#define FT1000_REG_RESET 0x0024 /* HCTR - Host Control Register */
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#define FT1000_REG_SUP_ISR 0x0026 /* HISR - Host Interrupt Status Register */
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#define FT1000_REG_SUP_ISR 0x0026 /* HISR - Host Interrupt Status
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* Register
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*/
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#define FT1000_REG_SUP_IMASK 0x0028 /* HIMASK - Host Interrupt Mask */
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#define FT1000_REG_DOORBELL 0x002a /* DBELL - Door Bell Register */
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#define FT1000_REG_ASIC_ID 0x002e /* ASICID - ASIC Identification Number */
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#define FT1000_REG_ASIC_ID 0x002e /* ASICID - ASIC Identification
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* Number
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*/
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/* MEMORY MAP FOR ELECTRABUZZ ASIC */
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#define FT1000_REG_UFIFO_STAT 0x0000 /* UFSR - Uplink FIFO status register */
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#define FT1000_REG_UFIFO_BEG 0x0002 /* UFBR - Uplink FIFO beginning register */
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#define FT1000_REG_UFIFO_BEG 0x0002 /* UFBR - Uplink FIFO beginning
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* register
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*/
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#define FT1000_REG_UFIFO_MID 0x0004 /* UFMR - Uplink FIFO middle register */
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#define FT1000_REG_UFIFO_END 0x0006 /* UFER - Uplink FIFO end register */
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#define FT1000_REG_DFIFO_STAT 0x0008 /* DFSR - Downlink FIFO status register */
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#define FT1000_REG_DFIFO_STAT 0x0008 /* DFSR - Downlink FIFO status
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* register
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*/
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#define FT1000_REG_DFIFO 0x000A /* DFR - Downlink FIFO Register */
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#define FT1000_REG_DPRAM_DATA 0x000C /* DPRAM - Dual Port Indirect Data Register */
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#define FT1000_REG_DPRAM_DATA 0x000C /* DPRAM - Dual Port Indirect
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* Data Register
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*/
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#define FT1000_REG_WATERMARK 0x0010 /* WMARK - Watermark Register */
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/* MEMORY MAP FOR MAGNEMITE */
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#define FT1000_REG_MAG_UFDR 0x0000 /* UFDR - Uplink FIFO Data Register (32-bits) */
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#define FT1000_REG_MAG_UFDRL 0x0000 /* UFDRL - Uplink FIFO Data Register low-word (16-bits) */
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#define FT1000_REG_MAG_UFDRH 0x0002 /* UFDRH - Uplink FIFO Data Register high-word (16-bits) */
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#define FT1000_REG_MAG_UFDR 0x0000 /* UFDR - Uplink FIFO Data
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* Register (32-bits)
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*/
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#define FT1000_REG_MAG_UFDRL 0x0000 /* UFDRL - Uplink FIFO Data
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* Register low-word (16-bits)
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*/
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#define FT1000_REG_MAG_UFDRH 0x0002 /* UFDRH - Uplink FIFO Data Register
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* high-word (16-bits)
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*/
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#define FT1000_REG_MAG_UFER 0x0004 /* UFER - Uplink FIFO End Register */
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#define FT1000_REG_MAG_UFSR 0x0006 /* UFSR - Uplink FIFO Status Register */
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#define FT1000_REG_MAG_DFR 0x0008 /* DFR - Downlink FIFO Register (32-bits) */
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#define FT1000_REG_MAG_DFRL 0x0008 /* DFRL - Downlink FIFO Register low-word (16-bits) */
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#define FT1000_REG_MAG_DFRH 0x000a /* DFRH - Downlink FIFO Register high-word (16-bits) */
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#define FT1000_REG_MAG_DFSR 0x000c /* DFSR - Downlink FIFO Status Register */
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#define FT1000_REG_MAG_DPDATA 0x0010 /* DPDATA - Dual Port RAM Indirect Data Register (32-bits) */
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#define FT1000_REG_MAG_DPDATAL 0x0010 /* DPDATAL - Dual Port RAM Indirect Data Register low-word (16-bits) */
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#define FT1000_REG_MAG_DPDATAH 0x0012 /* DPDATAH - Dual Port RAM Indirect Data Register high-word (16-bits) */
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#define FT1000_REG_MAG_DFR 0x0008 /* DFR - Downlink FIFO Register
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* (32-bits)
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*/
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#define FT1000_REG_MAG_DFRL 0x0008 /* DFRL - Downlink FIFO Register
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* low-word (16-bits)
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*/
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#define FT1000_REG_MAG_DFRH 0x000a /* DFRH - Downlink FIFO Register
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* high-word (16-bits)
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*/
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#define FT1000_REG_MAG_DFSR 0x000c /* DFSR - Downlink FIFO Status
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* Register
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*/
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#define FT1000_REG_MAG_DPDATA 0x0010 /* DPDATA - Dual Port RAM Indirect
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* Data Register (32-bits)
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*/
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#define FT1000_REG_MAG_DPDATAL 0x0010 /* DPDATAL - Dual Port RAM Indirect
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* Data Register low-word (16-bits)
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*/
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#define FT1000_REG_MAG_DPDATAH 0x0012 /* DPDATAH - Dual Port RAM Indirect Data
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* Register high-word (16-bits)
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*/
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#define FT1000_REG_MAG_WATERMARK 0x002c /* WMARK - Watermark Register */
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#define FT1000_REG_MAG_VERSION 0x0030 /* LLC Version */
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@ -57,7 +87,9 @@
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#define FT1000_DPRAM_RX_BASE 0x0800 /* PC Card to Host Messaging Area */
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#define FT1000_FIFO_LEN 0x07FC /* total length for DSP FIFO tracking */
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#define FT1000_HI_HO 0x07FE /* heartbeat with HI/HO */
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#define FT1000_DSP_STATUS 0x0FFE /* dsp status - non-zero is a request to reset dsp */
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#define FT1000_DSP_STATUS 0x0FFE /* dsp status - non-zero is a request
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* to reset dsp
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*/
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#define FT1000_DSP_LED 0x0FFA /* dsp led status for PAD device */
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#define FT1000_DSP_CON_STATE 0x0FF8 /* DSP Connection Status Info */
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#define FT1000_DPRAM_FEFE 0x0002 /* location for dsp ready indicator */
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@ -67,26 +99,48 @@
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#define FT1000_DSP_TIMER3 0x1FF6 /* Timer Field from Basestation */
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/* Reserved Dual Port RAM offsets for Magnemite */
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#define FT1000_DPRAM_MAG_TX_BASE 0x0000 /* Host to PC Card Messaging Area */
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#define FT1000_DPRAM_MAG_RX_BASE 0x0200 /* PC Card to Host Messaging Area */
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#define FT1000_DPRAM_MAG_TX_BASE 0x0000 /* Host to PC Card
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* Messaging Area
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*/
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#define FT1000_DPRAM_MAG_RX_BASE 0x0200 /* PC Card to Host
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* Messaging Area
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*/
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#define FT1000_MAG_FIFO_LEN 0x1FF /* total length for DSP FIFO tracking */
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#define FT1000_MAG_FIFO_LEN 0x1FF /* total length for DSP
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* FIFO tracking
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*/
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#define FT1000_MAG_FIFO_LEN_INDX 0x1 /* low-word index */
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#define FT1000_MAG_HI_HO 0x1FF /* heartbeat with HI/HO */
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#define FT1000_MAG_HI_HO_INDX 0x0 /* high-word index */
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#define FT1000_MAG_DSP_LED 0x3FE /* dsp led status for PAD device */
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#define FT1000_MAG_DSP_LED_INDX 0x0 /* dsp led status for PAD device */
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#define FT1000_MAG_DSP_LED 0x3FE /* dsp led status for
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* PAD device
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*/
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#define FT1000_MAG_DSP_LED_INDX 0x0 /* dsp led status for
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* PAD device
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*/
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#define FT1000_MAG_DSP_CON_STATE 0x3FE /* DSP Connection Status Info */
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#define FT1000_MAG_DSP_CON_STATE_INDX 0x1 /* DSP Connection Status Info */
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#define FT1000_MAG_DPRAM_FEFE 0x000 /* location for dsp ready indicator */
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#define FT1000_MAG_DPRAM_FEFE_INDX 0x0 /* location for dsp ready indicator */
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#define FT1000_MAG_DSP_TIMER0 0x3FC /* Timer Field from Basestation */
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#define FT1000_MAG_DPRAM_FEFE 0x000 /* location for dsp ready
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* indicator
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*/
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#define FT1000_MAG_DPRAM_FEFE_INDX 0x0 /* location for dsp ready
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* indicator
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*/
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#define FT1000_MAG_DSP_TIMER0 0x3FC /* Timer Field from
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* Basestation
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*/
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#define FT1000_MAG_DSP_TIMER0_INDX 0x1
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#define FT1000_MAG_DSP_TIMER1 0x3FC /* Timer Field from Basestation */
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#define FT1000_MAG_DSP_TIMER1 0x3FC /* Timer Field from
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* Basestation
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*/
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#define FT1000_MAG_DSP_TIMER1_INDX 0x0
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#define FT1000_MAG_DSP_TIMER2 0x3FD /* Timer Field from Basestation */
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#define FT1000_MAG_DSP_TIMER2 0x3FD /* Timer Field from
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* Basestation
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*/
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#define FT1000_MAG_DSP_TIMER2_INDX 0x1
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#define FT1000_MAG_DSP_TIMER3 0x3FD /* Timer Field from Basestation */
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#define FT1000_MAG_DSP_TIMER3 0x3FD /* Timer Field from
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* Basestation
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*/
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#define FT1000_MAG_DSP_TIMER3_INDX 0x0
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#define FT1000_MAG_TOTAL_LEN 0x200
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#define FT1000_MAG_TOTAL_LEN_INDX 0x1
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@ -99,24 +153,38 @@
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#define HOST_INTF_BE 0x1 /* Host interface big endian mode */
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/* FT1000 to Host Doorbell assignments */
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#define FT1000_DB_DPRAM_RX 0x0001 /* this value indicates that DSP has data for host in DPRAM */
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#define FT1000_DB_DPRAM_RX 0x0001 /* this value indicates that DSP
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* has data for host in DPRAM
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*/
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#define FT1000_DB_DNLD_RX 0x0002 /* Downloader handshake doorbell */
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#define FT1000_ASIC_RESET_REQ 0x0004 /* DSP requesting host to reset the ASIC */
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#define FT1000_DSP_ASIC_RESET 0x0008 /* DSP indicating host that it will reset the ASIC */
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#define FT1000_ASIC_RESET_REQ 0x0004 /* DSP requesting host to
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* reset the ASIC
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*/
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#define FT1000_DSP_ASIC_RESET 0x0008 /* DSP indicating host that
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* it will reset the ASIC
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*/
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#define FT1000_DB_COND_RESET 0x0010 /* DSP request for a card reset. */
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/* Host to FT1000 Doorbell assignments */
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#define FT1000_DB_DPRAM_TX 0x0100 /* this value indicates that host has data for DSP in DPRAM. */
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#define FT1000_DB_DPRAM_TX 0x0100 /* this value indicates that host
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* has data for DSP in DPRAM.
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*/
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#define FT1000_DB_DNLD_TX 0x0200 /* Downloader handshake doorbell */
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#define FT1000_ASIC_RESET_DSP 0x0400 /* Responds to FT1000_ASIC_RESET_REQ */
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#define FT1000_DB_HB 0x1000 /* Indicates that supervisor has a heartbeat message for DSP. */
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#define FT1000_DB_HB 0x1000 /* Indicates that supervisor has a
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* heartbeat message for DSP.
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*/
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#define hi 0x6869 /* PC Card heartbeat values */
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#define ho 0x686f /* PC Card heartbeat values */
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/* Magnemite specific defines */
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#define hi_mag 0x6968 /* Byte swap hi to avoid additional system call */
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#define ho_mag 0x6f68 /* Byte swap ho to avoid additional system call */
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#define hi_mag 0x6968 /* Byte swap hi to avoid
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* additional system call
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*/
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#define ho_mag 0x6f68 /* Byte swap ho to avoid
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* additional system call
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*/
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/* Bit field definitions for Host Interrupt Status Register */
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/* Indicate the cause of an interrupt. */
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@ -133,13 +201,19 @@
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#define ISR_MASK_RCV 0x0004 /* Downlink Packet available mask */
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#define ISR_MASK_WATERMARK 0x0008 /* Watermark interrupt mask */
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#define ISR_MASK_ALL 0xffff /* Mask all interrupts */
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/* Default interrupt mask (Enable Doorbell pending and Packet available interrupts) */
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/* Default interrupt mask
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* (Enable Doorbell pending and Packet available interrupts)
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*/
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#define ISR_DEFAULT_MASK 0x7ff9
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/* Bit field definition for Host Control Register */
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#define DSP_RESET_BIT 0x0001 /* Bit field to control dsp reset state */
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#define DSP_RESET_BIT 0x0001 /* Bit field to control
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* dsp reset state
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*/
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/* (0 = out of reset 1 = reset) */
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#define ASIC_RESET_BIT 0x0002 /* Bit field to control ASIC reset state */
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#define ASIC_RESET_BIT 0x0002 /* Bit field to control
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* ASIC reset state
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*/
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/* (0 = out of reset 1 = reset) */
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#define DSP_UNENCRYPTED 0x0004
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#define DSP_ENCRYPTED 0x0008
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@ -195,7 +269,9 @@ struct pseudo_hdr {
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unsigned char source; /* hardware source id */
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/* Host = 0x10 */
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/* Dsp = 0x20 */
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unsigned char destination; /* hardware destination id (refer to source) */
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unsigned char destination; /* hardware destination id
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* (refer to source)
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*/
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unsigned char portdest; /* software destination port id */
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/* Host = 0x00 */
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/* Applicaton Broadcast = 0x10 */
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@ -204,7 +280,9 @@ struct pseudo_hdr {
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/* Dsp Airlink = 0x90 */
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/* Dsp Loader = 0xa0 */
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/* Dsp MIP = 0xb0 */
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unsigned char portsrc; /* software source port id (refer to portdest) */
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unsigned char portsrc; /* software source port id
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* (refer to portdest)
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*/
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unsigned short sh_str_id; /* not used */
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unsigned char control; /* not used */
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unsigned char rsvd1;
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