clk: hisilicon: add CRG driver for Hi3798CV200 SoC
Add CRG driver for Hi3798CV200 SoC. CRG(Clock and Reset Generator) module generates clock and reset signals used by other module blocks on SoC. Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This commit is contained in:
Jiancheng Xue
Stephen Boyd
parent
1001354ca3
commit
707d33cb0b
6 changed files with 454 additions and 4 deletions
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@ -1,7 +1,7 @@
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* Hisilicon Hi3519 Clock and Reset Generator(CRG)
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* HiSilicon Clock and Reset Generator(CRG)
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The Hi3519 CRG module provides clock and reset signals to various
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controllers within the SoC.
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The CRG module provides clock and reset signals to various
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modules within the SoC.
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This binding uses the following bindings:
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Documentation/devicetree/bindings/clock/clock-bindings.txt
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@ -10,7 +10,11 @@ This binding uses the following bindings:
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Required Properties:
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- compatible: should be one of the following.
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- "hisilicon,hi3519-crg" - controller compatible with Hi3519 SoC.
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- "hisilicon,hi3516cv300-crg"
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- "hisilicon,hi3516cv300-sysctrl"
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- "hisilicon,hi3519-crg"
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- "hisilicon,hi3798cv200-crg"
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- "hisilicon,hi3798cv200-sysctrl"
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- reg: physical base address of the controller and length of memory mapped
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region.
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@ -6,6 +6,14 @@ config COMMON_CLK_HI3519
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help
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Build the clock driver for hi3519.
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config COMMON_CLK_HI3798CV200
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tristate "Hi3798CV200 Clock Driver"
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depends on ARCH_HISI || COMPILE_TEST
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select RESET_HISI
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default ARCH_HISI
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help
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Build the clock driver for hi3798cv200.
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config COMMON_CLK_HI6220
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bool "Hi6220 Clock Driver"
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depends on ARCH_HISI || COMPILE_TEST
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@ -8,6 +8,7 @@ obj-$(CONFIG_ARCH_HI3xxx) += clk-hi3620.o
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obj-$(CONFIG_ARCH_HIP04) += clk-hip04.o
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obj-$(CONFIG_ARCH_HIX5HD2) += clk-hix5hd2.o
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obj-$(CONFIG_COMMON_CLK_HI3519) += clk-hi3519.o
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obj-$(CONFIG_COMMON_CLK_HI3798CV200) += crg-hi3798cv200.o
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obj-$(CONFIG_COMMON_CLK_HI6220) += clk-hi6220.o
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obj-$(CONFIG_RESET_HISI) += reset.o
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obj-$(CONFIG_STUB_CLK_HI6220) += clk-hi6220-stub.o
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337
drivers/clk/hisilicon/crg-hi3798cv200.c
Normal file
337
drivers/clk/hisilicon/crg-hi3798cv200.c
Normal file
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@ -0,0 +1,337 @@
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/*
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* Hi3798CV200 Clock and Reset Generator Driver
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*
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* Copyright (c) 2016 HiSilicon Technologies Co., Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <dt-bindings/clock/histb-clock.h>
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#include <linux/clk-provider.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include "clk.h"
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#include "crg.h"
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#include "reset.h"
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/* hi3798CV200 core CRG */
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#define HI3798CV200_INNER_CLK_OFFSET 64
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#define HI3798CV200_FIXED_24M 65
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#define HI3798CV200_FIXED_25M 66
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#define HI3798CV200_FIXED_50M 67
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#define HI3798CV200_FIXED_75M 68
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#define HI3798CV200_FIXED_100M 69
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#define HI3798CV200_FIXED_150M 70
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#define HI3798CV200_FIXED_200M 71
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#define HI3798CV200_FIXED_250M 72
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#define HI3798CV200_FIXED_300M 73
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#define HI3798CV200_FIXED_400M 74
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#define HI3798CV200_MMC_MUX 75
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#define HI3798CV200_ETH_PUB_CLK 76
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#define HI3798CV200_ETH_BUS_CLK 77
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#define HI3798CV200_ETH_BUS0_CLK 78
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#define HI3798CV200_ETH_BUS1_CLK 79
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#define HI3798CV200_COMBPHY1_MUX 80
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#define HI3798CV200_CRG_NR_CLKS 128
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static const struct hisi_fixed_rate_clock hi3798cv200_fixed_rate_clks[] = {
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{ HISTB_OSC_CLK, "clk_osc", NULL, 0, 24000000, },
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{ HISTB_APB_CLK, "clk_apb", NULL, 0, 100000000, },
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{ HISTB_AHB_CLK, "clk_ahb", NULL, 0, 200000000, },
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{ HI3798CV200_FIXED_24M, "24m", NULL, 0, 24000000, },
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{ HI3798CV200_FIXED_25M, "25m", NULL, 0, 25000000, },
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{ HI3798CV200_FIXED_50M, "50m", NULL, 0, 50000000, },
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{ HI3798CV200_FIXED_75M, "75m", NULL, 0, 75000000, },
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{ HI3798CV200_FIXED_100M, "100m", NULL, 0, 100000000, },
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{ HI3798CV200_FIXED_150M, "150m", NULL, 0, 150000000, },
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{ HI3798CV200_FIXED_200M, "200m", NULL, 0, 200000000, },
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{ HI3798CV200_FIXED_250M, "250m", NULL, 0, 250000000, },
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};
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static const char *const mmc_mux_p[] = {
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"100m", "50m", "25m", "200m", "150m" };
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static u32 mmc_mux_table[] = {0, 1, 2, 3, 6};
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static const char *const comphy1_mux_p[] = {
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"100m", "25m"};
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static u32 comphy1_mux_table[] = {2, 3};
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static struct hisi_mux_clock hi3798cv200_mux_clks[] = {
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{ HI3798CV200_MMC_MUX, "mmc_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
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CLK_SET_RATE_PARENT, 0xa0, 8, 3, 0, mmc_mux_table, },
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{ HI3798CV200_COMBPHY1_MUX, "combphy1_mux",
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comphy1_mux_p, ARRAY_SIZE(comphy1_mux_p),
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CLK_SET_RATE_PARENT, 0x188, 10, 2, 0, comphy1_mux_table, },
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};
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static const struct hisi_gate_clock hi3798cv200_gate_clks[] = {
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/* UART */
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{ HISTB_UART2_CLK, "clk_uart2", "75m",
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CLK_SET_RATE_PARENT, 0x68, 4, 0, },
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/* I2C */
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{ HISTB_I2C0_CLK, "clk_i2c0", "clk_apb",
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CLK_SET_RATE_PARENT, 0x6C, 4, 0, },
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{ HISTB_I2C1_CLK, "clk_i2c1", "clk_apb",
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CLK_SET_RATE_PARENT, 0x6C, 8, 0, },
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{ HISTB_I2C2_CLK, "clk_i2c2", "clk_apb",
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CLK_SET_RATE_PARENT, 0x6C, 12, 0, },
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{ HISTB_I2C3_CLK, "clk_i2c3", "clk_apb",
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CLK_SET_RATE_PARENT, 0x6C, 16, 0, },
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{ HISTB_I2C4_CLK, "clk_i2c4", "clk_apb",
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CLK_SET_RATE_PARENT, 0x6C, 20, 0, },
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/* SPI */
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{ HISTB_SPI0_CLK, "clk_spi0", "clk_apb",
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CLK_SET_RATE_PARENT, 0x70, 0, 0, },
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/* SDIO */
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{ HISTB_SDIO0_BIU_CLK, "clk_sdio0_biu", "200m",
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CLK_SET_RATE_PARENT, 0x9c, 0, 0, },
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{ HISTB_SDIO0_CIU_CLK, "clk_sdio0_ciu", "mmc_mux",
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CLK_SET_RATE_PARENT, 0x9c, 1, 0, },
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/* EMMC */
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{ HISTB_MMC_BIU_CLK, "clk_mmc_biu", "200m",
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CLK_SET_RATE_PARENT, 0xa0, 0, 0, },
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{ HISTB_MMC_CIU_CLK, "clk_mmc_ciu", "mmc_mux",
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CLK_SET_RATE_PARENT, 0xa0, 1, 0, },
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/* PCIE*/
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{ HISTB_PCIE_BUS_CLK, "clk_pcie_bus", "200m",
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CLK_SET_RATE_PARENT, 0x18c, 0, 0, },
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{ HISTB_PCIE_SYS_CLK, "clk_pcie_sys", "100m",
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CLK_SET_RATE_PARENT, 0x18c, 1, 0, },
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{ HISTB_PCIE_PIPE_CLK, "clk_pcie_pipe", "250m",
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CLK_SET_RATE_PARENT, 0x18c, 2, 0, },
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{ HISTB_PCIE_AUX_CLK, "clk_pcie_aux", "24m",
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CLK_SET_RATE_PARENT, 0x18c, 3, 0, },
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/* Ethernet */
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{ HI3798CV200_ETH_PUB_CLK, "clk_pub", NULL,
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CLK_SET_RATE_PARENT, 0xcc, 5, 0, },
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{ HI3798CV200_ETH_BUS_CLK, "clk_bus", "clk_pub",
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CLK_SET_RATE_PARENT, 0xcc, 0, 0, },
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{ HI3798CV200_ETH_BUS0_CLK, "clk_bus_m0", "clk_bus",
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CLK_SET_RATE_PARENT, 0xcc, 1, 0, },
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{ HI3798CV200_ETH_BUS1_CLK, "clk_bus_m1", "clk_bus",
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CLK_SET_RATE_PARENT, 0xcc, 2, 0, },
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{ HISTB_ETH0_MAC_CLK, "clk_mac0", "clk_bus_m0",
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CLK_SET_RATE_PARENT, 0xcc, 3, 0, },
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{ HISTB_ETH0_MACIF_CLK, "clk_macif0", "clk_bus_m0",
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CLK_SET_RATE_PARENT, 0xcc, 24, 0, },
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{ HISTB_ETH1_MAC_CLK, "clk_mac1", "clk_bus_m1",
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CLK_SET_RATE_PARENT, 0xcc, 4, 0, },
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{ HISTB_ETH1_MACIF_CLK, "clk_macif1", "clk_bus_m1",
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CLK_SET_RATE_PARENT, 0xcc, 25, 0, },
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/* COMBPHY1 */
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{ HISTB_COMBPHY1_CLK, "clk_combphy1", "combphy1_mux",
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CLK_SET_RATE_PARENT, 0x188, 8, 0, },
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};
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static struct hisi_clock_data *hi3798cv200_clk_register(
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struct platform_device *pdev)
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{
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struct hisi_clock_data *clk_data;
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int ret;
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clk_data = hisi_clk_alloc(pdev, HI3798CV200_CRG_NR_CLKS);
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if (!clk_data)
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return ERR_PTR(-ENOMEM);
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ret = hisi_clk_register_fixed_rate(hi3798cv200_fixed_rate_clks,
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ARRAY_SIZE(hi3798cv200_fixed_rate_clks),
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clk_data);
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if (ret)
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return ERR_PTR(ret);
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ret = hisi_clk_register_mux(hi3798cv200_mux_clks,
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ARRAY_SIZE(hi3798cv200_mux_clks),
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clk_data);
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if (ret)
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goto unregister_fixed_rate;
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ret = hisi_clk_register_gate(hi3798cv200_gate_clks,
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ARRAY_SIZE(hi3798cv200_gate_clks),
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clk_data);
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if (ret)
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goto unregister_mux;
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ret = of_clk_add_provider(pdev->dev.of_node,
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of_clk_src_onecell_get, &clk_data->clk_data);
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if (ret)
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goto unregister_gate;
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return clk_data;
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unregister_fixed_rate:
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hisi_clk_unregister_fixed_rate(hi3798cv200_fixed_rate_clks,
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ARRAY_SIZE(hi3798cv200_fixed_rate_clks),
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clk_data);
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unregister_mux:
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hisi_clk_unregister_mux(hi3798cv200_mux_clks,
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ARRAY_SIZE(hi3798cv200_mux_clks),
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clk_data);
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unregister_gate:
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hisi_clk_unregister_gate(hi3798cv200_gate_clks,
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ARRAY_SIZE(hi3798cv200_gate_clks),
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clk_data);
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return ERR_PTR(ret);
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}
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static void hi3798cv200_clk_unregister(struct platform_device *pdev)
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{
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struct hisi_crg_dev *crg = platform_get_drvdata(pdev);
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of_clk_del_provider(pdev->dev.of_node);
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hisi_clk_unregister_gate(hi3798cv200_gate_clks,
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ARRAY_SIZE(hi3798cv200_gate_clks),
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crg->clk_data);
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hisi_clk_unregister_mux(hi3798cv200_mux_clks,
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ARRAY_SIZE(hi3798cv200_mux_clks),
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crg->clk_data);
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hisi_clk_unregister_fixed_rate(hi3798cv200_fixed_rate_clks,
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ARRAY_SIZE(hi3798cv200_fixed_rate_clks),
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crg->clk_data);
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}
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static const struct hisi_crg_funcs hi3798cv200_crg_funcs = {
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.register_clks = hi3798cv200_clk_register,
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.unregister_clks = hi3798cv200_clk_unregister,
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};
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/* hi3798CV200 sysctrl CRG */
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#define HI3798CV200_SYSCTRL_NR_CLKS 16
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static const struct hisi_gate_clock hi3798cv200_sysctrl_gate_clks[] = {
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{ HISTB_IR_CLK, "clk_ir", "100m",
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CLK_SET_RATE_PARENT, 0x48, 4, 0, },
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{ HISTB_TIMER01_CLK, "clk_timer01", "24m",
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CLK_SET_RATE_PARENT, 0x48, 6, 0, },
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{ HISTB_UART0_CLK, "clk_uart0", "75m",
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CLK_SET_RATE_PARENT, 0x48, 10, 0, },
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};
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static struct hisi_clock_data *hi3798cv200_sysctrl_clk_register(
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struct platform_device *pdev)
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{
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struct hisi_clock_data *clk_data;
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int ret;
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clk_data = hisi_clk_alloc(pdev, HI3798CV200_SYSCTRL_NR_CLKS);
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if (!clk_data)
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return ERR_PTR(-ENOMEM);
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ret = hisi_clk_register_gate(hi3798cv200_sysctrl_gate_clks,
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ARRAY_SIZE(hi3798cv200_sysctrl_gate_clks),
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clk_data);
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if (ret)
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return ERR_PTR(ret);
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ret = of_clk_add_provider(pdev->dev.of_node,
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of_clk_src_onecell_get, &clk_data->clk_data);
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if (ret)
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goto unregister_gate;
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return clk_data;
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unregister_gate:
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hisi_clk_unregister_gate(hi3798cv200_sysctrl_gate_clks,
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ARRAY_SIZE(hi3798cv200_sysctrl_gate_clks),
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clk_data);
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return ERR_PTR(ret);
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}
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static void hi3798cv200_sysctrl_clk_unregister(struct platform_device *pdev)
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{
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struct hisi_crg_dev *crg = platform_get_drvdata(pdev);
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of_clk_del_provider(pdev->dev.of_node);
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hisi_clk_unregister_gate(hi3798cv200_sysctrl_gate_clks,
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ARRAY_SIZE(hi3798cv200_sysctrl_gate_clks),
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crg->clk_data);
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}
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static const struct hisi_crg_funcs hi3798cv200_sysctrl_funcs = {
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.register_clks = hi3798cv200_sysctrl_clk_register,
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.unregister_clks = hi3798cv200_sysctrl_clk_unregister,
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};
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static const struct of_device_id hi3798cv200_crg_match_table[] = {
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{ .compatible = "hisilicon,hi3798cv200-crg",
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.data = &hi3798cv200_crg_funcs },
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{ .compatible = "hisilicon,hi3798cv200-sysctrl",
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.data = &hi3798cv200_sysctrl_funcs },
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{ }
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};
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MODULE_DEVICE_TABLE(of, hi3798cv200_crg_match_table);
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static int hi3798cv200_crg_probe(struct platform_device *pdev)
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{
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struct hisi_crg_dev *crg;
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crg = devm_kmalloc(&pdev->dev, sizeof(*crg), GFP_KERNEL);
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if (!crg)
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return -ENOMEM;
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crg->funcs = of_device_get_match_data(&pdev->dev);
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if (!crg->funcs)
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return -ENOENT;
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crg->rstc = hisi_reset_init(pdev);
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if (!crg->rstc)
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return -ENOMEM;
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crg->clk_data = crg->funcs->register_clks(pdev);
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if (IS_ERR(crg->clk_data)) {
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hisi_reset_exit(crg->rstc);
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return PTR_ERR(crg->clk_data);
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}
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platform_set_drvdata(pdev, crg);
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return 0;
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}
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static int hi3798cv200_crg_remove(struct platform_device *pdev)
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{
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struct hisi_crg_dev *crg = platform_get_drvdata(pdev);
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hisi_reset_exit(crg->rstc);
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crg->funcs->unregister_clks(pdev);
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return 0;
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}
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static struct platform_driver hi3798cv200_crg_driver = {
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.probe = hi3798cv200_crg_probe,
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.remove = hi3798cv200_crg_remove,
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.driver = {
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.name = "hi3798cv200-crg",
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.of_match_table = hi3798cv200_crg_match_table,
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},
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};
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static int __init hi3798cv200_crg_init(void)
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{
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return platform_driver_register(&hi3798cv200_crg_driver);
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}
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core_initcall(hi3798cv200_crg_init);
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static void __exit hi3798cv200_crg_exit(void)
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{
|
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platform_driver_unregister(&hi3798cv200_crg_driver);
|
||||
}
|
||||
module_exit(hi3798cv200_crg_exit);
|
||||
|
||||
MODULE_LICENSE("GPL v2");
|
||||
MODULE_DESCRIPTION("HiSilicon Hi3798CV200 CRG Driver");
|
||||
34
drivers/clk/hisilicon/crg.h
Normal file
34
drivers/clk/hisilicon/crg.h
Normal file
|
|
@ -0,0 +1,34 @@
|
|||
/*
|
||||
* HiSilicon Clock and Reset Driver Header
|
||||
*
|
||||
* Copyright (c) 2016 HiSilicon Limited.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef __HISI_CRG_H
|
||||
#define __HISI_CRG_H
|
||||
|
||||
struct hisi_clock_data;
|
||||
struct hisi_reset_controller;
|
||||
|
||||
struct hisi_crg_funcs {
|
||||
struct hisi_clock_data* (*register_clks)(struct platform_device *pdev);
|
||||
void (*unregister_clks)(struct platform_device *pdev);
|
||||
};
|
||||
|
||||
struct hisi_crg_dev {
|
||||
struct hisi_clock_data *clk_data;
|
||||
struct hisi_reset_controller *rstc;
|
||||
const struct hisi_crg_funcs *funcs;
|
||||
};
|
||||
|
||||
#endif /* __HISI_CRG_H */
|
||||
66
include/dt-bindings/clock/histb-clock.h
Normal file
66
include/dt-bindings/clock/histb-clock.h
Normal file
|
|
@ -0,0 +1,66 @@
|
|||
/*
|
||||
* Copyright (c) 2016 HiSilicon Technologies Co., Ltd.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef __DTS_HISTB_CLOCK_H
|
||||
#define __DTS_HISTB_CLOCK_H
|
||||
|
||||
/* clocks provided by core CRG */
|
||||
#define HISTB_OSC_CLK 0
|
||||
#define HISTB_APB_CLK 1
|
||||
#define HISTB_AHB_CLK 2
|
||||
#define HISTB_UART1_CLK 3
|
||||
#define HISTB_UART2_CLK 4
|
||||
#define HISTB_UART3_CLK 5
|
||||
#define HISTB_I2C0_CLK 6
|
||||
#define HISTB_I2C1_CLK 7
|
||||
#define HISTB_I2C2_CLK 8
|
||||
#define HISTB_I2C3_CLK 9
|
||||
#define HISTB_I2C4_CLK 10
|
||||
#define HISTB_I2C5_CLK 11
|
||||
#define HISTB_SPI0_CLK 12
|
||||
#define HISTB_SPI1_CLK 13
|
||||
#define HISTB_SPI2_CLK 14
|
||||
#define HISTB_SCI_CLK 15
|
||||
#define HISTB_FMC_CLK 16
|
||||
#define HISTB_MMC_BIU_CLK 17
|
||||
#define HISTB_MMC_CIU_CLK 18
|
||||
#define HISTB_MMC_DRV_CLK 19
|
||||
#define HISTB_MMC_SAMPLE_CLK 20
|
||||
#define HISTB_SDIO0_BIU_CLK 21
|
||||
#define HISTB_SDIO0_CIU_CLK 22
|
||||
#define HISTB_SDIO0_DRV_CLK 23
|
||||
#define HISTB_SDIO0_SAMPLE_CLK 24
|
||||
#define HISTB_PCIE_AUX_CLK 25
|
||||
#define HISTB_PCIE_PIPE_CLK 26
|
||||
#define HISTB_PCIE_SYS_CLK 27
|
||||
#define HISTB_PCIE_BUS_CLK 28
|
||||
#define HISTB_ETH0_MAC_CLK 29
|
||||
#define HISTB_ETH0_MACIF_CLK 30
|
||||
#define HISTB_ETH1_MAC_CLK 31
|
||||
#define HISTB_ETH1_MACIF_CLK 32
|
||||
#define HISTB_COMBPHY1_CLK 33
|
||||
|
||||
|
||||
/* clocks provided by mcu CRG */
|
||||
#define HISTB_MCE_CLK 1
|
||||
#define HISTB_IR_CLK 2
|
||||
#define HISTB_TIMER01_CLK 3
|
||||
#define HISTB_LEDC_CLK 4
|
||||
#define HISTB_UART0_CLK 5
|
||||
#define HISTB_LSADC_CLK 6
|
||||
|
||||
#endif /* __DTS_HISTB_CLOCK_H */
|
||||
Loading…
Reference in a new issue