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arm-soc: late OMAP changes

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This branch contains changes for OMAP that came in late during the release
 staging, close to when the merge window opened.
 
 It contains, among other things:
 
 - OMAP PM fixes and some patches for audio device integration
 - OMAP clock fixes related to common clock conversion
 - A set of patches cleaning up WFI entry and blocking.
 - A set of fixes and IP block support for PM on TI AM33xx SoCs (Beaglebone, etc)
 - A set of smaller fixes and cleanups around AM33xx restart and revision
   detection, as well as removal of some dead code (CONFIG_32K_TIMER_HZ)
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1.4.11 (GNU/Linux)
 
 iQIcBAABAgAGBQJRL9AUAAoJEIwa5zzehBx3BiIQAIwJOAZQhbIsDAmqVAGfj39i
 Y6DneECJ3BvrMsC3nk6IUOC/aW5uUi2GAmhYI6YuDDKzLfeTSGW2VQcMa98cvWig
 dLo2CPqKuuB7YZAwHkg4i3BwHVJcaPntaKOajNmhwJQIiNEiXCauP/f9kG2NKvHu
 XxlWuNyeEB1uQlnB0nXL+HHqcHKxproK6eIvILWYJMdVYnMn+57O3yWBmXkCr07b
 9oOa1NdR+4xN7cSbS5YGUfxqwDWnXSZSKggXEPLglHObmSqj7R7NDBNgRR7ui8+t
 c3UYljPsiRprY8TYVTbator9wyYocZ6pMja+vrPwATHUMsxGZTurURzpYsyAXaMc
 VKWLWItCOOee8CKn1+pGpelon69//EJEFIsg1hChJJZKMRLHYVg48tM64/uN1VOo
 Mu/6XDLx4DearMxZv5pZ7Qe0IkIDGtlpyIwo1Yy6T5xEC6pcwRG0XeTuQtOxndFc
 XUcXrE+Nlg3eW/6xtB7XhftnKVoBsCrIQ5Z+PxMw1QNUTXWxQwZffeBLxGenuoD6
 IofLCdjVyRMcPnVj+s29ZO5k7yMllQ0dO8bySxoU2Y2QvD7wUdZxGDY5Nu7cwfAt
 jL0sEpT32g4ZSD8R75qt+qTDWv/IjB4EE/uNw3y2AUSTT5A+cN7H3MXw5s7hm8nI
 fw5cYz37iH0zUZhoIU/w
 =/vBT
 -----END PGP SIGNATURE-----

Merge tag 'late-omap' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC late OMAP changes from Olof Johansson:
 "This branch contains changes for OMAP that came in late during the
  release staging, close to when the merge window opened.

  It contains, among other things:

   - OMAP PM fixes and some patches for audio device integration
   - OMAP clock fixes related to common clock conversion
   - A set of patches cleaning up WFI entry and blocking.
   - A set of fixes and IP block support for PM on TI AM33xx SoCs
     (Beaglebone, etc)
   - A set of smaller fixes and cleanups around AM33xx restart and
     revision detection, as well as removal of some dead code
     (CONFIG_32K_TIMER_HZ)"

* tag 'late-omap' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (34 commits)
  ARM: omap2: include linux/errno.h in hwmod_reset
  ARM: OMAP2+: fix some omap_device_build() calls that aren't compiled by default
  ARM: OMAP4: hwmod data: Enable AESS hwmod device
  ARM: OMAP4: hwmod data: Update AESS data with memory bank area
  ARM: OMAP4+: AESS: enable internal auto-gating during initial setup
  ASoC: TI AESS: add autogating-enable function, callable from architecture code
  ARM: OMAP2+: hwmod: add enable_preprogram hook
  ARM: OMAP4: clock data: Add missing clkdm association for dpll_usb
  ARM: OMAP2+: PM: Fix the dt return condition in pm_late_init()
  ARM: OMAP2: am33xx-hwmod: Fix "register offset NULL check" bug
  ARM: OMAP2+: AM33xx: hwmod: add missing HWMOD_NO_IDLEST flags
  ARM: OMAP: AM33xx hwmod: Add parent-child relationship for PWM subsystem
  ARM: OMAP: AM33xx hwmod: Corrects PWM subsystem HWMOD entries
  ARM: DTS: AM33XX: Add nodes for OCMC RAM and WKUP-M3
  ARM: OMAP2+: AM33XX: Update the hardreset API
  ARM: OMAP2+: AM33XX: hwmod: Update the WKUP-M3 hwmod with reset status bit
  ARM: OMAP2+: AM33XX: hwmod: Fixup cpgmac0 hwmod entry
  ARM: OMAP2+: AM33XX: hwmod: Update TPTC0 hwmod with the right flags
  ARM: OMAP2+: AM33XX: hwmod: Register OCMC RAM hwmod
  ARM: OMAP2+: AM33XX: CM/PRM: Use __ASSEMBLER__ macros in header files
  ...
This commit is contained in:
Linus Torvalds 2013-02-28 20:00:40 -08:00
commit 7307c00f33
35 changed files with 659 additions and 305 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

1
arch/arm/Kconfig
View file

@ -1676,7 +1676,6 @@ config HZ
int
default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
ARCH_S5PV210 || ARCH_EXYNOS4
default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
default AT91_TIMER_HZ if ARCH_AT91
default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
default 100

14
arch/arm/boot/dts/am33xx.dtsi
View file

@ -385,5 +385,19 @@
mac-address = [ 00 00 00 00 00 00 ];
};
};
ocmcram: ocmcram@40300000 {
compatible = "ti,am3352-ocmcram";
reg = <0x40300000 0x10000>;
ti,hwmods = "ocmcram";
ti,no_idle_on_suspend;
};
wkup_m3: wkup_m3@44d00000 {
compatible = "ti,am3353-wkup-m3";
reg = <0x44d00000 0x4000 /* M3 UMEM */
0x44d80000 0x2000>; /* M3 DMEM */
ti,hwmods = "wkup_m3";
};
};
};

3
arch/arm/mach-omap2/Makefile
View file

@ -11,7 +11,7 @@ obj-y := id.o io.o control.o mux.o devices.o fb.o serial.o gpmc.o timer.o pm.o \
omap_device.o sram.o
omap-2-3-common = irq.o
hwmod-common = omap_hwmod.o \
hwmod-common = omap_hwmod.o omap_hwmod_reset.o \
omap_hwmod_common_data.o
clock-common = clock.o clock_common_data.o \
clkt_dpll.o clkt_clksel.o
@ -56,6 +56,7 @@ AFLAGS_sram34xx.o :=-Wa,-march=armv7-a
# Restart code (OMAP4/5 currently in omap4-common.c)
obj-$(CONFIG_SOC_OMAP2420) += omap2-restart.o
obj-$(CONFIG_SOC_OMAP2430) += omap2-restart.o
obj-$(CONFIG_SOC_AM33XX) += am33xx-restart.o
obj-$(CONFIG_ARCH_OMAP3) += omap3-restart.o
# Pin multiplexing

34
arch/arm/mach-omap2/am33xx-restart.c Normal file
View file

@ -0,0 +1,34 @@
/*
* am33xx-restart.c - Code common to all AM33xx machines.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include "common.h"
#include "prm-regbits-33xx.h"
#include "prm33xx.h"
/**
* am3xx_restart - trigger a software restart of the SoC
* @mode: the "reboot mode", see arch/arm/kernel/{setup,process}.c
* @cmd: passed from the userspace program rebooting the system (if provided)
*
* Resets the SoC. For @cmd, see the 'reboot' syscall in
* kernel/sys.c. No return value.
*/
void am33xx_restart(char mode, const char *cmd)
{
/* TODO: Handle mode and cmd if necessary */
am33xx_prm_rmw_reg_bits(AM33XX_GLOBAL_WARM_SW_RST_MASK,
AM33XX_GLOBAL_WARM_SW_RST_MASK,
AM33XX_PRM_DEVICE_MOD,
AM33XX_PRM_RSTCTRL_OFFSET);
/* OCP barrier */
(void)am33xx_prm_read_reg(AM33XX_PRM_DEVICE_MOD,
AM33XX_PRM_RSTCTRL_OFFSET);
}

3
arch/arm/mach-omap2/am35xx-emac.c
View file

@ -62,8 +62,7 @@ static int __init omap_davinci_emac_dev_init(struct omap_hwmod *oh,
{
struct platform_device *pdev;
pdev = omap_device_build(oh->class->name, 0, oh, pdata, pdata_len,
false);
pdev = omap_device_build(oh->class->name, 0, oh, pdata, pdata_len);
if (IS_ERR(pdev)) {
WARN(1, "Can't build omap_device for %s:%s.\n",
oh->class->name, oh->name);

1
arch/arm/mach-omap2/board-generic.c
View file

@ -140,6 +140,7 @@ DT_MACHINE_START(AM33XX_DT, "Generic AM33XX (Flattened Device Tree)")
.init_machine = omap_generic_init,
.init_time = omap3_am33xx_gptimer_timer_init,
.dt_compat = am33xx_boards_compat,
.restart = am33xx_restart,
MACHINE_END
#endif

10
arch/arm/mach-omap2/cclock33xx_data.c
View file

@ -284,9 +284,10 @@ DEFINE_STRUCT_CLK(dpll_disp_ck, dpll_core_ck_parents, dpll_ddr_ck_ops);
* TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2
* and ALT_CLK1/2)
*/
DEFINE_CLK_DIVIDER(dpll_disp_m2_ck, "dpll_disp_ck", &dpll_disp_ck, 0x0,
AM33XX_CM_DIV_M2_DPLL_DISP, AM33XX_DPLL_CLKOUT_DIV_SHIFT,
AM33XX_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);
DEFINE_CLK_DIVIDER(dpll_disp_m2_ck, "dpll_disp_ck", &dpll_disp_ck,
CLK_SET_RATE_PARENT, AM33XX_CM_DIV_M2_DPLL_DISP,
AM33XX_DPLL_CLKOUT_DIV_SHIFT, AM33XX_DPLL_CLKOUT_DIV_WIDTH,
CLK_DIVIDER_ONE_BASED, NULL);
/* DPLL_PER */
static struct dpll_data dpll_per_dd = {
@ -723,7 +724,8 @@ static struct clk_hw_omap lcd_gclk_hw = {
.clksel_mask = AM33XX_CLKSEL_0_1_MASK,
};
DEFINE_STRUCT_CLK(lcd_gclk, lcd_ck_parents, gpio_fck_ops);
DEFINE_STRUCT_CLK_FLAGS(lcd_gclk, lcd_ck_parents,
gpio_fck_ops, CLK_SET_RATE_PARENT);
DEFINE_CLK_FIXED_FACTOR(mmc_clk, "dpll_per_m2_ck", &dpll_per_m2_ck, 0x0, 1, 2);

10
arch/arm/mach-omap2/cclock3xxx_data.c
View file

@ -426,6 +426,7 @@ static struct clk dpll4_m5x2_ck_3630 = {
.parent_names = dpll4_m5x2_ck_parent_names,
.num_parents = ARRAY_SIZE(dpll4_m5x2_ck_parent_names),
.ops = &dpll4_m5x2_ck_3630_ops,
.flags = CLK_SET_RATE_PARENT,
};
static struct clk cam_mclk;
@ -443,7 +444,14 @@ static struct clk_hw_omap cam_mclk_hw = {
.clkdm_name = "cam_clkdm",
};
DEFINE_STRUCT_CLK(cam_mclk, cam_mclk_parent_names, aes2_ick_ops);
static struct clk cam_mclk = {
.name = "cam_mclk",
.hw = &cam_mclk_hw.hw,
.parent_names = cam_mclk_parent_names,
.num_parents = ARRAY_SIZE(cam_mclk_parent_names),
.ops = &aes2_ick_ops,
.flags = CLK_SET_RATE_PARENT,
};
static const struct clksel_rate clkout2_src_core_rates[] = {
{ .div = 1, .val = 0, .flags = RATE_IN_3XXX },

13
arch/arm/mach-omap2/cclock44xx_data.c
View file

@ -605,15 +605,26 @@ static const char *dpll_usb_ck_parents[] = {
static struct clk dpll_usb_ck;
static const struct clk_ops dpll_usb_ck_ops = {
.enable = &omap3_noncore_dpll_enable,
.disable = &omap3_noncore_dpll_disable,
.recalc_rate = &omap3_dpll_recalc,
.round_rate = &omap2_dpll_round_rate,
.set_rate = &omap3_noncore_dpll_set_rate,
.get_parent = &omap2_init_dpll_parent,
.init = &omap2_init_clk_clkdm,
};
static struct clk_hw_omap dpll_usb_ck_hw = {
.hw = {
.clk = &dpll_usb_ck,
},
.dpll_data = &dpll_usb_dd,
.clkdm_name = "l3_init_clkdm",
.ops = &clkhwops_omap3_dpll,
};
DEFINE_STRUCT_CLK(dpll_usb_ck, dpll_usb_ck_parents, dpll_ck_ops);
DEFINE_STRUCT_CLK(dpll_usb_ck, dpll_usb_ck_parents, dpll_usb_ck_ops);
static const char *dpll_usb_clkdcoldo_ck_parents[] = {
"dpll_usb_ck",

11
arch/arm/mach-omap2/clock.h
View file

@ -65,6 +65,17 @@ struct clockdomain;
.ops = &_clkops_name, \
};
#define DEFINE_STRUCT_CLK_FLAGS(_name, _parent_array_name, \
_clkops_name, _flags) \
static struct clk _name = { \
.name = #_name, \
.hw = &_name##_hw.hw, \
.parent_names = _parent_array_name, \
.num_parents = ARRAY_SIZE(_parent_array_name), \
.ops = &_clkops_name, \
.flags = _flags, \
};
#define DEFINE_STRUCT_CLK_HW_OMAP(_name, _clkdm_name) \
static struct clk_hw_omap _name##_hw = { \
.hw = { \

3
arch/arm/mach-omap2/cm33xx.c
View file

@ -241,9 +241,6 @@ int am33xx_cm_wait_module_ready(u16 inst, s16 cdoffs, u16 clkctrl_offs)
{
int i = 0;
if (!clkctrl_offs)
return 0;
omap_test_timeout(_is_module_ready(inst, cdoffs, clkctrl_offs),
MAX_MODULE_READY_TIME, i);

9
arch/arm/mach-omap2/cm33xx.h
View file

@ -17,16 +17,11 @@
#ifndef __ARCH_ARM_MACH_OMAP2_CM_33XX_H
#define __ARCH_ARM_MACH_OMAP2_CM_33XX_H
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/err.h>
#include <linux/io.h>
#include "common.h"
#include "cm.h"
#include "cm-regbits-33xx.h"
#include "cm33xx.h"
#include "iomap.h"
/* CM base address */
#define AM33XX_CM_BASE 0x44e00000
@ -381,6 +376,7 @@
#define AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_CEFUSE_MOD, 0x0020)
#ifndef __ASSEMBLER__
extern bool am33xx_cm_is_clkdm_in_hwsup(s16 inst, u16 cdoffs);
extern void am33xx_cm_clkdm_enable_hwsup(s16 inst, u16 cdoffs);
extern void am33xx_cm_clkdm_disable_hwsup(s16 inst, u16 cdoffs);
@ -417,4 +413,5 @@ static inline int am33xx_cm_wait_module_ready(u16 inst, s16 cdoffs,
}
#endif
#endif /* ASSEMBLER */
#endif

8
arch/arm/mach-omap2/common.h
View file

@ -119,6 +119,14 @@ static inline void omap2xxx_restart(char mode, const char *cmd)
}
#endif
#ifdef CONFIG_SOC_AM33XX
void am33xx_restart(char mode, const char *cmd);
#else
static inline void am33xx_restart(char mode, const char *cmd)
{
}
#endif
#ifdef CONFIG_ARCH_OMAP3
void omap3xxx_restart(char mode, const char *cmd);
#else

2
arch/arm/mach-omap2/devices.c
View file

@ -426,7 +426,7 @@ static void __init omap_init_hdmi_audio(void)
return;
}
pdev = omap_device_build("omap-hdmi-audio-dai", -1, oh, NULL, 0, 0);
pdev = omap_device_build("omap-hdmi-audio-dai", -1, oh, NULL, 0);
WARN(IS_ERR(pdev),
"Can't build omap_device for omap-hdmi-audio-dai.\n");

5
arch/arm/mach-omap2/dpll3xxx.c
View file

@ -500,8 +500,9 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
if (dd->last_rounded_rate == 0)
return -EINVAL;
/* No freqsel on OMAP4 and OMAP3630 */
if (!cpu_is_omap44xx() && !cpu_is_omap3630()) {
/* No freqsel on AM335x, OMAP4 and OMAP3630 */
if (!soc_is_am33xx() && !cpu_is_omap44xx() &&
!cpu_is_omap3630()) {
freqsel = _omap3_dpll_compute_freqsel(clk,
dd->last_rounded_n);
WARN_ON(!freqsel);

14
arch/arm/mach-omap2/id.c
View file

@ -399,8 +399,18 @@ void __init omap3xxx_check_revision(void)
}
break;
case 0xb944:
omap_revision = AM335X_REV_ES1_0;
cpu_rev = "1.0";
switch (rev) {
case 0:
omap_revision = AM335X_REV_ES1_0;
cpu_rev = "1.0";
break;
case 1:
/* FALLTHROUGH */
default:
omap_revision = AM335X_REV_ES2_0;
cpu_rev = "2.0";
break;
}
break;
case 0xb8f2:
switch (rev) {

23
arch/arm/mach-omap2/omap_hwmod.c
View file

@ -2054,6 +2054,23 @@ static int _omap4_get_context_lost(struct omap_hwmod *oh)
return oh->prcm.omap4.context_lost_counter;
}
/**
* _enable_preprogram - Pre-program an IP block during the _enable() process
* @oh: struct omap_hwmod *
*
* Some IP blocks (such as AESS) require some additional programming
* after enable before they can enter idle. If a function pointer to
* do so is present in the hwmod data, then call it and pass along the
* return value; otherwise, return 0.
*/
static int __init _enable_preprogram(struct omap_hwmod *oh)
{
if (!oh->class->enable_preprogram)
return 0;
return oh->class->enable_preprogram(oh);
}
/**
* _enable - enable an omap_hwmod
* @oh: struct omap_hwmod *
@ -2160,6 +2177,7 @@ static int _enable(struct omap_hwmod *oh)
_update_sysc_cache(oh);
_enable_sysc(oh);
}
r = _enable_preprogram(oh);
} else {
if (soc_ops.disable_module)
soc_ops.disable_module(oh);
@ -3049,11 +3067,8 @@ static int _am33xx_assert_hardreset(struct omap_hwmod *oh,
static int _am33xx_deassert_hardreset(struct omap_hwmod *oh,
struct omap_hwmod_rst_info *ohri)
{
if (ohri->st_shift)
pr_err("omap_hwmod: %s: %s: hwmod data error: OMAP4 does not support st_shift\n",
oh->name, ohri->name);
return am33xx_prm_deassert_hardreset(ohri->rst_shift,
ohri->st_shift,
oh->clkdm->pwrdm.ptr->prcm_offs,
oh->prcm.omap4.rstctrl_offs,
oh->prcm.omap4.rstst_offs);

8
arch/arm/mach-omap2/omap_hwmod.h
View file

@ -510,6 +510,7 @@ struct omap_hwmod_omap4_prcm {
* @rev: revision of the IP class
* @pre_shutdown: ptr to fn to be executed immediately prior to device shutdown
* @reset: ptr to fn to be executed in place of the standard hwmod reset fn
* @enable_preprogram: ptr to fn to be executed during device enable
*
* Represent the class of a OMAP hardware "modules" (e.g. timer,
* smartreflex, gpio, uart...)
@ -533,6 +534,7 @@ struct omap_hwmod_class {
u32 rev;
int (*pre_shutdown)(struct omap_hwmod *oh);
int (*reset)(struct omap_hwmod *oh);
int (*enable_preprogram)(struct omap_hwmod *oh);
};
/**
@ -679,6 +681,12 @@ extern void __init omap_hwmod_init(void);
const char *omap_hwmod_get_main_clk(struct omap_hwmod *oh);
/*
*
*/
extern int omap_hwmod_aess_preprogram(struct omap_hwmod *oh);
/*
* Chip variant-specific hwmod init routines - XXX should be converted
* to use initcalls once the initial boot ordering is straightened out

491
arch/arm/mach-omap2/omap_hwmod_33xx_data.c
View file

@ -262,13 +262,15 @@ static struct omap_hwmod am33xx_wkup_m3_hwmod = {
.name = "wkup_m3",
.class = &am33xx_wkup_m3_hwmod_class,
.clkdm_name = "l4_wkup_aon_clkdm",
.flags = HWMOD_INIT_NO_RESET, /* Keep hardreset asserted */
/* Keep hardreset asserted */
.flags = HWMOD_INIT_NO_RESET | HWMOD_NO_IDLEST,
.mpu_irqs = am33xx_wkup_m3_irqs,
.main_clk = "dpll_core_m4_div2_ck",
.prcm = {
.omap4 = {
.clkctrl_offs = AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
.rstctrl_offs = AM33XX_RM_WKUP_RSTCTRL_OFFSET,
.rstst_offs = AM33XX_RM_WKUP_RSTST_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
@ -414,7 +416,6 @@ static struct omap_hwmod am33xx_adc_tsc_hwmod = {
* - cEFUSE (doesn't fall under any ocp_if)
* - clkdiv32k
* - debugss
* - ocmc ram
* - ocp watch point
* - aes0
* - sha0
@ -481,25 +482,6 @@ static struct omap_hwmod am33xx_debugss_hwmod = {
},
};
/* ocmcram */
static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
.name = "ocmcram",
};
static struct omap_hwmod am33xx_ocmcram_hwmod = {
.name = "ocmcram",
.class = &am33xx_ocmcram_hwmod_class,
.clkdm_name = "l3_clkdm",
.flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
.main_clk = "l3_gclk",
.prcm = {
.omap4 = {
.clkctrl_offs = AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/* ocpwp */
static struct omap_hwmod_class am33xx_ocpwp_hwmod_class = {
.name = "ocpwp",
@ -570,6 +552,25 @@ static struct omap_hwmod am33xx_sha0_hwmod = {
#endif
/* ocmcram */
static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
.name = "ocmcram",
};
static struct omap_hwmod am33xx_ocmcram_hwmod = {
.name = "ocmcram",
.class = &am33xx_ocmcram_hwmod_class,
.clkdm_name = "l3_clkdm",
.flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
.main_clk = "l3_gclk",
.prcm = {
.omap4 = {
.clkctrl_offs = AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/* 'smartreflex' class */
static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = {
.name = "smartreflex",
@ -783,9 +784,7 @@ static struct omap_hwmod am33xx_elm_hwmod = {
},
};
/*
* 'epwmss' class: ecap0,1,2, ehrpwm0,1,2
*/
/* pwmss */
static struct omap_hwmod_class_sysconfig am33xx_epwmss_sysc = {
.rev_offs = 0x0,
.sysc_offs = 0x4,
@ -801,18 +800,23 @@ static struct omap_hwmod_class am33xx_epwmss_hwmod_class = {
.sysc = &am33xx_epwmss_sysc,
};
/* ehrpwm0 */
static struct omap_hwmod_irq_info am33xx_ehrpwm0_irqs[] = {
{ .name = "int", .irq = 86 + OMAP_INTC_START, },
{ .name = "tzint", .irq = 58 + OMAP_INTC_START, },
{ .irq = -1 },
static struct omap_hwmod_class am33xx_ecap_hwmod_class = {
.name = "ecap",
};
static struct omap_hwmod am33xx_ehrpwm0_hwmod = {
.name = "ehrpwm0",
static struct omap_hwmod_class am33xx_eqep_hwmod_class = {
.name = "eqep",
};
static struct omap_hwmod_class am33xx_ehrpwm_hwmod_class = {
.name = "ehrpwm",
};
/* epwmss0 */
static struct omap_hwmod am33xx_epwmss0_hwmod = {
.name = "epwmss0",
.class = &am33xx_epwmss_hwmod_class,
.clkdm_name = "l4ls_clkdm",
.mpu_irqs = am33xx_ehrpwm0_irqs,
.main_clk = "l4ls_gclk",
.prcm = {
.omap4 = {
@ -822,48 +826,6 @@ static struct omap_hwmod am33xx_ehrpwm0_hwmod = {
},
};
/* ehrpwm1 */
static struct omap_hwmod_irq_info am33xx_ehrpwm1_irqs[] = {
{ .name = "int", .irq = 87 + OMAP_INTC_START, },
{ .name = "tzint", .irq = 59 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod am33xx_ehrpwm1_hwmod = {
.name = "ehrpwm1",
.class = &am33xx_epwmss_hwmod_class,
.clkdm_name = "l4ls_clkdm",
.mpu_irqs = am33xx_ehrpwm1_irqs,
.main_clk = "l4ls_gclk",
.prcm = {
.omap4 = {
.clkctrl_offs = AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/* ehrpwm2 */
static struct omap_hwmod_irq_info am33xx_ehrpwm2_irqs[] = {
{ .name = "int", .irq = 39 + OMAP_INTC_START, },
{ .name = "tzint", .irq = 60 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod am33xx_ehrpwm2_hwmod = {
.name = "ehrpwm2",
.class = &am33xx_epwmss_hwmod_class,
.clkdm_name = "l4ls_clkdm",
.mpu_irqs = am33xx_ehrpwm2_irqs,
.main_clk = "l4ls_gclk",
.prcm = {
.omap4 = {
.clkctrl_offs = AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/* ecap0 */
static struct omap_hwmod_irq_info am33xx_ecap0_irqs[] = {
{ .irq = 31 + OMAP_INTC_START, },
@ -872,13 +834,50 @@ static struct omap_hwmod_irq_info am33xx_ecap0_irqs[] = {
static struct omap_hwmod am33xx_ecap0_hwmod = {
.name = "ecap0",
.class = &am33xx_epwmss_hwmod_class,
.class = &am33xx_ecap_hwmod_class,
.clkdm_name = "l4ls_clkdm",
.mpu_irqs = am33xx_ecap0_irqs,
.main_clk = "l4ls_gclk",
};
/* eqep0 */
static struct omap_hwmod_irq_info am33xx_eqep0_irqs[] = {
{ .irq = 79 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod am33xx_eqep0_hwmod = {
.name = "eqep0",
.class = &am33xx_eqep_hwmod_class,
.clkdm_name = "l4ls_clkdm",
.mpu_irqs = am33xx_eqep0_irqs,
.main_clk = "l4ls_gclk",
};
/* ehrpwm0 */
static struct omap_hwmod_irq_info am33xx_ehrpwm0_irqs[] = {
{ .name = "int", .irq = 86 + OMAP_INTC_START, },
{ .name = "tzint", .irq = 58 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod am33xx_ehrpwm0_hwmod = {
.name = "ehrpwm0",
.class = &am33xx_ehrpwm_hwmod_class,
.clkdm_name = "l4ls_clkdm",
.mpu_irqs = am33xx_ehrpwm0_irqs,
.main_clk = "l4ls_gclk",
};
/* epwmss1 */
static struct omap_hwmod am33xx_epwmss1_hwmod = {
.name = "epwmss1",
.class = &am33xx_epwmss_hwmod_class,
.clkdm_name = "l4ls_clkdm",
.main_clk = "l4ls_gclk",
.prcm = {
.omap4 = {
.clkctrl_offs = AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET,
.clkctrl_offs = AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
@ -892,13 +891,50 @@ static struct omap_hwmod_irq_info am33xx_ecap1_irqs[] = {
static struct omap_hwmod am33xx_ecap1_hwmod = {
.name = "ecap1",
.class = &am33xx_epwmss_hwmod_class,
.class = &am33xx_ecap_hwmod_class,
.clkdm_name = "l4ls_clkdm",
.mpu_irqs = am33xx_ecap1_irqs,
.main_clk = "l4ls_gclk",
};
/* eqep1 */
static struct omap_hwmod_irq_info am33xx_eqep1_irqs[] = {
{ .irq = 88 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod am33xx_eqep1_hwmod = {
.name = "eqep1",
.class = &am33xx_eqep_hwmod_class,
.clkdm_name = "l4ls_clkdm",
.mpu_irqs = am33xx_eqep1_irqs,
.main_clk = "l4ls_gclk",
};
/* ehrpwm1 */
static struct omap_hwmod_irq_info am33xx_ehrpwm1_irqs[] = {
{ .name = "int", .irq = 87 + OMAP_INTC_START, },
{ .name = "tzint", .irq = 59 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod am33xx_ehrpwm1_hwmod = {
.name = "ehrpwm1",
.class = &am33xx_ehrpwm_hwmod_class,
.clkdm_name = "l4ls_clkdm",
.mpu_irqs = am33xx_ehrpwm1_irqs,
.main_clk = "l4ls_gclk",
};
/* epwmss2 */
static struct omap_hwmod am33xx_epwmss2_hwmod = {
.name = "epwmss2",
.class = &am33xx_epwmss_hwmod_class,
.clkdm_name = "l4ls_clkdm",
.main_clk = "l4ls_gclk",
.prcm = {
.omap4 = {
.clkctrl_offs = AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET,
.clkctrl_offs = AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
@ -912,16 +948,39 @@ static struct omap_hwmod_irq_info am33xx_ecap2_irqs[] = {
static struct omap_hwmod am33xx_ecap2_hwmod = {
.name = "ecap2",
.mpu_irqs = am33xx_ecap2_irqs,
.class = &am33xx_epwmss_hwmod_class,
.class = &am33xx_ecap_hwmod_class,
.clkdm_name = "l4ls_clkdm",
.mpu_irqs = am33xx_ecap2_irqs,
.main_clk = "l4ls_gclk",
};
/* eqep2 */
static struct omap_hwmod_irq_info am33xx_eqep2_irqs[] = {
{ .irq = 89 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod am33xx_eqep2_hwmod = {
.name = "eqep2",
.class = &am33xx_eqep_hwmod_class,
.clkdm_name = "l4ls_clkdm",
.mpu_irqs = am33xx_eqep2_irqs,
.main_clk = "l4ls_gclk",
};
/* ehrpwm2 */
static struct omap_hwmod_irq_info am33xx_ehrpwm2_irqs[] = {
{ .name = "int", .irq = 39 + OMAP_INTC_START, },
{ .name = "tzint", .irq = 60 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod am33xx_ehrpwm2_hwmod = {
.name = "ehrpwm2",
.class = &am33xx_ehrpwm_hwmod_class,
.clkdm_name = "l4ls_clkdm",
.mpu_irqs = am33xx_ehrpwm2_irqs,
.main_clk = "l4ls_gclk",
.prcm = {
.omap4 = {
.clkctrl_offs = AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/*
@ -1824,6 +1883,7 @@ static struct omap_hwmod am33xx_tptc0_hwmod = {
.class = &am33xx_tptc_hwmod_class,
.clkdm_name = "l3_clkdm",
.mpu_irqs = am33xx_tptc0_irqs,
.flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
.main_clk = "l3_gclk",
.prcm = {
.omap4 = {
@ -2496,7 +2556,6 @@ static struct omap_hwmod_addr_space am33xx_cpgmac0_addr_space[] = {
{
.pa_start = 0x4a100000,
.pa_end = 0x4a100000 + SZ_2K - 1,
.flags = ADDR_TYPE_RT,
},
/* cpsw wr */
{
@ -2547,162 +2606,202 @@ static struct omap_hwmod_ocp_if am33xx_l4_ls__elm = {
.user = OCP_USER_MPU,
};
/*
* Splitting the resources to handle access of PWMSS config space
* and module specific part independently
*/
static struct omap_hwmod_addr_space am33xx_ehrpwm0_addr_space[] = {
static struct omap_hwmod_addr_space am33xx_epwmss0_addr_space[] = {
{
.pa_start = 0x48300000,
.pa_end = 0x48300000 + SZ_16 - 1,
.flags = ADDR_TYPE_RT
},
{
.pa_start = 0x48300200,
.pa_end = 0x48300200 + SZ_256 - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_l4_ls__ehrpwm0 = {
static struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss0 = {
.master = &am33xx_l4_ls_hwmod,
.slave = &am33xx_ehrpwm0_hwmod,
.slave = &am33xx_epwmss0_hwmod,
.clk = "l4ls_gclk",
.addr = am33xx_ehrpwm0_addr_space,
.addr = am33xx_epwmss0_addr_space,
.user = OCP_USER_MPU,
};
/*
* Splitting the resources to handle access of PWMSS config space
* and module specific part independently
*/
static struct omap_hwmod_addr_space am33xx_ehrpwm1_addr_space[] = {
{
.pa_start = 0x48302000,
.pa_end = 0x48302000 + SZ_16 - 1,
.flags = ADDR_TYPE_RT
},
{
.pa_start = 0x48302200,
.pa_end = 0x48302200 + SZ_256 - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_l4_ls__ehrpwm1 = {
.master = &am33xx_l4_ls_hwmod,
.slave = &am33xx_ehrpwm1_hwmod,
.clk = "l4ls_gclk",
.addr = am33xx_ehrpwm1_addr_space,
.user = OCP_USER_MPU,
};
/*
* Splitting the resources to handle access of PWMSS config space
* and module specific part independently
*/
static struct omap_hwmod_addr_space am33xx_ehrpwm2_addr_space[] = {
{
.pa_start = 0x48304000,
.pa_end = 0x48304000 + SZ_16 - 1,
.flags = ADDR_TYPE_RT
},
{
.pa_start = 0x48304200,
.pa_end = 0x48304200 + SZ_256 - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_l4_ls__ehrpwm2 = {
.master = &am33xx_l4_ls_hwmod,
.slave = &am33xx_ehrpwm2_hwmod,
.clk = "l4ls_gclk",
.addr = am33xx_ehrpwm2_addr_space,
.user = OCP_USER_MPU,
};
/*
* Splitting the resources to handle access of PWMSS config space
* and module specific part independently
*/
static struct omap_hwmod_addr_space am33xx_ecap0_addr_space[] = {
{
.pa_start = 0x48300000,
.pa_end = 0x48300000 + SZ_16 - 1,
.flags = ADDR_TYPE_RT
},
{
.pa_start = 0x48300100,
.pa_end = 0x48300100 + SZ_256 - 1,
.flags = ADDR_TYPE_RT
.pa_end = 0x48300100 + SZ_128 - 1,
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_l4_ls__ecap0 = {
.master = &am33xx_l4_ls_hwmod,
static struct omap_hwmod_ocp_if am33xx_epwmss0__ecap0 = {
.master = &am33xx_epwmss0_hwmod,
.slave = &am33xx_ecap0_hwmod,
.clk = "l4ls_gclk",
.addr = am33xx_ecap0_addr_space,
.user = OCP_USER_MPU,
};
/*
* Splitting the resources to handle access of PWMSS config space
* and module specific part independently
*/
static struct omap_hwmod_addr_space am33xx_ecap1_addr_space[] = {
static struct omap_hwmod_addr_space am33xx_eqep0_addr_space[] = {
{
.pa_start = 0x48300180,
.pa_end = 0x48300180 + SZ_128 - 1,
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_epwmss0__eqep0 = {
.master = &am33xx_epwmss0_hwmod,
.slave = &am33xx_eqep0_hwmod,
.clk = "l4ls_gclk",
.addr = am33xx_eqep0_addr_space,
.user = OCP_USER_MPU,
};
static struct omap_hwmod_addr_space am33xx_ehrpwm0_addr_space[] = {
{
.pa_start = 0x48300200,
.pa_end = 0x48300200 + SZ_128 - 1,
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_epwmss0__ehrpwm0 = {
.master = &am33xx_epwmss0_hwmod,
.slave = &am33xx_ehrpwm0_hwmod,
.clk = "l4ls_gclk",
.addr = am33xx_ehrpwm0_addr_space,
.user = OCP_USER_MPU,
};
static struct omap_hwmod_addr_space am33xx_epwmss1_addr_space[] = {
{
.pa_start = 0x48302000,
.pa_end = 0x48302000 + SZ_16 - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss1 = {
.master = &am33xx_l4_ls_hwmod,
.slave = &am33xx_epwmss1_hwmod,
.clk = "l4ls_gclk",
.addr = am33xx_epwmss1_addr_space,
.user = OCP_USER_MPU,
};
static struct omap_hwmod_addr_space am33xx_ecap1_addr_space[] = {
{
.pa_start = 0x48302100,
.pa_end = 0x48302100 + SZ_256 - 1,
.flags = ADDR_TYPE_RT
.pa_end = 0x48302100 + SZ_128 - 1,
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_l4_ls__ecap1 = {
.master = &am33xx_l4_ls_hwmod,
static struct omap_hwmod_ocp_if am33xx_epwmss1__ecap1 = {
.master = &am33xx_epwmss1_hwmod,
.slave = &am33xx_ecap1_hwmod,
.clk = "l4ls_gclk",
.addr = am33xx_ecap1_addr_space,
.user = OCP_USER_MPU,
};
/*
* Splitting the resources to handle access of PWMSS config space
* and module specific part independently
*/
static struct omap_hwmod_addr_space am33xx_ecap2_addr_space[] = {
static struct omap_hwmod_addr_space am33xx_eqep1_addr_space[] = {
{
.pa_start = 0x48302180,
.pa_end = 0x48302180 + SZ_128 - 1,
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_epwmss1__eqep1 = {
.master = &am33xx_epwmss1_hwmod,
.slave = &am33xx_eqep1_hwmod,
.clk = "l4ls_gclk",
.addr = am33xx_eqep1_addr_space,
.user = OCP_USER_MPU,
};
static struct omap_hwmod_addr_space am33xx_ehrpwm1_addr_space[] = {
{
.pa_start = 0x48302200,
.pa_end = 0x48302200 + SZ_128 - 1,
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_epwmss1__ehrpwm1 = {
.master = &am33xx_epwmss1_hwmod,
.slave = &am33xx_ehrpwm1_hwmod,
.clk = "l4ls_gclk",
.addr = am33xx_ehrpwm1_addr_space,
.user = OCP_USER_MPU,
};
static struct omap_hwmod_addr_space am33xx_epwmss2_addr_space[] = {
{
.pa_start = 0x48304000,
.pa_end = 0x48304000 + SZ_16 - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss2 = {
.master = &am33xx_l4_ls_hwmod,
.slave = &am33xx_epwmss2_hwmod,
.clk = "l4ls_gclk",
.addr = am33xx_epwmss2_addr_space,
.user = OCP_USER_MPU,
};
static struct omap_hwmod_addr_space am33xx_ecap2_addr_space[] = {
{
.pa_start = 0x48304100,
.pa_end = 0x48304100 + SZ_256 - 1,
.flags = ADDR_TYPE_RT
.pa_end = 0x48304100 + SZ_128 - 1,
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_l4_ls__ecap2 = {
.master = &am33xx_l4_ls_hwmod,
static struct omap_hwmod_ocp_if am33xx_epwmss2__ecap2 = {
.master = &am33xx_epwmss2_hwmod,
.slave = &am33xx_ecap2_hwmod,
.clk = "l4ls_gclk",
.addr = am33xx_ecap2_addr_space,
.user = OCP_USER_MPU,
};
static struct omap_hwmod_addr_space am33xx_eqep2_addr_space[] = {
{
.pa_start = 0x48304180,
.pa_end = 0x48304180 + SZ_128 - 1,
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_epwmss2__eqep2 = {
.master = &am33xx_epwmss2_hwmod,
.slave = &am33xx_eqep2_hwmod,
.clk = "l4ls_gclk",
.addr = am33xx_eqep2_addr_space,
.user = OCP_USER_MPU,
};
static struct omap_hwmod_addr_space am33xx_ehrpwm2_addr_space[] = {
{
.pa_start = 0x48304200,
.pa_end = 0x48304200 + SZ_128 - 1,
},
{ }
};
static struct omap_hwmod_ocp_if am33xx_epwmss2__ehrpwm2 = {
.master = &am33xx_epwmss2_hwmod,
.slave = &am33xx_ehrpwm2_hwmod,
.clk = "l4ls_gclk",
.addr = am33xx_ehrpwm2_addr_space,
.user = OCP_USER_MPU,
};
/* l3s cfg -> gpmc */
static struct omap_hwmod_addr_space am33xx_gpmc_addr_space[] = {
{
@ -3328,6 +3427,13 @@ static struct omap_hwmod_ocp_if am33xx_l3_s__usbss = {
.flags = OCPIF_SWSUP_IDLE,
};
/* l3 main -> ocmc */
static struct omap_hwmod_ocp_if am33xx_l3_main__ocmc = {
.master = &am33xx_l3_main_hwmod,
.slave = &am33xx_ocmcram_hwmod,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
&am33xx_l4_fw__emif_fw,
&am33xx_l3_main__emif,
@ -3385,12 +3491,18 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
&am33xx_l4_ls__uart6,
&am33xx_l4_ls__spinlock,
&am33xx_l4_ls__elm,
&am33xx_l4_ls__ehrpwm0,
&am33xx_l4_ls__ehrpwm1,
&am33xx_l4_ls__ehrpwm2,
&am33xx_l4_ls__ecap0,
&am33xx_l4_ls__ecap1,
&am33xx_l4_ls__ecap2,
&am33xx_l4_ls__epwmss0,
&am33xx_epwmss0__ecap0,
&am33xx_epwmss0__eqep0,
&am33xx_epwmss0__ehrpwm0,
&am33xx_l4_ls__epwmss1,
&am33xx_epwmss1__ecap1,
&am33xx_epwmss1__eqep1,
&am33xx_epwmss1__ehrpwm1,
&am33xx_l4_ls__epwmss2,
&am33xx_epwmss2__ecap2,
&am33xx_epwmss2__eqep2,
&am33xx_epwmss2__ehrpwm2,
&am33xx_l3_s__gpmc,
&am33xx_l3_main__lcdc,
&am33xx_l4_ls__mcspi0,
@ -3398,6 +3510,7 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
&am33xx_l3_main__tptc0,
&am33xx_l3_main__tptc1,
&am33xx_l3_main__tptc2,
&am33xx_l3_main__ocmc,
&am33xx_l3_s__usbss,
&am33xx_l4_hs__cpgmac0,
&am33xx_cpgmac0__mdio,

7
arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
View file

@ -3493,7 +3493,12 @@ static struct omap_hwmod am35xx_emac_hwmod = {
.name = "davinci_emac",
.mpu_irqs = am35xx_emac_mpu_irqs,
.class = &am35xx_emac_class,
.flags = HWMOD_NO_IDLEST,
/*
* According to Mark Greer, the MPU will not return from WFI
* when the EMAC signals an interrupt.
* http://www.spinics.net/lists/arm-kernel/msg174734.html
*/
.flags = (HWMOD_NO_IDLEST | HWMOD_BLOCK_WFI),
};
/* l3_core -> davinci emac interface */

51
arch/arm/mach-omap2/omap_hwmod_44xx_data.c
View file

@ -322,6 +322,7 @@ static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
.name = "aess",
.sysc = &omap44xx_aess_sysc,
.enable_preprogram = omap_hwmod_aess_preprogram,
};
/* aess */
@ -348,7 +349,7 @@ static struct omap_hwmod omap44xx_aess_hwmod = {
.clkdm_name = "abe_clkdm",
.mpu_irqs = omap44xx_aess_irqs,
.sdma_reqs = omap44xx_aess_sdma_reqs,
.main_clk = "aess_fck",
.main_clk = "aess_fclk",
.prcm = {
.omap4 = {
.clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET,
@ -4241,6 +4242,27 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc = {
static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
{
.name = "dmem",
.pa_start = 0x40180000,
.pa_end = 0x4018ffff
},
{
.name = "cmem",
.pa_start = 0x401a0000,
.pa_end = 0x401a1fff
},
{
.name = "smem",
.pa_start = 0x401c0000,
.pa_end = 0x401c5fff
},
{
.name = "pmem",
.pa_start = 0x401e0000,
.pa_end = 0x401e1fff
},
{
.name = "mpu",
.pa_start = 0x401f1000,
.pa_end = 0x401f13ff,
.flags = ADDR_TYPE_RT
@ -4259,6 +4281,27 @@ static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess = {
static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
{
.name = "dmem_dma",
.pa_start = 0x49080000,
.pa_end = 0x4908ffff
},
{
.name = "cmem_dma",
.pa_start = 0x490a0000,
.pa_end = 0x490a1fff
},
{
.name = "smem_dma",
.pa_start = 0x490c0000,
.pa_end = 0x490c5fff
},
{
.name = "pmem_dma",
.pa_start = 0x490e0000,
.pa_end = 0x490e1fff
},
{
.name = "dma",
.pa_start = 0x490f1000,
.pa_end = 0x490f13ff,
.flags = ADDR_TYPE_RT
@ -6268,7 +6311,7 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
&omap44xx_l3_main_1__l3_main_3,
&omap44xx_l3_main_2__l3_main_3,
&omap44xx_l4_cfg__l3_main_3,
/* &omap44xx_aess__l4_abe, */
&omap44xx_aess__l4_abe,
&omap44xx_dsp__l4_abe,
&omap44xx_l3_main_1__l4_abe,
&omap44xx_mpu__l4_abe,
@ -6277,8 +6320,8 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
&omap44xx_l4_cfg__l4_wkup,
&omap44xx_mpu__mpu_private,
&omap44xx_l4_cfg__ocp_wp_noc,
/* &omap44xx_l4_abe__aess, */
/* &omap44xx_l4_abe__aess_dma, */
&omap44xx_l4_abe__aess,
&omap44xx_l4_abe__aess_dma,
&omap44xx_l3_main_2__c2c,
&omap44xx_l4_wkup__counter_32k,
&omap44xx_l4_cfg__ctrl_module_core,

53
arch/arm/mach-omap2/omap_hwmod_reset.c Normal file
View file

@ -0,0 +1,53 @@
/*
* OMAP IP block custom reset and preprogramming stubs
*
* Copyright (C) 2012 Texas Instruments, Inc.
* Paul Walmsley
*
* A small number of IP blocks need custom reset and preprogramming
* functions. The stubs in this file provide a standard way for the
* hwmod code to call these functions, which are to be located under
* drivers/.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
* 02110-1301 USA
*/
#include <linux/kernel.h>
#include <linux/errno.h>
#include <sound/aess.h>
#include "omap_hwmod.h"
/**
* omap_hwmod_aess_preprogram - enable AESS internal autogating
* @oh: struct omap_hwmod *
*
* The AESS will not IdleAck to the PRCM until its internal autogating
* is enabled. Since internal autogating is disabled by default after
* AESS reset, we must enable autogating after the hwmod code resets
* the AESS. Returns 0.
*/
int omap_hwmod_aess_preprogram(struct omap_hwmod *oh)
{
void __iomem *va;
va = omap_hwmod_get_mpu_rt_va(oh);
if (!va)
return -EINVAL;
aess_enable_autogating(va);
return 0;
}

20
arch/arm/mach-omap2/pm.c
View file

@ -282,19 +282,19 @@ int __init omap2_common_pm_late_init(void)
* a completely different mechanism.
* Disable this part if a DT blob is available.
*/
if (of_have_populated_dt())
return 0;
if (!of_have_populated_dt()) {
/* Init the voltage layer */
omap_pmic_late_init();
omap_voltage_late_init();
/* Init the voltage layer */
omap_pmic_late_init();
omap_voltage_late_init();
/* Initialize the voltages */
omap3_init_voltages();
omap4_init_voltages();
/* Initialize the voltages */
omap3_init_voltages();
omap4_init_voltages();
/* Smartreflex device init */
omap_devinit_smartreflex();
/* Smartreflex device init */
omap_devinit_smartreflex();
}
#ifdef CONFIG_SUSPEND
suspend_set_ops(&omap_pm_ops);

12
arch/arm/mach-omap2/pm24xx.c
View file

@ -54,7 +54,6 @@
#include "powerdomain.h"
#include "clockdomain.h"
static void (*omap2_sram_idle)(void);
static void (*omap2_sram_suspend)(u32 dllctrl, void __iomem *sdrc_dlla_ctrl,
void __iomem *sdrc_power);
@ -163,6 +162,8 @@ static int omap2_allow_mpu_retention(void)
static void omap2_enter_mpu_retention(void)
{
const int zero = 0;
/* The peripherals seem not to be able to wake up the MPU when
* it is in retention mode. */
if (omap2_allow_mpu_retention()) {
@ -179,7 +180,8 @@ static void omap2_enter_mpu_retention(void)
pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
}
omap2_sram_idle();
/* WFI */
asm("mcr p15, 0, %0, c7, c0, 4" : : "r" (zero) : "memory", "cc");
pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
}
@ -333,11 +335,9 @@ int __init omap2_pm_init(void)
/*
* We copy the assembler sleep/wakeup routines to SRAM.
* These routines need to be in SRAM as that's the only
* memory the MPU can see when it wakes up.
* memory the MPU can see when it wakes up after the entire
* chip enters idle.
*/
omap2_sram_idle = omap_sram_push(omap24xx_idle_loop_suspend,
omap24xx_idle_loop_suspend_sz);
omap2_sram_suspend = omap_sram_push(omap24xx_cpu_suspend,
omap24xx_cpu_suspend_sz);

21
arch/arm/mach-omap2/pm44xx.c
View file

@ -77,10 +77,20 @@ static int omap4_pm_suspend(void)
omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
pwrdm_set_logic_retst(pwrst->pwrdm, pwrst->saved_logic_state);
}
if (ret)
if (ret) {
pr_crit("Could not enter target state in pm_suspend\n");
else
/*
* OMAP4 chip PM currently works only with certain (newer)
* versions of bootloaders. This is due to missing code in the
* kernel to properly reset and initialize some devices.
* Warn the user about the bootloader version being one of the
* possible causes.
* http://www.spinics.net/lists/arm-kernel/msg218641.html
*/
pr_warn("A possible cause could be an old bootloader - try u-boot >= v2012.07\n");
} else {
pr_info("Successfully put all powerdomains to target state\n");
}
return 0;
}
@ -146,6 +156,13 @@ int __init omap4_pm_init(void)
}
pr_err("Power Management for TI OMAP4.\n");
/*
* OMAP4 chip PM currently works only with certain (newer)
* versions of bootloaders. This is due to missing code in the
* kernel to properly reset and initialize some devices.
* http://www.spinics.net/lists/arm-kernel/msg218641.html
*/
pr_warn("OMAP4 PM: u-boot >= v2012.07 is required for full PM support\n");
ret = pwrdm_for_each(pwrdms_setup, NULL);
if (ret) {

15
arch/arm/mach-omap2/prm33xx.c
View file

@ -110,11 +110,11 @@ int am33xx_prm_assert_hardreset(u8 shift, s16 inst, u16 rstctrl_offs)
* -EINVAL upon an argument error, -EEXIST if the submodule was already out
* of reset, or -EBUSY if the submodule did not exit reset promptly.
*/
int am33xx_prm_deassert_hardreset(u8 shift, s16 inst,
int am33xx_prm_deassert_hardreset(u8 shift, u8 st_shift, s16 inst,
u16 rstctrl_offs, u16 rstst_offs)
{
int c;
u32 mask = 1 << shift;
u32 mask = 1 << st_shift;
/* Check the current status to avoid de-asserting the line twice */
if (am33xx_prm_is_hardreset_asserted(shift, inst, rstctrl_offs) == 0)
@ -122,11 +122,14 @@ int am33xx_prm_deassert_hardreset(u8 shift, s16 inst,
/* Clear the reset status by writing 1 to the status bit */
am33xx_prm_rmw_reg_bits(0xffffffff, mask, inst, rstst_offs);
/* de-assert the reset control line */
am33xx_prm_rmw_reg_bits(mask, 0, inst, rstctrl_offs);
/* wait the status to be set */
omap_test_timeout(am33xx_prm_is_hardreset_asserted(shift, inst,
/* de-assert the reset control line */
mask = 1 << shift;
am33xx_prm_rmw_reg_bits(mask, 0, inst, rstctrl_offs);
/* wait the status to be set */
omap_test_timeout(am33xx_prm_is_hardreset_asserted(st_shift, inst,
rstst_offs),
MAX_MODULE_HARDRESET_WAIT, c);

4
arch/arm/mach-omap2/prm33xx.h
View file

@ -117,6 +117,7 @@
#define AM33XX_PM_CEFUSE_PWRSTST_OFFSET 0x0004
#define AM33XX_PM_CEFUSE_PWRSTST AM33XX_PRM_REGADDR(AM33XX_PRM_CEFUSE_MOD, 0x0004)
#ifndef __ASSEMBLER__
extern u32 am33xx_prm_read_reg(s16 inst, u16 idx);
extern void am33xx_prm_write_reg(u32 val, s16 inst, u16 idx);
extern u32 am33xx_prm_rmw_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
@ -124,6 +125,7 @@ extern void am33xx_prm_global_warm_sw_reset(void);
extern int am33xx_prm_is_hardreset_asserted(u8 shift, s16 inst,
u16 rstctrl_offs);
extern int am33xx_prm_assert_hardreset(u8 shift, s16 inst, u16 rstctrl_offs);
extern int am33xx_prm_deassert_hardreset(u8 shift, s16 inst,
extern int am33xx_prm_deassert_hardreset(u8 shift, u8 st_shift, s16 inst,
u16 rstctrl_offs, u16 rstst_offs);
#endif /* ASSEMBLER */
#endif

19
arch/arm/mach-omap2/sleep24xx.S
View file

@ -36,25 +36,6 @@
.text
/*
* Forces OMAP into idle state
*
* omap24xx_idle_loop_suspend() - This bit of code just executes the WFI
* for normal idles.
*
* Note: This code get's copied to internal SRAM at boot. When the OMAP
* wakes up it continues execution at the point it went to sleep.
*/
.align 3
ENTRY(omap24xx_idle_loop_suspend)
stmfd sp!, {r0, lr} @ save registers on stack
mov r0, #0 @ clear for mcr setup
mcr p15, 0, r0, c7, c0, 4 @ wait for interrupt
ldmfd sp!, {r0, pc} @ restore regs and return
ENTRY(omap24xx_idle_loop_suspend_sz)
.word . - omap24xx_idle_loop_suspend
/*
* omap24xx_cpu_suspend() - Forces OMAP into deep sleep state by completing
* SDRC shutdown then ARM shutdown. Upon wake MPU is back on so just restore

1
arch/arm/mach-omap2/soc.h
View file

@ -395,6 +395,7 @@ IS_OMAP_TYPE(3430, 0x3430)
#define AM335X_CLASS 0x33500033
#define AM335X_REV_ES1_0 AM335X_CLASS
#define AM335X_REV_ES2_0 (AM335X_CLASS | (0x1 << 8))
#define OMAP443X_CLASS 0x44300044
#define OMAP4430_REV_ES1_0 (OMAP443X_CLASS | (0x10 << 8))

2
arch/arm/mach-omap2/sr_device.c
View file

@ -152,7 +152,7 @@ static int __init sr_dev_init(struct omap_hwmod *oh, void *user)
sr_data->enable_on_init = sr_enable_on_init;
pdev = omap_device_build(name, i, oh, sr_data, sizeof(*sr_data), 0);
pdev = omap_device_build(name, i, oh, sr_data, sizeof(*sr_data));
if (IS_ERR(pdev))
pr_warning("%s: Could not build omap_device for %s: %s.\n\n",
__func__, name, oh->name);

9
arch/arm/plat-omap/Kconfig
View file

@ -147,15 +147,6 @@ config OMAP3_L2_AUX_SECURE_SERVICE_SET_ID
help
PPA routine service ID for setting L2 auxiliary control register.
config OMAP_32K_TIMER_HZ
int "Kernel internal timer frequency for 32KHz timer"
range 32 1024
depends on OMAP_32K_TIMER
default "128"
help
Kernel internal timer frequency should be a divisor of 32768,
such as 64 or 128.
config OMAP_DM_TIMER
bool "Use dual-mode timer"
depends on ARCH_OMAP16XX || ARCH_OMAP2PLUS

8
arch/arm/plat-omap/include/plat/timex.h
View file

@ -28,14 +28,6 @@
#if !defined(__ASM_ARCH_OMAP_TIMEX_H)
#define __ASM_ARCH_OMAP_TIMEX_H
/*
* OMAP 32KHz timer updates time one jiffie at a time from a secondary timer,
* and that's why the CLOCK_TICK_RATE is not 32768.
*/
#ifdef CONFIG_OMAP_32K_TIMER
#define CLOCK_TICK_RATE (CONFIG_OMAP_32K_TIMER_HZ)
#else
#define CLOCK_TICK_RATE (HZ * 100000UL)
#endif
#endif /* __ASM_ARCH_OMAP_TIMEX_H */

18
drivers/media/platform/omap3isp/isp.c
View file

@ -1338,28 +1338,15 @@ static int isp_enable_clocks(struct isp_device *isp)
{
int r;
unsigned long rate;
int divisor;
/*
* cam_mclk clock chain:
* dpll4 -> dpll4_m5 -> dpll4_m5x2 -> cam_mclk
*
* In OMAP3630 dpll4_m5x2 != 2 x dpll4_m5 but both are
* set to the same value. Hence the rate set for dpll4_m5
* has to be twice of what is set on OMAP3430 to get
* the required value for cam_mclk
*/
divisor = isp->revision == ISP_REVISION_15_0 ? 1 : 2;
r = clk_prepare_enable(isp->clock[ISP_CLK_CAM_ICK]);
if (r) {
dev_err(isp->dev, "failed to enable cam_ick clock\n");
goto out_clk_enable_ick;
}
r = clk_set_rate(isp->clock[ISP_CLK_DPLL4_M5_CK],
CM_CAM_MCLK_HZ/divisor);
r = clk_set_rate(isp->clock[ISP_CLK_CAM_MCLK], CM_CAM_MCLK_HZ);
if (r) {
dev_err(isp->dev, "clk_set_rate for dpll4_m5_ck failed\n");
dev_err(isp->dev, "clk_set_rate for cam_mclk failed\n");
goto out_clk_enable_mclk;
}
r = clk_prepare_enable(isp->clock[ISP_CLK_CAM_MCLK]);
@ -1401,7 +1388,6 @@ static void isp_disable_clocks(struct isp_device *isp)
static const char *isp_clocks[] = {
"cam_ick",
"cam_mclk",
"dpll4_m5_ck",
"csi2_96m_fck",
"l3_ick",
};

8
drivers/media/platform/omap3isp/isp.h
View file

@ -147,7 +147,6 @@ struct isp_platform_callback {
* @ref_count: Reference count for handling multiple ISP requests.
* @cam_ick: Pointer to camera interface clock structure.
* @cam_mclk: Pointer to camera functional clock structure.
* @dpll4_m5_ck: Pointer to DPLL4 M5 clock structure.
* @csi2_fck: Pointer to camera CSI2 complexIO clock structure.
* @l3_ick: Pointer to OMAP3 L3 bus interface clock.
* @irq: Currently attached ISP ISR callbacks information structure.
@ -189,10 +188,9 @@ struct isp_device {
u32 xclk_divisor[2]; /* Two clocks, a and b. */
#define ISP_CLK_CAM_ICK 0
#define ISP_CLK_CAM_MCLK 1
#define ISP_CLK_DPLL4_M5_CK 2
#define ISP_CLK_CSI2_FCK 3
#define ISP_CLK_L3_ICK 4
struct clk *clock[5];
#define ISP_CLK_CSI2_FCK 2
#define ISP_CLK_L3_ICK 3
struct clk *clock[4];
/* ISP modules */
struct ispstat isp_af;

53
include/sound/aess.h Normal file
View file

@ -0,0 +1,53 @@
/*
* AESS IP block reset
*
* Copyright (C) 2012 Texas Instruments, Inc.
* Paul Walmsley
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
* 02110-1301 USA
*/
#ifndef __SOUND_AESS_H__
#define __SOUND_AESS_H__
#include <linux/kernel.h>
#include <linux/io.h>
/*
* AESS_AUTO_GATING_ENABLE_OFFSET: offset in bytes of the AESS IP
* block's AESS_AUTO_GATING_ENABLE__1 register from the IP block's
* base address
*/
#define AESS_AUTO_GATING_ENABLE_OFFSET 0x07c
/* Register bitfields in the AESS_AUTO_GATING_ENABLE__1 register */
#define AESS_AUTO_GATING_ENABLE_SHIFT 0
/**
* aess_enable_autogating - enable AESS internal autogating
* @oh: struct omap_hwmod *
*
* Enable internal autogating on the AESS. This allows the AESS to
* indicate that it is idle to the OMAP PRCM. Returns 0.
*/
static inline void aess_enable_autogating(void __iomem *base)
{
u32 v;
/* Set AESS_AUTO_GATING_ENABLE__1.ENABLE to allow idle entry */
v = 1 << AESS_AUTO_GATING_ENABLE_SHIFT;
writel(v, base + AESS_AUTO_GATING_ENABLE_OFFSET);
}
#endif /* __SOUND_AESS_H__ */