clk: davinci: pll: allow dev == NULL
This modifies the TI Davinci PLL clock driver to allow for the case when dev == NULL. On some (most) SoCs that use this driver, the PLL clock needs to be registered during early boot because it is used for clocksource/clkevent and there will be no platform device available. Signed-off-by: David Lechner <david@lechnology.com> Reviewed-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/20180525181150.17873-7-david@lechnology.com
This commit is contained in:
David Lechner
Michael Turquette
parent
9c39fc1fe8
commit
76c9dd9dbd
9 changed files with 259 additions and 137 deletions
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@ -6,6 +6,7 @@
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*/
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#include <linux/clkdev.h>
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#include <linux/clk/davinci.h>
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#include <linux/bitops.h>
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#include <linux/init.h>
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#include <linux/types.h>
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@ -36,11 +37,11 @@ SYSCLK(5, pll0_sysclk5, pll0_pllen, 5, 0);
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SYSCLK(6, pll0_sysclk6, pll0_pllen, 5, SYSCLK_FIXED_DIV);
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SYSCLK(7, pll0_sysclk7, pll0_pllen, 5, 0);
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int da830_pll_init(struct device *dev, void __iomem *base)
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int da830_pll_init(struct device *dev, void __iomem *base, struct regmap *cfgchip)
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{
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struct clk *clk;
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davinci_pll_clk_register(dev, &da830_pll_info, "ref_clk", base);
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davinci_pll_clk_register(dev, &da830_pll_info, "ref_clk", base, cfgchip);
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clk = davinci_pll_sysclk_register(dev, &pll0_sysclk2, base);
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clk_register_clkdev(clk, "pll0_sysclk2", "da830-psc0");
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@ -7,7 +7,9 @@
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#include <linux/bitops.h>
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#include <linux/clk-provider.h>
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#include <linux/clk/davinci.h>
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#include <linux/clkdev.h>
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#include <linux/device.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/mfd/da8xx-cfgchip.h>
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@ -81,11 +83,11 @@ static const struct davinci_pll_obsclk_info da850_pll0_obsclk_info = {
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.ocsrc_mask = GENMASK(4, 0),
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};
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int da850_pll0_init(struct device *dev, void __iomem *base)
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int da850_pll0_init(struct device *dev, void __iomem *base, struct regmap *cfgchip)
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{
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struct clk *clk;
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davinci_pll_clk_register(dev, &da850_pll0_info, "ref_clk", base);
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davinci_pll_clk_register(dev, &da850_pll0_info, "ref_clk", base, cfgchip);
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clk = davinci_pll_sysclk_register(dev, &pll0_sysclk1, base);
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clk_register_clkdev(clk, "pll0_sysclk1", "da850-psc0");
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@ -134,11 +136,11 @@ static const struct davinci_pll_sysclk_info *da850_pll0_sysclk_info[] = {
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NULL
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};
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int of_da850_pll0_init(struct device *dev, void __iomem *base)
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int of_da850_pll0_init(struct device *dev, void __iomem *base, struct regmap *cfgchip)
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{
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return of_davinci_pll_init(dev, &da850_pll0_info,
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return of_davinci_pll_init(dev, dev->of_node, &da850_pll0_info,
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&da850_pll0_obsclk_info,
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da850_pll0_sysclk_info, 7, base);
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da850_pll0_sysclk_info, 7, base, cfgchip);
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}
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static const struct davinci_pll_clk_info da850_pll1_info = {
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@ -179,11 +181,11 @@ static const struct davinci_pll_obsclk_info da850_pll1_obsclk_info = {
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.ocsrc_mask = GENMASK(4, 0),
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};
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int da850_pll1_init(struct device *dev, void __iomem *base)
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int da850_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip)
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{
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struct clk *clk;
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davinci_pll_clk_register(dev, &da850_pll1_info, "oscin", base);
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davinci_pll_clk_register(dev, &da850_pll1_info, "oscin", base, cfgchip);
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davinci_pll_sysclk_register(dev, &pll1_sysclk1, base);
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@ -204,9 +206,9 @@ static const struct davinci_pll_sysclk_info *da850_pll1_sysclk_info[] = {
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NULL
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};
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int of_da850_pll1_init(struct device *dev, void __iomem *base)
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int of_da850_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip)
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{
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return of_davinci_pll_init(dev, &da850_pll1_info,
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return of_davinci_pll_init(dev, dev->of_node, &da850_pll1_info,
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&da850_pll1_obsclk_info,
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da850_pll1_sysclk_info, 3, base);
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da850_pll1_sysclk_info, 3, base, cfgchip);
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}
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@ -6,6 +6,7 @@
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*/
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#include <linux/bitops.h>
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#include <linux/clk/davinci.h>
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#include <linux/clkdev.h>
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#include <linux/init.h>
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#include <linux/types.h>
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@ -27,11 +28,11 @@ SYSCLK(2, pll1_sysclk2, pll1_pllen, 5, SYSCLK_FIXED_DIV | SYSCLK_ALWAYS_ENABLED)
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SYSCLK(3, pll1_sysclk3, pll1_pllen, 5, SYSCLK_ALWAYS_ENABLED);
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SYSCLK(4, pll1_sysclk4, pll1_pllen, 5, SYSCLK_ALWAYS_ENABLED);
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int dm355_pll1_init(struct device *dev, void __iomem *base)
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int dm355_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip)
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{
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struct clk *clk;
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davinci_pll_clk_register(dev, &dm355_pll1_info, "ref_clk", base);
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davinci_pll_clk_register(dev, &dm355_pll1_info, "ref_clk", base, cfgchip);
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clk = davinci_pll_sysclk_register(dev, &pll1_sysclk1, base);
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clk_register_clkdev(clk, "pll1_sysclk1", "dm355-psc");
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@ -64,9 +65,9 @@ static const struct davinci_pll_clk_info dm355_pll2_info = {
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SYSCLK(1, pll2_sysclk1, pll2_pllen, 5, SYSCLK_FIXED_DIV | SYSCLK_ALWAYS_ENABLED);
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int dm355_pll2_init(struct device *dev, void __iomem *base)
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int dm355_pll2_init(struct device *dev, void __iomem *base, struct regmap *cfgchip)
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{
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davinci_pll_clk_register(dev, &dm355_pll2_info, "oscin", base);
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davinci_pll_clk_register(dev, &dm355_pll2_info, "oscin", base, cfgchip);
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davinci_pll_sysclk_register(dev, &pll2_sysclk1, base);
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@ -7,6 +7,7 @@
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#include <linux/bitops.h>
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#include <linux/clkdev.h>
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#include <linux/clk/davinci.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/types.h>
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@ -56,11 +57,11 @@ static const struct davinci_pll_obsclk_info dm365_pll1_obsclk_info = {
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.ocsrc_mask = BIT(4),
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};
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int dm365_pll1_init(struct device *dev, void __iomem *base)
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int dm365_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip)
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{
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struct clk *clk;
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davinci_pll_clk_register(dev, &dm365_pll1_info, "ref_clk", base);
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davinci_pll_clk_register(dev, &dm365_pll1_info, "ref_clk", base, cfgchip);
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clk = davinci_pll_sysclk_register(dev, &pll1_sysclk1, base);
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clk_register_clkdev(clk, "pll1_sysclk1", "dm365-psc");
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@ -119,11 +120,11 @@ static const struct davinci_pll_obsclk_info dm365_pll2_obsclk_info = {
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.ocsrc_mask = BIT(4),
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};
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int dm365_pll2_init(struct device *dev, void __iomem *base)
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int dm365_pll2_init(struct device *dev, void __iomem *base, struct regmap *cfgchip)
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{
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struct clk *clk;
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davinci_pll_clk_register(dev, &dm365_pll2_info, "oscin", base);
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davinci_pll_clk_register(dev, &dm365_pll2_info, "oscin", base, cfgchip);
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davinci_pll_sysclk_register(dev, &pll2_sysclk1, base);
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@ -6,6 +6,7 @@
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*/
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#include <linux/bitops.h>
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#include <linux/clk/davinci.h>
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#include <linux/clkdev.h>
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#include <linux/init.h>
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#include <linux/types.h>
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@ -27,11 +28,11 @@ SYSCLK(2, pll1_sysclk2, pll1_pllen, 4, SYSCLK_FIXED_DIV);
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SYSCLK(3, pll1_sysclk3, pll1_pllen, 4, SYSCLK_FIXED_DIV);
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SYSCLK(5, pll1_sysclk5, pll1_pllen, 4, SYSCLK_FIXED_DIV);
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int dm644x_pll1_init(struct device *dev, void __iomem *base)
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int dm644x_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip)
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{
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struct clk *clk;
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davinci_pll_clk_register(dev, &dm644x_pll1_info, "ref_clk", base);
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davinci_pll_clk_register(dev, &dm644x_pll1_info, "ref_clk", base, cfgchip);
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clk = davinci_pll_sysclk_register(dev, &pll1_sysclk1, base);
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clk_register_clkdev(clk, "pll1_sysclk1", "dm644x-psc");
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@ -66,9 +67,9 @@ static const struct davinci_pll_clk_info dm644x_pll2_info = {
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SYSCLK(1, pll2_sysclk1, pll2_pllen, 4, 0);
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SYSCLK(2, pll2_sysclk2, pll2_pllen, 4, 0);
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int dm644x_pll2_init(struct device *dev, void __iomem *base)
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int dm644x_pll2_init(struct device *dev, void __iomem *base, struct regmap *cfgchip)
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{
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davinci_pll_clk_register(dev, &dm644x_pll2_info, "oscin", base);
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davinci_pll_clk_register(dev, &dm644x_pll2_info, "oscin", base, cfgchip);
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davinci_pll_sysclk_register(dev, &pll2_sysclk1, base);
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@ -6,6 +6,7 @@
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*/
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#include <linux/clk-provider.h>
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#include <linux/clk/davinci.h>
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#include <linux/clkdev.h>
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#include <linux/init.h>
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#include <linux/types.h>
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@ -29,11 +30,11 @@ SYSCLK(6, pll1_sysclk6, pll1_pllen, 4, 0);
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SYSCLK(8, pll1_sysclk8, pll1_pllen, 4, 0);
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SYSCLK(9, pll1_sysclk9, pll1_pllen, 4, 0);
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int dm646x_pll1_init(struct device *dev, void __iomem *base)
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int dm646x_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip)
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{
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struct clk *clk;
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davinci_pll_clk_register(dev, &dm646x_pll1_info, "ref_clk", base);
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davinci_pll_clk_register(dev, &dm646x_pll1_info, "ref_clk", base, cfgchip);
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clk = davinci_pll_sysclk_register(dev, &pll1_sysclk1, base);
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clk_register_clkdev(clk, "pll1_sysclk1", "dm646x-psc");
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@ -74,9 +75,9 @@ static const struct davinci_pll_clk_info dm646x_pll2_info = {
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SYSCLK(1, pll2_sysclk1, pll2_pllen, 4, SYSCLK_ALWAYS_ENABLED);
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int dm646x_pll2_init(struct device *dev, void __iomem *base)
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int dm646x_pll2_init(struct device *dev, void __iomem *base, struct regmap *cfgchip)
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{
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davinci_pll_clk_register(dev, &dm646x_pll2_info, "oscin", base);
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davinci_pll_clk_register(dev, &dm646x_pll2_info, "oscin", base, cfgchip);
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davinci_pll_sysclk_register(dev, &pll2_sysclk1, base);
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@ -11,6 +11,7 @@
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#include <linux/clk-provider.h>
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#include <linux/clk.h>
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#include <linux/clk/davinci.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/io.h>
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@ -223,6 +224,7 @@ static const struct clk_ops dm365_pll_ops = {
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/**
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* davinci_pll_div_register - common *DIV clock implementation
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* @dev: The PLL platform device or NULL
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* @name: the clock name
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* @parent_name: the parent clock name
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* @reg: the *DIV register
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@ -240,17 +242,21 @@ static struct clk *davinci_pll_div_register(struct device *dev,
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const struct clk_ops *divider_ops = &clk_divider_ops;
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struct clk_gate *gate;
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struct clk_divider *divider;
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struct clk *clk;
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int ret;
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gate = devm_kzalloc(dev, sizeof(*gate), GFP_KERNEL);
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gate = kzalloc(sizeof(*gate), GFP_KERNEL);
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if (!gate)
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return ERR_PTR(-ENOMEM);
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gate->reg = reg;
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gate->bit_idx = DIV_ENABLE_SHIFT;
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divider = devm_kzalloc(dev, sizeof(*divider), GFP_KERNEL);
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if (!divider)
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return ERR_PTR(-ENOMEM);
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divider = kzalloc(sizeof(*divider), GFP_KERNEL);
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if (!divider) {
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ret = -ENOMEM;
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goto err_free_gate;
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}
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divider->reg = reg;
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divider->shift = DIV_RATIO_SHIFT;
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@ -261,9 +267,22 @@ static struct clk *davinci_pll_div_register(struct device *dev,
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divider_ops = &clk_divider_ro_ops;
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}
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return clk_register_composite(dev, name, parent_names, num_parents,
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NULL, NULL, ÷r->hw, divider_ops,
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&gate->hw, &clk_gate_ops, flags);
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clk = clk_register_composite(dev, name, parent_names, num_parents,
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NULL, NULL, ÷r->hw, divider_ops,
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&gate->hw, &clk_gate_ops, flags);
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if (IS_ERR(clk)) {
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ret = PTR_ERR(clk);
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goto err_free_divider;
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}
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return clk;
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err_free_divider:
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kfree(divider);
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err_free_gate:
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kfree(gate);
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return ERR_PTR(ret);
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}
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struct davinci_pllen_clk {
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@ -321,36 +340,17 @@ static int davinci_pllen_rate_change(struct notifier_block *nb,
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return NOTIFY_OK;
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}
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static struct davinci_pll_platform_data *davinci_pll_get_pdata(struct device *dev)
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{
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struct davinci_pll_platform_data *pdata = dev_get_platdata(dev);
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/*
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* Platform data is optional, so allocate a new struct if one was not
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* provided. For device tree, this will always be the case.
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*/
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if (!pdata)
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pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
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if (!pdata)
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return NULL;
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/* for device tree, we need to fill in the struct */
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if (dev->of_node)
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pdata->cfgchip =
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syscon_regmap_lookup_by_compatible("ti,da830-cfgchip");
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return pdata;
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}
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static struct notifier_block davinci_pllen_notifier = {
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.notifier_call = davinci_pllen_rate_change,
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};
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/**
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* davinci_pll_clk_register - Register a PLL clock
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* @dev: The PLL platform device or NULL
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* @info: The device-specific clock info
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* @parent_name: The parent clock name
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* @base: The PLL's memory region
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* @cfgchip: CFGCHIP syscon regmap for info->unlock_reg or NULL
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*
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* This creates a series of clocks that represent the PLL.
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*
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@ -366,9 +366,9 @@ static struct notifier_block davinci_pllen_notifier = {
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struct clk *davinci_pll_clk_register(struct device *dev,
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const struct davinci_pll_clk_info *info,
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const char *parent_name,
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void __iomem *base)
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void __iomem *base,
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struct regmap *cfgchip)
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{
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struct davinci_pll_platform_data *pdata;
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char prediv_name[MAX_NAME_SIZE];
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char pllout_name[MAX_NAME_SIZE];
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char postdiv_name[MAX_NAME_SIZE];
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@ -376,11 +376,12 @@ struct clk *davinci_pll_clk_register(struct device *dev,
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struct clk_init_data init;
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struct davinci_pll_clk *pllout;
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struct davinci_pllen_clk *pllen;
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struct clk *pllout_clk, *clk;
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pdata = davinci_pll_get_pdata(dev);
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if (!pdata)
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return ERR_PTR(-ENOMEM);
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struct clk *oscin_clk = NULL;
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struct clk *prediv_clk = NULL;
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struct clk *pllout_clk;
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struct clk *postdiv_clk = NULL;
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struct clk *pllen_clk;
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int ret;
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if (info->flags & PLL_HAS_CLKMODE) {
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/*
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@ -392,10 +393,10 @@ struct clk *davinci_pll_clk_register(struct device *dev,
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* a number of different things. In this driver we use it to
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* mean the signal after the PLLCTL[CLKMODE] switch.
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*/
|
||||
clk = clk_register_fixed_factor(dev, OSCIN_CLK_NAME,
|
||||
parent_name, 0, 1, 1);
|
||||
if (IS_ERR(clk))
|
||||
return clk;
|
||||
oscin_clk = clk_register_fixed_factor(dev, OSCIN_CLK_NAME,
|
||||
parent_name, 0, 1, 1);
|
||||
if (IS_ERR(oscin_clk))
|
||||
return oscin_clk;
|
||||
|
||||
parent_name = OSCIN_CLK_NAME;
|
||||
}
|
||||
|
|
@ -411,30 +412,34 @@ struct clk *davinci_pll_clk_register(struct device *dev,
|
|||
|
||||
/* Some? DM355 chips don't correctly report the PREDIV value */
|
||||
if (info->flags & PLL_PREDIV_FIXED8)
|
||||
clk = clk_register_fixed_factor(dev, prediv_name,
|
||||
parent_name, flags, 1, 8);
|
||||
prediv_clk = clk_register_fixed_factor(dev, prediv_name,
|
||||
parent_name, flags, 1, 8);
|
||||
else
|
||||
clk = davinci_pll_div_register(dev, prediv_name,
|
||||
prediv_clk = davinci_pll_div_register(dev, prediv_name,
|
||||
parent_name, base + PREDIV, fixed, flags);
|
||||
if (IS_ERR(clk))
|
||||
return clk;
|
||||
if (IS_ERR(prediv_clk)) {
|
||||
ret = PTR_ERR(prediv_clk);
|
||||
goto err_unregister_oscin;
|
||||
}
|
||||
|
||||
parent_name = prediv_name;
|
||||
}
|
||||
|
||||
/* Unlock writing to PLL registers */
|
||||
if (info->unlock_reg) {
|
||||
if (IS_ERR_OR_NULL(pdata->cfgchip))
|
||||
if (IS_ERR_OR_NULL(cfgchip))
|
||||
dev_warn(dev, "Failed to get CFGCHIP (%ld)\n",
|
||||
PTR_ERR(pdata->cfgchip));
|
||||
PTR_ERR(cfgchip));
|
||||
else
|
||||
regmap_write_bits(pdata->cfgchip, info->unlock_reg,
|
||||
regmap_write_bits(cfgchip, info->unlock_reg,
|
||||
info->unlock_mask, 0);
|
||||
}
|
||||
|
||||
pllout = devm_kzalloc(dev, sizeof(*pllout), GFP_KERNEL);
|
||||
if (!pllout)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
pllout = kzalloc(sizeof(*pllout), GFP_KERNEL);
|
||||
if (!pllout) {
|
||||
ret = -ENOMEM;
|
||||
goto err_unregister_prediv;
|
||||
}
|
||||
|
||||
snprintf(pllout_name, MAX_NAME_SIZE, "%s_pllout", info->name);
|
||||
|
||||
|
|
@ -456,9 +461,11 @@ struct clk *davinci_pll_clk_register(struct device *dev,
|
|||
pllout->pllm_min = info->pllm_min;
|
||||
pllout->pllm_max = info->pllm_max;
|
||||
|
||||
pllout_clk = devm_clk_register(dev, &pllout->hw);
|
||||
if (IS_ERR(pllout_clk))
|
||||
return pllout_clk;
|
||||
pllout_clk = clk_register(dev, &pllout->hw);
|
||||
if (IS_ERR(pllout_clk)) {
|
||||
ret = PTR_ERR(pllout_clk);
|
||||
goto err_free_pllout;
|
||||
}
|
||||
|
||||
clk_hw_set_rate_range(&pllout->hw, info->pllout_min_rate,
|
||||
info->pllout_max_rate);
|
||||
|
|
@ -474,17 +481,21 @@ struct clk *davinci_pll_clk_register(struct device *dev,
|
|||
if (info->flags & PLL_POSTDIV_ALWAYS_ENABLED)
|
||||
flags |= CLK_IS_CRITICAL;
|
||||
|
||||
clk = davinci_pll_div_register(dev, postdiv_name, parent_name,
|
||||
base + POSTDIV, fixed, flags);
|
||||
if (IS_ERR(clk))
|
||||
return clk;
|
||||
postdiv_clk = davinci_pll_div_register(dev, postdiv_name,
|
||||
parent_name, base + POSTDIV, fixed, flags);
|
||||
if (IS_ERR(postdiv_clk)) {
|
||||
ret = PTR_ERR(postdiv_clk);
|
||||
goto err_unregister_pllout;
|
||||
}
|
||||
|
||||
parent_name = postdiv_name;
|
||||
}
|
||||
|
||||
pllen = devm_kzalloc(dev, sizeof(*pllout), GFP_KERNEL);
|
||||
if (!pllen)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
pllen = kzalloc(sizeof(*pllout), GFP_KERNEL);
|
||||
if (!pllen) {
|
||||
ret = -ENOMEM;
|
||||
goto err_unregister_postdiv;
|
||||
}
|
||||
|
||||
snprintf(pllen_name, MAX_NAME_SIZE, "%s_pllen", info->name);
|
||||
|
||||
|
|
@ -497,17 +508,35 @@ struct clk *davinci_pll_clk_register(struct device *dev,
|
|||
pllen->hw.init = &init;
|
||||
pllen->base = base;
|
||||
|
||||
clk = devm_clk_register(dev, &pllen->hw);
|
||||
if (IS_ERR(clk))
|
||||
return clk;
|
||||
pllen_clk = clk_register(dev, &pllen->hw);
|
||||
if (IS_ERR(pllen_clk)) {
|
||||
ret = PTR_ERR(pllen_clk);
|
||||
goto err_free_pllen;
|
||||
}
|
||||
|
||||
clk_notifier_register(clk, &davinci_pllen_notifier);
|
||||
clk_notifier_register(pllen_clk, &davinci_pllen_notifier);
|
||||
|
||||
return pllout_clk;
|
||||
|
||||
err_free_pllen:
|
||||
kfree(pllen);
|
||||
err_unregister_postdiv:
|
||||
clk_unregister(postdiv_clk);
|
||||
err_unregister_pllout:
|
||||
clk_unregister(pllout_clk);
|
||||
err_free_pllout:
|
||||
kfree(pllout);
|
||||
err_unregister_prediv:
|
||||
clk_unregister(prediv_clk);
|
||||
err_unregister_oscin:
|
||||
clk_unregister(oscin_clk);
|
||||
|
||||
return ERR_PTR(ret);
|
||||
}
|
||||
|
||||
/**
|
||||
* davinci_pll_auxclk_register - Register bypass clock (AUXCLK)
|
||||
* @dev: The PLL platform device or NULL
|
||||
* @name: The clock name
|
||||
* @base: The PLL memory region
|
||||
*/
|
||||
|
|
@ -521,6 +550,7 @@ struct clk *davinci_pll_auxclk_register(struct device *dev,
|
|||
|
||||
/**
|
||||
* davinci_pll_sysclkbp_clk_register - Register bypass divider clock (SYSCLKBP)
|
||||
* @dev: The PLL platform device or NULL
|
||||
* @name: The clock name
|
||||
* @base: The PLL memory region
|
||||
*/
|
||||
|
|
@ -535,6 +565,7 @@ struct clk *davinci_pll_sysclkbp_clk_register(struct device *dev,
|
|||
|
||||
/**
|
||||
* davinci_pll_obsclk_register - Register oscillator divider clock (OBSCLK)
|
||||
* @dev: The PLL platform device or NULL
|
||||
* @info: The clock info
|
||||
* @base: The PLL memory region
|
||||
*/
|
||||
|
|
@ -546,9 +577,11 @@ davinci_pll_obsclk_register(struct device *dev,
|
|||
struct clk_mux *mux;
|
||||
struct clk_gate *gate;
|
||||
struct clk_divider *divider;
|
||||
struct clk *clk;
|
||||
u32 oscdiv;
|
||||
int ret;
|
||||
|
||||
mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
|
||||
mux = kzalloc(sizeof(*mux), GFP_KERNEL);
|
||||
if (!mux)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
|
|
@ -556,16 +589,20 @@ davinci_pll_obsclk_register(struct device *dev,
|
|||
mux->table = info->table;
|
||||
mux->mask = info->ocsrc_mask;
|
||||
|
||||
gate = devm_kzalloc(dev, sizeof(*gate), GFP_KERNEL);
|
||||
if (!gate)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
gate = kzalloc(sizeof(*gate), GFP_KERNEL);
|
||||
if (!gate) {
|
||||
ret = -ENOMEM;
|
||||
goto err_free_mux;
|
||||
}
|
||||
|
||||
gate->reg = base + CKEN;
|
||||
gate->bit_idx = CKEN_OBSCLK_SHIFT;
|
||||
|
||||
divider = devm_kzalloc(dev, sizeof(*divider), GFP_KERNEL);
|
||||
if (!divider)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
divider = kzalloc(sizeof(*divider), GFP_KERNEL);
|
||||
if (!divider) {
|
||||
ret = -ENOMEM;
|
||||
goto err_free_gate;
|
||||
}
|
||||
|
||||
divider->reg = base + OSCDIV;
|
||||
divider->shift = DIV_RATIO_SHIFT;
|
||||
|
|
@ -576,11 +613,27 @@ davinci_pll_obsclk_register(struct device *dev,
|
|||
oscdiv |= BIT(DIV_ENABLE_SHIFT);
|
||||
writel(oscdiv, base + OSCDIV);
|
||||
|
||||
return clk_register_composite(dev, info->name, info->parent_names,
|
||||
info->num_parents,
|
||||
&mux->hw, &clk_mux_ops,
|
||||
÷r->hw, &clk_divider_ops,
|
||||
&gate->hw, &clk_gate_ops, 0);
|
||||
clk = clk_register_composite(dev, info->name, info->parent_names,
|
||||
info->num_parents,
|
||||
&mux->hw, &clk_mux_ops,
|
||||
÷r->hw, &clk_divider_ops,
|
||||
&gate->hw, &clk_gate_ops, 0);
|
||||
|
||||
if (IS_ERR(clk)) {
|
||||
ret = PTR_ERR(clk);
|
||||
goto err_free_divider;
|
||||
}
|
||||
|
||||
return clk;
|
||||
|
||||
err_free_divider:
|
||||
kfree(divider);
|
||||
err_free_gate:
|
||||
kfree(gate);
|
||||
err_free_mux:
|
||||
kfree(mux);
|
||||
|
||||
return ERR_PTR(ret);
|
||||
}
|
||||
|
||||
/* The PLL SYSCLKn clocks have a mechanism for synchronizing rate changes. */
|
||||
|
|
@ -616,6 +669,7 @@ static struct notifier_block davinci_pll_sysclk_notifier = {
|
|||
|
||||
/**
|
||||
* davinci_pll_sysclk_register - Register divider clocks (SYSCLKn)
|
||||
* @dev: The PLL platform device or NULL
|
||||
* @info: The clock info
|
||||
* @base: The PLL memory region
|
||||
*/
|
||||
|
|
@ -630,6 +684,7 @@ davinci_pll_sysclk_register(struct device *dev,
|
|||
struct clk *clk;
|
||||
u32 reg;
|
||||
u32 flags = 0;
|
||||
int ret;
|
||||
|
||||
/* PLLDIVn registers are not entirely consecutive */
|
||||
if (info->id < 4)
|
||||
|
|
@ -637,16 +692,18 @@ davinci_pll_sysclk_register(struct device *dev,
|
|||
else
|
||||
reg = PLLDIV4 + 4 * (info->id - 4);
|
||||
|
||||
gate = devm_kzalloc(dev, sizeof(*gate), GFP_KERNEL);
|
||||
gate = kzalloc(sizeof(*gate), GFP_KERNEL);
|
||||
if (!gate)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
gate->reg = base + reg;
|
||||
gate->bit_idx = DIV_ENABLE_SHIFT;
|
||||
|
||||
divider = devm_kzalloc(dev, sizeof(*divider), GFP_KERNEL);
|
||||
if (!divider)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
divider = kzalloc(sizeof(*divider), GFP_KERNEL);
|
||||
if (!divider) {
|
||||
ret = -ENOMEM;
|
||||
goto err_free_gate;
|
||||
}
|
||||
|
||||
divider->reg = base + reg;
|
||||
divider->shift = DIV_RATIO_SHIFT;
|
||||
|
|
@ -668,22 +725,31 @@ davinci_pll_sysclk_register(struct device *dev,
|
|||
clk = clk_register_composite(dev, info->name, &info->parent_name, 1,
|
||||
NULL, NULL, ÷r->hw, divider_ops,
|
||||
&gate->hw, &clk_gate_ops, flags);
|
||||
if (IS_ERR(clk))
|
||||
return clk;
|
||||
if (IS_ERR(clk)) {
|
||||
ret = PTR_ERR(clk);
|
||||
goto err_free_divider;
|
||||
}
|
||||
|
||||
clk_notifier_register(clk, &davinci_pll_sysclk_notifier);
|
||||
|
||||
return clk;
|
||||
|
||||
err_free_divider:
|
||||
kfree(divider);
|
||||
err_free_gate:
|
||||
kfree(gate);
|
||||
|
||||
return ERR_PTR(ret);
|
||||
}
|
||||
|
||||
int of_davinci_pll_init(struct device *dev,
|
||||
int of_davinci_pll_init(struct device *dev, struct device_node *node,
|
||||
const struct davinci_pll_clk_info *info,
|
||||
const struct davinci_pll_obsclk_info *obsclk_info,
|
||||
const struct davinci_pll_sysclk_info **div_info,
|
||||
u8 max_sysclk_id,
|
||||
void __iomem *base)
|
||||
void __iomem *base,
|
||||
struct regmap *cfgchip)
|
||||
{
|
||||
struct device_node *node = dev->of_node;
|
||||
struct device_node *child;
|
||||
const char *parent_name;
|
||||
struct clk *clk;
|
||||
|
|
@ -693,7 +759,7 @@ int of_davinci_pll_init(struct device *dev,
|
|||
else
|
||||
parent_name = OSCIN_CLK_NAME;
|
||||
|
||||
clk = davinci_pll_clk_register(dev, info, parent_name, base);
|
||||
clk = davinci_pll_clk_register(dev, info, parent_name, base, cfgchip);
|
||||
if (IS_ERR(clk)) {
|
||||
dev_err(dev, "failed to register %s\n", info->name);
|
||||
return PTR_ERR(clk);
|
||||
|
|
@ -711,13 +777,15 @@ int of_davinci_pll_init(struct device *dev,
|
|||
int n_clks = max_sysclk_id + 1;
|
||||
int i;
|
||||
|
||||
clk_data = devm_kzalloc(dev, sizeof(*clk_data), GFP_KERNEL);
|
||||
clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
|
||||
if (!clk_data)
|
||||
return -ENOMEM;
|
||||
|
||||
clks = devm_kmalloc_array(dev, n_clks, sizeof(*clks), GFP_KERNEL);
|
||||
if (!clks)
|
||||
clks = kmalloc_array(n_clks, sizeof(*clks), GFP_KERNEL);
|
||||
if (!clks) {
|
||||
kfree(clk_data);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
clk_data->clks = clks;
|
||||
clk_data->clk_num = n_clks;
|
||||
|
|
@ -770,6 +838,27 @@ int of_davinci_pll_init(struct device *dev,
|
|||
return 0;
|
||||
}
|
||||
|
||||
static struct davinci_pll_platform_data *davinci_pll_get_pdata(struct device *dev)
|
||||
{
|
||||
struct davinci_pll_platform_data *pdata = dev_get_platdata(dev);
|
||||
|
||||
/*
|
||||
* Platform data is optional, so allocate a new struct if one was not
|
||||
* provided. For device tree, this will always be the case.
|
||||
*/
|
||||
if (!pdata)
|
||||
pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
|
||||
if (!pdata)
|
||||
return NULL;
|
||||
|
||||
/* for device tree, we need to fill in the struct */
|
||||
if (dev->of_node)
|
||||
pdata->cfgchip =
|
||||
syscon_regmap_lookup_by_compatible("ti,da830-cfgchip");
|
||||
|
||||
return pdata;
|
||||
}
|
||||
|
||||
static const struct of_device_id davinci_pll_of_match[] = {
|
||||
{ .compatible = "ti,da850-pll0", .data = of_da850_pll0_init },
|
||||
{ .compatible = "ti,da850-pll1", .data = of_da850_pll1_init },
|
||||
|
|
@ -791,11 +880,13 @@ static const struct platform_device_id davinci_pll_id_table[] = {
|
|||
{ }
|
||||
};
|
||||
|
||||
typedef int (*davinci_pll_init)(struct device *dev, void __iomem *base);
|
||||
typedef int (*davinci_pll_init)(struct device *dev, void __iomem *base,
|
||||
struct regmap *cfgchip);
|
||||
|
||||
static int davinci_pll_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct davinci_pll_platform_data *pdata;
|
||||
const struct of_device_id *of_id;
|
||||
davinci_pll_init pll_init = NULL;
|
||||
struct resource *res;
|
||||
|
|
@ -812,12 +903,18 @@ static int davinci_pll_probe(struct platform_device *pdev)
|
|||
return -EINVAL;
|
||||
}
|
||||
|
||||
pdata = davinci_pll_get_pdata(dev);
|
||||
if (!pdata) {
|
||||
dev_err(dev, "missing platform data\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
base = devm_ioremap_resource(dev, res);
|
||||
if (IS_ERR(base))
|
||||
return PTR_ERR(base);
|
||||
|
||||
return pll_init(dev, base);
|
||||
return pll_init(dev, base, pdata->cfgchip);
|
||||
}
|
||||
|
||||
static struct platform_driver davinci_pll_driver = {
|
||||
|
|
|
|||
|
|
@ -11,6 +11,7 @@
|
|||
#include <linux/bitops.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/regmap.h>
|
||||
#include <linux/types.h>
|
||||
|
||||
#define PLL_HAS_CLKMODE BIT(0) /* PLL has PLLCTL[CLKMODE] */
|
||||
|
|
@ -94,7 +95,8 @@ struct davinci_pll_obsclk_info {
|
|||
struct clk *davinci_pll_clk_register(struct device *dev,
|
||||
const struct davinci_pll_clk_info *info,
|
||||
const char *parent_name,
|
||||
void __iomem *base);
|
||||
void __iomem *base,
|
||||
struct regmap *cfgchip);
|
||||
struct clk *davinci_pll_auxclk_register(struct device *dev,
|
||||
const char *name,
|
||||
void __iomem *base);
|
||||
|
|
@ -110,32 +112,24 @@ davinci_pll_sysclk_register(struct device *dev,
|
|||
const struct davinci_pll_sysclk_info *info,
|
||||
void __iomem *base);
|
||||
|
||||
int of_davinci_pll_init(struct device *dev,
|
||||
int of_davinci_pll_init(struct device *dev, struct device_node *node,
|
||||
const struct davinci_pll_clk_info *info,
|
||||
const struct davinci_pll_obsclk_info *obsclk_info,
|
||||
const struct davinci_pll_sysclk_info **div_info,
|
||||
u8 max_sysclk_id,
|
||||
void __iomem *base);
|
||||
void __iomem *base,
|
||||
struct regmap *cfgchip);
|
||||
|
||||
/* Platform-specific callbacks */
|
||||
|
||||
int da830_pll_init(struct device *dev, void __iomem *base);
|
||||
int da850_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip);
|
||||
int of_da850_pll0_init(struct device *dev, void __iomem *base, struct regmap *cfgchip);
|
||||
int of_da850_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip);
|
||||
|
||||
int da850_pll0_init(struct device *dev, void __iomem *base);
|
||||
int da850_pll1_init(struct device *dev, void __iomem *base);
|
||||
int of_da850_pll0_init(struct device *dev, void __iomem *base);
|
||||
int of_da850_pll1_init(struct device *dev, void __iomem *base);
|
||||
int dm355_pll2_init(struct device *dev, void __iomem *base, struct regmap *cfgchip);
|
||||
|
||||
int dm355_pll1_init(struct device *dev, void __iomem *base);
|
||||
int dm355_pll2_init(struct device *dev, void __iomem *base);
|
||||
int dm644x_pll2_init(struct device *dev, void __iomem *base, struct regmap *cfgchip);
|
||||
|
||||
int dm365_pll1_init(struct device *dev, void __iomem *base);
|
||||
int dm365_pll2_init(struct device *dev, void __iomem *base);
|
||||
|
||||
int dm644x_pll1_init(struct device *dev, void __iomem *base);
|
||||
int dm644x_pll2_init(struct device *dev, void __iomem *base);
|
||||
|
||||
int dm646x_pll1_init(struct device *dev, void __iomem *base);
|
||||
int dm646x_pll2_init(struct device *dev, void __iomem *base);
|
||||
int dm646x_pll2_init(struct device *dev, void __iomem *base, struct regmap *cfgchip);
|
||||
|
||||
#endif /* __CLK_DAVINCI_PLL_H___ */
|
||||
|
|
|
|||
24
include/linux/clk/davinci.h
Normal file
24
include/linux/clk/davinci.h
Normal file
|
|
@ -0,0 +1,24 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Clock drivers for TI DaVinci PLL and PSC controllers
|
||||
*
|
||||
* Copyright (C) 2018 David Lechner <david@lechnology.com>
|
||||
*/
|
||||
|
||||
#ifndef __LINUX_CLK_DAVINCI_PLL_H___
|
||||
#define __LINUX_CLK_DAVINCI_PLL_H___
|
||||
|
||||
#include <linux/device.h>
|
||||
#include <linux/regmap.h>
|
||||
|
||||
/* function for registering clocks in early boot */
|
||||
|
||||
int da830_pll_init(struct device *dev, void __iomem *base, struct regmap *cfgchip);
|
||||
int da850_pll0_init(struct device *dev, void __iomem *base, struct regmap *cfgchip);
|
||||
int dm355_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip);
|
||||
int dm365_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip);
|
||||
int dm365_pll2_init(struct device *dev, void __iomem *base, struct regmap *cfgchip);
|
||||
int dm644x_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip);
|
||||
int dm646x_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip);
|
||||
|
||||
#endif /* __LINUX_CLK_DAVINCI_PLL_H___ */
|
||||
Loading…
Reference in a new issue