[SCSI] bfa: In MSIX mode, ignore spurious RME interrupts when FCoE ports are in FW mismatch state.
Use dummy interrupt handlers till chip initialization is complete. Install real interrupt handlers after chip initialization. Also removed msix installation code in bfa_iocfc_init(). Signed-off-by: Krishna Gudipati <kgudipat@brocade.com> Signed-off-by: James Bottomley <James.Bottomley@suse.de>
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2 changed files with 17 additions and 27 deletions
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@ -331,12 +331,12 @@ bfa_ioc_ct_pll_init(struct bfa_ioc_s *ioc)
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*/
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bfa_ioc_sem_get(ioc->ioc_regs.ioc_init_sem_reg);
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pll_sclk = __APP_PLL_312_ENABLE | __APP_PLL_312_LRESETN |
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__APP_PLL_312_RSEL200500 | __APP_PLL_312_P0_1(0U) |
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pll_sclk = __APP_PLL_312_LRESETN | __APP_PLL_312_ENARST |
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__APP_PLL_312_RSEL200500 | __APP_PLL_312_P0_1(3U) |
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__APP_PLL_312_JITLMT0_1(3U) |
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__APP_PLL_312_CNTLMT0_1(1U);
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pll_fclk = __APP_PLL_425_ENABLE | __APP_PLL_425_LRESETN |
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__APP_PLL_425_RSEL200500 | __APP_PLL_425_P0_1(0U) |
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pll_fclk = __APP_PLL_425_LRESETN | __APP_PLL_425_ENARST |
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__APP_PLL_425_RSEL200500 | __APP_PLL_425_P0_1(3U) |
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__APP_PLL_425_JITLMT0_1(3U) |
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__APP_PLL_425_CNTLMT0_1(1U);
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@ -366,36 +366,27 @@ bfa_ioc_ct_pll_init(struct bfa_ioc_s *ioc)
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bfa_reg_write((rb + HOSTFN0_INT_MSK), 0xffffffffU);
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bfa_reg_write((rb + HOSTFN1_INT_MSK), 0xffffffffU);
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bfa_reg_write(ioc->ioc_regs.app_pll_slow_ctl_reg,
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__APP_PLL_312_LOGIC_SOFT_RESET);
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bfa_reg_write(ioc->ioc_regs.app_pll_slow_ctl_reg,
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__APP_PLL_312_BYPASS |
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__APP_PLL_312_LOGIC_SOFT_RESET);
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bfa_reg_write(ioc->ioc_regs.app_pll_fast_ctl_reg,
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__APP_PLL_425_LOGIC_SOFT_RESET);
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bfa_reg_write(ioc->ioc_regs.app_pll_fast_ctl_reg,
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__APP_PLL_425_BYPASS |
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__APP_PLL_425_LOGIC_SOFT_RESET);
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bfa_os_udelay(2);
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bfa_reg_write(ioc->ioc_regs.app_pll_slow_ctl_reg,
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__APP_PLL_312_LOGIC_SOFT_RESET);
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bfa_reg_write(ioc->ioc_regs.app_pll_fast_ctl_reg,
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__APP_PLL_425_LOGIC_SOFT_RESET);
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bfa_reg_write(ioc->ioc_regs.app_pll_slow_ctl_reg,
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pll_sclk | __APP_PLL_312_LOGIC_SOFT_RESET);
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bfa_reg_write(ioc->ioc_regs.app_pll_fast_ctl_reg,
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pll_fclk | __APP_PLL_425_LOGIC_SOFT_RESET);
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bfa_reg_write(ioc->ioc_regs.app_pll_slow_ctl_reg, pll_sclk |
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__APP_PLL_312_LOGIC_SOFT_RESET);
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bfa_reg_write(ioc->ioc_regs.app_pll_fast_ctl_reg, pll_fclk |
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__APP_PLL_425_LOGIC_SOFT_RESET);
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bfa_reg_write(ioc->ioc_regs.app_pll_slow_ctl_reg, pll_sclk |
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__APP_PLL_312_LOGIC_SOFT_RESET | __APP_PLL_312_ENABLE);
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bfa_reg_write(ioc->ioc_regs.app_pll_fast_ctl_reg, pll_fclk |
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__APP_PLL_425_LOGIC_SOFT_RESET | __APP_PLL_425_ENABLE);
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/**
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* Wait for PLLs to lock.
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*/
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bfa_reg_read(rb + HOSTFN0_INT_MSK);
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bfa_os_udelay(2000);
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bfa_reg_write((rb + HOSTFN0_INT_STATUS), 0xffffffffU);
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bfa_reg_write((rb + HOSTFN1_INT_STATUS), 0xffffffffU);
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bfa_reg_write(ioc->ioc_regs.app_pll_slow_ctl_reg, pll_sclk);
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bfa_reg_write(ioc->ioc_regs.app_pll_fast_ctl_reg, pll_fclk);
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bfa_reg_write(ioc->ioc_regs.app_pll_slow_ctl_reg, pll_sclk |
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__APP_PLL_312_ENABLE);
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bfa_reg_write(ioc->ioc_regs.app_pll_fast_ctl_reg, pll_fclk |
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__APP_PLL_425_ENABLE);
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bfa_reg_write((rb + MBIST_CTL_REG), __EDRAM_BISTR_START);
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bfa_os_udelay(1000);
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@ -659,7 +659,6 @@ bfa_iocfc_init(struct bfa_s *bfa)
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{
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bfa->iocfc.action = BFA_IOCFC_ACT_INIT;
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bfa_ioc_enable(&bfa->ioc);
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bfa_msix_install(bfa);
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}
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/**
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