dmaengine: edma: Simplify the interrupt handling
With the merger of the arch/arm/common/edma.c code into the dmaengine driver, there is no longer need to have per channel callback/data storage for interrupt events. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
This commit is contained in:
Peter Ujfalusi
Vinod Koul
parent
11c157337a
commit
79ad2e383d
1 changed files with 207 additions and 247 deletions
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@ -154,12 +154,6 @@ struct edmacc_param {
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#define TCCHEN BIT(22)
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#define ITCCHEN BIT(23)
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/*ch_status parameter of callback function possible values*/
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#define EDMA_DMA_COMPLETE 1
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#define EDMA_DMA_CC_ERROR 2
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#define EDMA_DMA_TC1_ERROR 3
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#define EDMA_DMA_TC2_ERROR 4
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struct edma_pset {
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u32 len;
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dma_addr_t addr;
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@ -243,12 +237,6 @@ struct edma_cc {
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*/
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unsigned long *edma_unused;
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struct dma_interrupt_data {
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void (*callback)(unsigned channel, unsigned short ch_status,
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void *data);
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void *data;
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} *intr_data;
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struct dma_device dma_slave;
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struct edma_chan *slave_chans;
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int dummy_slot;
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@ -486,24 +474,18 @@ static int prepare_unused_channel_list(struct device *dev, void *data)
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return 0;
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}
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static void edma_setup_interrupt(struct edma_cc *ecc, unsigned lch,
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void (*callback)(unsigned channel, u16 ch_status, void *data),
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void *data)
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static void edma_setup_interrupt(struct edma_cc *ecc, unsigned lch, bool enable)
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{
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lch = EDMA_CHAN_SLOT(lch);
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if (!callback)
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edma_shadow0_write_array(ecc, SH_IECR, lch >> 5,
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BIT(lch & 0x1f));
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ecc->intr_data[lch].callback = callback;
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ecc->intr_data[lch].data = data;
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if (callback) {
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if (enable) {
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edma_shadow0_write_array(ecc, SH_ICR, lch >> 5,
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BIT(lch & 0x1f));
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edma_shadow0_write_array(ecc, SH_IESR, lch >> 5,
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BIT(lch & 0x1f));
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} else {
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edma_shadow0_write_array(ecc, SH_IECR, lch >> 5,
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BIT(lch & 0x1f));
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}
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}
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@ -795,8 +777,6 @@ static void edma_clean_channel(struct edma_cc *ecc, unsigned channel)
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* edma_alloc_channel - allocate DMA channel and paired parameter RAM
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* @ecc: pointer to edma_cc struct
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* @channel: specific channel to allocate; negative for "any unmapped channel"
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* @callback: optional; to be issued on DMA completion or errors
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* @data: passed to callback
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* @eventq_no: an EVENTQ_* constant, used to choose which Transfer
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* Controller (TC) executes requests using this channel. Use
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* EVENTQ_DEFAULT unless you really need a high priority queue.
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@ -823,9 +803,7 @@ static void edma_clean_channel(struct edma_cc *ecc, unsigned channel)
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* Returns the number of the channel, else negative errno.
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*/
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static int edma_alloc_channel(struct edma_cc *ecc, int channel,
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void (*callback)(unsigned channel, u16 ch_status, void *data),
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void *data,
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enum dma_event_q eventq_no)
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enum dma_event_q eventq_no)
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{
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unsigned done = 0;
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int ret = 0;
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@ -881,9 +859,7 @@ static int edma_alloc_channel(struct edma_cc *ecc, int channel,
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edma_stop(ecc, EDMA_CTLR_CHAN(ecc->id, channel));
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edma_write_slot(ecc, channel, &dummy_paramset);
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if (callback)
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edma_setup_interrupt(ecc, EDMA_CTLR_CHAN(ecc->id, channel),
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callback, data);
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edma_setup_interrupt(ecc, EDMA_CTLR_CHAN(ecc->id, channel), true);
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edma_map_dmach_to_queue(ecc, channel, eventq_no);
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@ -914,7 +890,7 @@ static void edma_free_channel(struct edma_cc *ecc, unsigned channel)
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if (channel >= ecc->num_channels)
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return;
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edma_setup_interrupt(ecc, channel, NULL, NULL);
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edma_setup_interrupt(ecc, channel, false);
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/* REVISIT should probably take out of shadow region 0 */
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edma_write_slot(ecc, channel, &dummy_paramset);
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@ -944,148 +920,6 @@ static void edma_assign_channel_eventq(struct edma_cc *ecc, unsigned channel,
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edma_map_dmach_to_queue(ecc, channel, eventq_no);
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}
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/* eDMA interrupt handler */
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static irqreturn_t dma_irq_handler(int irq, void *data)
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{
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struct edma_cc *ecc = data;
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int ctlr;
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u32 sh_ier;
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u32 sh_ipr;
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u32 bank;
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ctlr = ecc->id;
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if (ctlr < 0)
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return IRQ_NONE;
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dev_dbg(ecc->dev, "dma_irq_handler\n");
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sh_ipr = edma_shadow0_read_array(ecc, SH_IPR, 0);
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if (!sh_ipr) {
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sh_ipr = edma_shadow0_read_array(ecc, SH_IPR, 1);
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if (!sh_ipr)
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return IRQ_NONE;
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sh_ier = edma_shadow0_read_array(ecc, SH_IER, 1);
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bank = 1;
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} else {
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sh_ier = edma_shadow0_read_array(ecc, SH_IER, 0);
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bank = 0;
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}
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do {
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u32 slot;
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u32 channel;
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dev_dbg(ecc->dev, "IPR%d %08x\n", bank, sh_ipr);
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slot = __ffs(sh_ipr);
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sh_ipr &= ~(BIT(slot));
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if (sh_ier & BIT(slot)) {
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channel = (bank << 5) | slot;
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/* Clear the corresponding IPR bits */
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edma_shadow0_write_array(ecc, SH_ICR, bank, BIT(slot));
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if (ecc->intr_data[channel].callback)
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ecc->intr_data[channel].callback(
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EDMA_CTLR_CHAN(ctlr, channel),
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EDMA_DMA_COMPLETE,
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ecc->intr_data[channel].data);
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}
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} while (sh_ipr);
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edma_shadow0_write(ecc, SH_IEVAL, 1);
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return IRQ_HANDLED;
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}
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/* eDMA error interrupt handler */
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static irqreturn_t dma_ccerr_handler(int irq, void *data)
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{
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struct edma_cc *ecc = data;
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int i;
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int ctlr;
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unsigned int cnt = 0;
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ctlr = ecc->id;
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if (ctlr < 0)
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return IRQ_NONE;
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dev_dbg(ecc->dev, "dma_ccerr_handler\n");
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if ((edma_read_array(ecc, EDMA_EMR, 0) == 0) &&
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(edma_read_array(ecc, EDMA_EMR, 1) == 0) &&
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(edma_read(ecc, EDMA_QEMR) == 0) &&
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(edma_read(ecc, EDMA_CCERR) == 0))
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return IRQ_NONE;
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while (1) {
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int j = -1;
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if (edma_read_array(ecc, EDMA_EMR, 0))
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j = 0;
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else if (edma_read_array(ecc, EDMA_EMR, 1))
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j = 1;
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if (j >= 0) {
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dev_dbg(ecc->dev, "EMR%d %08x\n", j,
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edma_read_array(ecc, EDMA_EMR, j));
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for (i = 0; i < 32; i++) {
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int k = (j << 5) + i;
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if (edma_read_array(ecc, EDMA_EMR, j) &
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BIT(i)) {
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/* Clear the corresponding EMR bits */
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edma_write_array(ecc, EDMA_EMCR, j,
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BIT(i));
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/* Clear any SER */
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edma_shadow0_write_array(ecc, SH_SECR,
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j, BIT(i));
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if (ecc->intr_data[k].callback) {
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ecc->intr_data[k].callback(
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EDMA_CTLR_CHAN(ctlr, k),
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EDMA_DMA_CC_ERROR,
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ecc->intr_data[k].data);
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}
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}
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}
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} else if (edma_read(ecc, EDMA_QEMR)) {
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dev_dbg(ecc->dev, "QEMR %02x\n",
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edma_read(ecc, EDMA_QEMR));
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for (i = 0; i < 8; i++) {
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if (edma_read(ecc, EDMA_QEMR) & BIT(i)) {
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/* Clear the corresponding IPR bits */
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edma_write(ecc, EDMA_QEMCR, BIT(i));
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edma_shadow0_write(ecc, SH_QSECR,
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BIT(i));
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/* NOTE: not reported!! */
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}
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}
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} else if (edma_read(ecc, EDMA_CCERR)) {
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dev_dbg(ecc->dev, "CCERR %08x\n",
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edma_read(ecc, EDMA_CCERR));
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/* FIXME: CCERR.BIT(16) ignored! much better
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* to just write CCERRCLR with CCERR value...
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*/
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for (i = 0; i < 8; i++) {
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if (edma_read(ecc, EDMA_CCERR) & BIT(i)) {
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/* Clear the corresponding IPR bits */
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edma_write(ecc, EDMA_CCERRCLR, BIT(i));
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/* NOTE: not reported!! */
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}
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}
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}
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if ((edma_read_array(ecc, EDMA_EMR, 0) == 0) &&
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(edma_read_array(ecc, EDMA_EMR, 1) == 0) &&
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(edma_read(ecc, EDMA_QEMR) == 0) &&
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(edma_read(ecc, EDMA_CCERR) == 0))
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break;
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cnt++;
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if (cnt > 10)
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break;
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}
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edma_write(ecc, EDMA_EEVAL, 1);
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return IRQ_HANDLED;
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}
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static inline struct edma_cc *to_edma_cc(struct dma_device *d)
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{
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return container_of(d, struct edma_cc, dma_slave);
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@ -1667,83 +1501,216 @@ static struct dma_async_tx_descriptor *edma_prep_dma_cyclic(
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return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags);
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}
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static void edma_callback(unsigned ch_num, u16 ch_status, void *data)
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static void edma_completion_handler(struct edma_chan *echan)
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{
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struct edma_chan *echan = data;
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struct edma_cc *ecc = echan->ecc;
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struct device *dev = echan->vchan.chan.device->dev;
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struct edma_desc *edesc;
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struct edmacc_param p;
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struct edma_desc *edesc = echan->edesc;
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edesc = echan->edesc;
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if (!edesc)
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return;
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spin_lock(&echan->vchan.lock);
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switch (ch_status) {
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case EDMA_DMA_COMPLETE:
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if (edesc) {
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if (edesc->cyclic) {
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vchan_cyclic_callback(&edesc->vdesc);
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goto out;
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} else if (edesc->processed == edesc->pset_nr) {
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dev_dbg(dev,
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"Transfer completed on channel %d\n",
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ch_num);
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edesc->residue = 0;
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edma_stop(ecc, echan->ch_num);
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vchan_cookie_complete(&edesc->vdesc);
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echan->edesc = NULL;
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} else {
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dev_dbg(dev,
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"Sub transfer completed on channel %d\n",
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ch_num);
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if (edesc->cyclic) {
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vchan_cyclic_callback(&edesc->vdesc);
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spin_unlock(&echan->vchan.lock);
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return;
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} else if (edesc->processed == edesc->pset_nr) {
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edesc->residue = 0;
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edma_stop(ecc, echan->ch_num);
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vchan_cookie_complete(&edesc->vdesc);
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echan->edesc = NULL;
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edma_pause(ecc, echan->ch_num);
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dev_dbg(dev, "Transfer completed on channel %d\n",
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echan->ch_num);
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} else {
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dev_dbg(dev, "Sub transfer completed on channel %d\n",
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echan->ch_num);
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/* Update statistics for tx_status */
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edesc->residue -= edesc->sg_len;
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edesc->residue_stat = edesc->residue;
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edesc->processed_stat = edesc->processed;
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}
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edma_execute(echan);
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}
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break;
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case EDMA_DMA_CC_ERROR:
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edma_read_slot(ecc, echan->slot[0], &p);
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edma_pause(ecc, echan->ch_num);
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/*
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* Issue later based on missed flag which will be sure
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* to happen as:
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* (1) we finished transmitting an intermediate slot and
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* edma_execute is coming up.
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* (2) or we finished current transfer and issue will
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* call edma_execute.
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*
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* Important note: issuing can be dangerous here and
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* lead to some nasty recursion when we are in a NULL
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* slot. So we avoid doing so and set the missed flag.
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*/
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if (p.a_b_cnt == 0 && p.ccnt == 0) {
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dev_dbg(dev, "Error on null slot, setting miss\n");
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echan->missed = 1;
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} else {
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/*
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* The slot is already programmed but the event got
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* missed, so its safe to issue it here.
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*/
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dev_dbg(dev, "Missed event, TRIGGERING\n");
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edma_clean_channel(ecc, echan->ch_num);
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edma_stop(ecc, echan->ch_num);
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edma_start(ecc, echan->ch_num);
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edma_trigger_channel(ecc, echan->ch_num);
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}
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break;
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default:
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break;
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/* Update statistics for tx_status */
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edesc->residue -= edesc->sg_len;
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edesc->residue_stat = edesc->residue;
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edesc->processed_stat = edesc->processed;
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}
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out:
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edma_execute(echan);
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spin_unlock(&echan->vchan.lock);
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}
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/* eDMA interrupt handler */
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static irqreturn_t dma_irq_handler(int irq, void *data)
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{
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struct edma_cc *ecc = data;
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int ctlr;
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u32 sh_ier;
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u32 sh_ipr;
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u32 bank;
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ctlr = ecc->id;
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if (ctlr < 0)
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return IRQ_NONE;
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dev_vdbg(ecc->dev, "dma_irq_handler\n");
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sh_ipr = edma_shadow0_read_array(ecc, SH_IPR, 0);
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if (!sh_ipr) {
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sh_ipr = edma_shadow0_read_array(ecc, SH_IPR, 1);
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if (!sh_ipr)
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return IRQ_NONE;
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sh_ier = edma_shadow0_read_array(ecc, SH_IER, 1);
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bank = 1;
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} else {
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sh_ier = edma_shadow0_read_array(ecc, SH_IER, 0);
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bank = 0;
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}
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do {
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u32 slot;
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u32 channel;
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slot = __ffs(sh_ipr);
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sh_ipr &= ~(BIT(slot));
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if (sh_ier & BIT(slot)) {
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channel = (bank << 5) | slot;
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/* Clear the corresponding IPR bits */
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edma_shadow0_write_array(ecc, SH_ICR, bank, BIT(slot));
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edma_completion_handler(&ecc->slave_chans[channel]);
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}
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} while (sh_ipr);
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edma_shadow0_write(ecc, SH_IEVAL, 1);
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return IRQ_HANDLED;
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}
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static void edma_error_handler(struct edma_chan *echan)
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{
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struct edma_cc *ecc = echan->ecc;
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struct device *dev = echan->vchan.chan.device->dev;
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struct edmacc_param p;
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if (!echan->edesc)
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return;
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spin_lock(&echan->vchan.lock);
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edma_read_slot(ecc, echan->slot[0], &p);
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/*
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* Issue later based on missed flag which will be sure
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* to happen as:
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* (1) we finished transmitting an intermediate slot and
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* edma_execute is coming up.
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* (2) or we finished current transfer and issue will
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* call edma_execute.
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*
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* Important note: issuing can be dangerous here and
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* lead to some nasty recursion when we are in a NULL
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* slot. So we avoid doing so and set the missed flag.
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*/
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if (p.a_b_cnt == 0 && p.ccnt == 0) {
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dev_dbg(dev, "Error on null slot, setting miss\n");
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echan->missed = 1;
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} else {
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/*
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* The slot is already programmed but the event got
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* missed, so its safe to issue it here.
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*/
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dev_dbg(dev, "Missed event, TRIGGERING\n");
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edma_clean_channel(ecc, echan->ch_num);
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edma_stop(ecc, echan->ch_num);
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edma_start(ecc, echan->ch_num);
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edma_trigger_channel(ecc, echan->ch_num);
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}
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spin_unlock(&echan->vchan.lock);
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}
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/* eDMA error interrupt handler */
|
||||
static irqreturn_t dma_ccerr_handler(int irq, void *data)
|
||||
{
|
||||
struct edma_cc *ecc = data;
|
||||
int i;
|
||||
int ctlr;
|
||||
unsigned int cnt = 0;
|
||||
|
||||
ctlr = ecc->id;
|
||||
if (ctlr < 0)
|
||||
return IRQ_NONE;
|
||||
|
||||
dev_vdbg(ecc->dev, "dma_ccerr_handler\n");
|
||||
|
||||
if ((edma_read_array(ecc, EDMA_EMR, 0) == 0) &&
|
||||
(edma_read_array(ecc, EDMA_EMR, 1) == 0) &&
|
||||
(edma_read(ecc, EDMA_QEMR) == 0) &&
|
||||
(edma_read(ecc, EDMA_CCERR) == 0))
|
||||
return IRQ_NONE;
|
||||
|
||||
while (1) {
|
||||
int j = -1;
|
||||
|
||||
if (edma_read_array(ecc, EDMA_EMR, 0))
|
||||
j = 0;
|
||||
else if (edma_read_array(ecc, EDMA_EMR, 1))
|
||||
j = 1;
|
||||
if (j >= 0) {
|
||||
dev_dbg(ecc->dev, "EMR%d %08x\n", j,
|
||||
edma_read_array(ecc, EDMA_EMR, j));
|
||||
for (i = 0; i < 32; i++) {
|
||||
int k = (j << 5) + i;
|
||||
|
||||
if (edma_read_array(ecc, EDMA_EMR, j) &
|
||||
BIT(i)) {
|
||||
/* Clear the corresponding EMR bits */
|
||||
edma_write_array(ecc, EDMA_EMCR, j,
|
||||
BIT(i));
|
||||
/* Clear any SER */
|
||||
edma_shadow0_write_array(ecc, SH_SECR,
|
||||
j, BIT(i));
|
||||
edma_error_handler(&ecc->slave_chans[k]);
|
||||
}
|
||||
}
|
||||
} else if (edma_read(ecc, EDMA_QEMR)) {
|
||||
dev_dbg(ecc->dev, "QEMR %02x\n",
|
||||
edma_read(ecc, EDMA_QEMR));
|
||||
for (i = 0; i < 8; i++) {
|
||||
if (edma_read(ecc, EDMA_QEMR) & BIT(i)) {
|
||||
/* Clear the corresponding IPR bits */
|
||||
edma_write(ecc, EDMA_QEMCR, BIT(i));
|
||||
edma_shadow0_write(ecc, SH_QSECR,
|
||||
BIT(i));
|
||||
|
||||
/* NOTE: not reported!! */
|
||||
}
|
||||
}
|
||||
} else if (edma_read(ecc, EDMA_CCERR)) {
|
||||
dev_dbg(ecc->dev, "CCERR %08x\n",
|
||||
edma_read(ecc, EDMA_CCERR));
|
||||
/* FIXME: CCERR.BIT(16) ignored! much better
|
||||
* to just write CCERRCLR with CCERR value...
|
||||
*/
|
||||
for (i = 0; i < 8; i++) {
|
||||
if (edma_read(ecc, EDMA_CCERR) & BIT(i)) {
|
||||
/* Clear the corresponding IPR bits */
|
||||
edma_write(ecc, EDMA_CCERRCLR, BIT(i));
|
||||
|
||||
/* NOTE: not reported!! */
|
||||
}
|
||||
}
|
||||
}
|
||||
if ((edma_read_array(ecc, EDMA_EMR, 0) == 0) &&
|
||||
(edma_read_array(ecc, EDMA_EMR, 1) == 0) &&
|
||||
(edma_read(ecc, EDMA_QEMR) == 0) &&
|
||||
(edma_read(ecc, EDMA_CCERR) == 0))
|
||||
break;
|
||||
cnt++;
|
||||
if (cnt > 10)
|
||||
break;
|
||||
}
|
||||
edma_write(ecc, EDMA_EEVAL, 1);
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
/* Alloc channel resources */
|
||||
static int edma_alloc_chan_resources(struct dma_chan *chan)
|
||||
{
|
||||
|
|
@ -1753,8 +1720,7 @@ static int edma_alloc_chan_resources(struct dma_chan *chan)
|
|||
int a_ch_num;
|
||||
LIST_HEAD(descs);
|
||||
|
||||
a_ch_num = edma_alloc_channel(echan->ecc, echan->ch_num,
|
||||
edma_callback, echan, EVENTQ_DEFAULT);
|
||||
a_ch_num = edma_alloc_channel(echan->ecc, echan->ch_num, EVENTQ_DEFAULT);
|
||||
|
||||
if (a_ch_num < 0) {
|
||||
ret = -ENODEV;
|
||||
|
|
@ -2175,11 +2141,6 @@ static int edma_probe(struct platform_device *pdev)
|
|||
if (!ecc->slave_chans)
|
||||
return -ENOMEM;
|
||||
|
||||
ecc->intr_data = devm_kcalloc(dev, ecc->num_channels,
|
||||
sizeof(*ecc->intr_data), GFP_KERNEL);
|
||||
if (!ecc->intr_data)
|
||||
return -ENOMEM;
|
||||
|
||||
ecc->edma_unused = devm_kcalloc(dev, BITS_TO_LONGS(ecc->num_channels),
|
||||
sizeof(unsigned long), GFP_KERNEL);
|
||||
if (!ecc->edma_unused)
|
||||
|
|
@ -2350,8 +2311,7 @@ static int edma_pm_resume(struct device *dev)
|
|||
BIT(i & 0x1f));
|
||||
|
||||
edma_setup_interrupt(ecc, EDMA_CTLR_CHAN(ecc->id, i),
|
||||
ecc->intr_data[i].callback,
|
||||
ecc->intr_data[i].data);
|
||||
true);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue