sfc: Add support for SFE4003 board and TXC43128 PHY
This board never went into production, but some engineering samples are in use. Signed-off-by: Ben Hutchings <bhutchings@solarflare.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Ben Hutchings
David S. Miller
parent
8fbca79130
commit
7e51b439f1
5 changed files with 656 additions and 1 deletions
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@ -1,7 +1,8 @@
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sfc-y += efx.o nic.o falcon.o siena.o tx.o rx.o filter.o \
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falcon_xmac.o mcdi_mac.o \
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selftest.o ethtool.o qt202x_phy.o mdio_10g.o \
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tenxpress.o falcon_boards.o mcdi.o mcdi_phy.o
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tenxpress.o txc43128_phy.o falcon_boards.o \
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mcdi.o mcdi_phy.o
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sfc-$(CONFIG_SFC_MTD) += mtd.o
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obj-$(CONFIG_SFC) += sfc.o
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@ -831,6 +831,9 @@ static int falcon_probe_port(struct efx_nic *efx)
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case PHY_TYPE_QT2025C:
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efx->phy_op = &falcon_qt202x_phy_ops;
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break;
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case PHY_TYPE_TXC43128:
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efx->phy_op = &falcon_txc_phy_ops;
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break;
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default:
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netif_err(efx, probe, efx->net_dev, "Unknown PHY type %d\n",
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efx->phy_type);
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@ -26,6 +26,7 @@
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/* Board types */
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#define FALCON_BOARD_SFE4001 0x01
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#define FALCON_BOARD_SFE4002 0x02
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#define FALCON_BOARD_SFE4003 0x03
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#define FALCON_BOARD_SFN4112F 0x52
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/* Board temperature is about 15°C above ambient when air flow is
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@ -582,6 +583,75 @@ static int sfn4112f_init(struct efx_nic *efx)
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return efx_init_lm87(efx, &sfn4112f_hwmon_info, sfn4112f_lm87_regs);
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}
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/*****************************************************************************
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* Support for the SFE4003
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*
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*/
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static u8 sfe4003_lm87_channel = 0x03; /* use AIN not FAN inputs */
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static const u8 sfe4003_lm87_regs[] = {
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LM87_IN_LIMITS(0, 0x67, 0x7f), /* 2.5V: 1.5V +/- 10% */
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LM87_IN_LIMITS(1, 0x4c, 0x5e), /* Vccp1: 1.2V +/- 10% */
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LM87_IN_LIMITS(2, 0xac, 0xd4), /* 3.3V: 3.3V +/- 10% */
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LM87_IN_LIMITS(4, 0xac, 0xe0), /* 12V: 10.8-14V */
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LM87_IN_LIMITS(5, 0x3f, 0x4f), /* Vccp2: 1.0V +/- 10% */
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LM87_TEMP_INT_LIMITS(0, 70 + FALCON_BOARD_TEMP_BIAS),
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0
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};
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static struct i2c_board_info sfe4003_hwmon_info = {
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I2C_BOARD_INFO("lm87", 0x2e),
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.platform_data = &sfe4003_lm87_channel,
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};
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/* Board-specific LED info. */
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#define SFE4003_RED_LED_GPIO 11
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#define SFE4003_LED_ON 1
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#define SFE4003_LED_OFF 0
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static void sfe4003_set_id_led(struct efx_nic *efx, enum efx_led_mode mode)
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{
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struct falcon_board *board = falcon_board(efx);
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/* The LEDs were not wired to GPIOs before A3 */
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if (board->minor < 3 && board->major == 0)
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return;
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falcon_txc_set_gpio_val(
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efx, SFE4003_RED_LED_GPIO,
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(mode == EFX_LED_ON) ? SFE4003_LED_ON : SFE4003_LED_OFF);
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}
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static void sfe4003_init_phy(struct efx_nic *efx)
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{
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struct falcon_board *board = falcon_board(efx);
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/* The LEDs were not wired to GPIOs before A3 */
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if (board->minor < 3 && board->major == 0)
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return;
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falcon_txc_set_gpio_dir(efx, SFE4003_RED_LED_GPIO, TXC_GPIO_DIR_OUTPUT);
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falcon_txc_set_gpio_val(efx, SFE4003_RED_LED_GPIO, SFE4003_LED_OFF);
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}
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static int sfe4003_check_hw(struct efx_nic *efx)
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{
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struct falcon_board *board = falcon_board(efx);
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/* A0/A1/A2 board rev. 4003s report a temperature fault the whole time
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* (bad sensor) so we mask it out. */
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unsigned alarm_mask =
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(board->major == 0 && board->minor <= 2) ?
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~LM87_ALARM_TEMP_EXT1 : ~0;
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return efx_check_lm87(efx, alarm_mask);
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}
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static int sfe4003_init(struct efx_nic *efx)
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{
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return efx_init_lm87(efx, &sfe4003_hwmon_info, sfe4003_lm87_regs);
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}
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static const struct falcon_board_type board_types[] = {
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{
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.id = FALCON_BOARD_SFE4001,
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@ -603,6 +673,16 @@ static const struct falcon_board_type board_types[] = {
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.set_id_led = sfe4002_set_id_led,
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.monitor = sfe4002_check_hw,
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},
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{
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.id = FALCON_BOARD_SFE4003,
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.ref_model = "SFE4003",
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.gen_type = "10GBASE-CX4 adapter",
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.init = sfe4003_init,
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.init_phy = sfe4003_init_phy,
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.fini = efx_fini_lm87,
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.set_id_led = sfe4003_set_id_led,
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.monitor = sfe4003_check_hw,
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},
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{
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.id = FALCON_BOARD_SFN4112F,
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.ref_model = "SFN4112F",
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@ -36,6 +36,17 @@ extern struct efx_phy_operations falcon_qt202x_phy_ops;
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extern void falcon_qt202x_set_led(struct efx_nic *p, int led, int state);
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/****************************************************************************
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* Transwitch CX4 retimer
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*/
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extern struct efx_phy_operations falcon_txc_phy_ops;
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#define TXC_GPIO_DIR_INPUT 0
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#define TXC_GPIO_DIR_OUTPUT 1
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extern void falcon_txc_set_gpio_dir(struct efx_nic *efx, int pin, int dir);
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extern void falcon_txc_set_gpio_val(struct efx_nic *efx, int pin, int val);
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/****************************************************************************
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* Siena managed PHYs
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*/
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560
drivers/net/sfc/txc43128_phy.c
Normal file
560
drivers/net/sfc/txc43128_phy.c
Normal file
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@ -0,0 +1,560 @@
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/****************************************************************************
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* Driver for Solarflare Solarstorm network controllers and boards
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* Copyright 2006-2010 Solarflare Communications Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation, incorporated herein by reference.
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*/
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/*
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* Driver for Transwitch/Mysticom CX4 retimer
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* see www.transwitch.com, part is TXC-43128
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*/
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#include <linux/delay.h>
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#include <linux/slab.h>
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#include "efx.h"
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#include "mdio_10g.h"
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#include "phy.h"
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#include "nic.h"
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/* We expect these MMDs to be in the package */
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#define TXC_REQUIRED_DEVS (MDIO_DEVS_PCS | \
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MDIO_DEVS_PMAPMD | \
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MDIO_DEVS_PHYXS)
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#define TXC_LOOPBACKS ((1 << LOOPBACK_PCS) | \
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(1 << LOOPBACK_PMAPMD) | \
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(1 << LOOPBACK_PHYXS_WS))
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/**************************************************************************
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*
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* Compile-time config
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*
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**************************************************************************
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*/
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#define TXCNAME "TXC43128"
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/* Total length of time we'll wait for the PHY to come out of reset (ms) */
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#define TXC_MAX_RESET_TIME 500
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/* Interval between checks (ms) */
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#define TXC_RESET_WAIT 10
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/* How long to run BIST (us) */
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#define TXC_BIST_DURATION 50
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/**************************************************************************
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*
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* Register definitions
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*
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**************************************************************************
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*/
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/* Command register */
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#define TXC_GLRGS_GLCMD 0xc004
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/* Useful bits in command register */
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/* Lane power-down */
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#define TXC_GLCMD_L01PD_LBN 5
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#define TXC_GLCMD_L23PD_LBN 6
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/* Limited SW reset: preserves configuration but
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* initiates a logic reset. Self-clearing */
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#define TXC_GLCMD_LMTSWRST_LBN 14
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/* Signal Quality Control */
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#define TXC_GLRGS_GSGQLCTL 0xc01a
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/* Enable bit */
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#define TXC_GSGQLCT_SGQLEN_LBN 15
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/* Lane selection */
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#define TXC_GSGQLCT_LNSL_LBN 13
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#define TXC_GSGQLCT_LNSL_WIDTH 2
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/* Analog TX control */
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#define TXC_ALRGS_ATXCTL 0xc040
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/* Lane power-down */
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#define TXC_ATXCTL_TXPD3_LBN 15
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#define TXC_ATXCTL_TXPD2_LBN 14
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#define TXC_ATXCTL_TXPD1_LBN 13
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#define TXC_ATXCTL_TXPD0_LBN 12
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/* Amplitude on lanes 0, 1 */
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#define TXC_ALRGS_ATXAMP0 0xc041
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/* Amplitude on lanes 2, 3 */
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#define TXC_ALRGS_ATXAMP1 0xc042
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/* Bit position of value for lane 0 (or 2) */
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#define TXC_ATXAMP_LANE02_LBN 3
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/* Bit position of value for lane 1 (or 3) */
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#define TXC_ATXAMP_LANE13_LBN 11
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#define TXC_ATXAMP_1280_mV 0
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#define TXC_ATXAMP_1200_mV 8
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#define TXC_ATXAMP_1120_mV 12
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#define TXC_ATXAMP_1060_mV 14
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#define TXC_ATXAMP_0820_mV 25
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#define TXC_ATXAMP_0720_mV 26
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#define TXC_ATXAMP_0580_mV 27
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#define TXC_ATXAMP_0440_mV 28
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#define TXC_ATXAMP_0820_BOTH \
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((TXC_ATXAMP_0820_mV << TXC_ATXAMP_LANE02_LBN) \
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| (TXC_ATXAMP_0820_mV << TXC_ATXAMP_LANE13_LBN))
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#define TXC_ATXAMP_DEFAULT 0x6060 /* From databook */
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/* Preemphasis on lanes 0, 1 */
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#define TXC_ALRGS_ATXPRE0 0xc043
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/* Preemphasis on lanes 2, 3 */
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#define TXC_ALRGS_ATXPRE1 0xc044
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#define TXC_ATXPRE_NONE 0
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#define TXC_ATXPRE_DEFAULT 0x1010 /* From databook */
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#define TXC_ALRGS_ARXCTL 0xc045
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/* Lane power-down */
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#define TXC_ARXCTL_RXPD3_LBN 15
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#define TXC_ARXCTL_RXPD2_LBN 14
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#define TXC_ARXCTL_RXPD1_LBN 13
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#define TXC_ARXCTL_RXPD0_LBN 12
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/* Main control */
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#define TXC_MRGS_CTL 0xc340
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/* Bits in main control */
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#define TXC_MCTL_RESET_LBN 15 /* Self clear */
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#define TXC_MCTL_TXLED_LBN 14 /* 1 to show align status */
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#define TXC_MCTL_RXLED_LBN 13 /* 1 to show align status */
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/* GPIO output */
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#define TXC_GPIO_OUTPUT 0xc346
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#define TXC_GPIO_DIR 0xc348
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/* Vendor-specific BIST registers */
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#define TXC_BIST_CTL 0xc280
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#define TXC_BIST_TXFRMCNT 0xc281
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#define TXC_BIST_RX0FRMCNT 0xc282
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#define TXC_BIST_RX1FRMCNT 0xc283
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#define TXC_BIST_RX2FRMCNT 0xc284
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#define TXC_BIST_RX3FRMCNT 0xc285
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#define TXC_BIST_RX0ERRCNT 0xc286
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#define TXC_BIST_RX1ERRCNT 0xc287
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#define TXC_BIST_RX2ERRCNT 0xc288
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#define TXC_BIST_RX3ERRCNT 0xc289
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/* BIST type (controls bit patter in test) */
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#define TXC_BIST_CTRL_TYPE_LBN 10
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#define TXC_BIST_CTRL_TYPE_TSD 0 /* TranSwitch Deterministic */
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#define TXC_BIST_CTRL_TYPE_CRP 1 /* CRPAT standard */
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#define TXC_BIST_CTRL_TYPE_CJP 2 /* CJPAT standard */
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#define TXC_BIST_CTRL_TYPE_TSR 3 /* TranSwitch pseudo-random */
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/* Set this to 1 for 10 bit and 0 for 8 bit */
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#define TXC_BIST_CTRL_B10EN_LBN 12
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/* Enable BIST (write 0 to disable) */
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#define TXC_BIST_CTRL_ENAB_LBN 13
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/* Stop BIST (self-clears when stop complete) */
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#define TXC_BIST_CTRL_STOP_LBN 14
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/* Start BIST (cleared by writing 1 to STOP) */
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#define TXC_BIST_CTRL_STRT_LBN 15
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/* Mt. Diablo test configuration */
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#define TXC_MTDIABLO_CTRL 0xc34f
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#define TXC_MTDIABLO_CTRL_PMA_LOOP_LBN 10
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struct txc43128_data {
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unsigned long bug10934_timer;
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enum efx_phy_mode phy_mode;
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enum efx_loopback_mode loopback_mode;
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};
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/* The PHY sometimes needs a reset to bring the link back up. So long as
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* it reports link down, we reset it every 5 seconds.
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*/
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#define BUG10934_RESET_INTERVAL (5 * HZ)
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/* Perform a reset that doesn't clear configuration changes */
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static void txc_reset_logic(struct efx_nic *efx);
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/* Set the output value of a gpio */
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void falcon_txc_set_gpio_val(struct efx_nic *efx, int pin, int on)
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{
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efx_mdio_set_flag(efx, MDIO_MMD_PHYXS, TXC_GPIO_OUTPUT, 1 << pin, on);
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}
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/* Set up the GPIO direction register */
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void falcon_txc_set_gpio_dir(struct efx_nic *efx, int pin, int dir)
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{
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efx_mdio_set_flag(efx, MDIO_MMD_PHYXS, TXC_GPIO_DIR, 1 << pin, dir);
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}
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/* Reset the PMA/PMD MMD. The documentation is explicit that this does a
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* global reset (it's less clear what reset of other MMDs does).*/
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static int txc_reset_phy(struct efx_nic *efx)
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{
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int rc = efx_mdio_reset_mmd(efx, MDIO_MMD_PMAPMD,
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TXC_MAX_RESET_TIME / TXC_RESET_WAIT,
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TXC_RESET_WAIT);
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if (rc < 0)
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goto fail;
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/* Check that all the MMDs we expect are present and responding. */
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rc = efx_mdio_check_mmds(efx, TXC_REQUIRED_DEVS, 0);
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if (rc < 0)
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goto fail;
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return 0;
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fail:
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netif_err(efx, hw, efx->net_dev, TXCNAME ": reset timed out!\n");
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return rc;
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}
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/* Run a single BIST on one MMD */
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static int txc_bist_one(struct efx_nic *efx, int mmd, int test)
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{
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int ctrl, bctl;
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int lane;
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int rc = 0;
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/* Set PMA to test into loopback using Mt Diablo reg as per app note */
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ctrl = efx_mdio_read(efx, MDIO_MMD_PCS, TXC_MTDIABLO_CTRL);
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ctrl |= (1 << TXC_MTDIABLO_CTRL_PMA_LOOP_LBN);
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efx_mdio_write(efx, MDIO_MMD_PCS, TXC_MTDIABLO_CTRL, ctrl);
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/* The BIST app. note lists these as 3 distinct steps. */
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/* Set the BIST type */
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bctl = (test << TXC_BIST_CTRL_TYPE_LBN);
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efx_mdio_write(efx, mmd, TXC_BIST_CTL, bctl);
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/* Set the BSTEN bit in the BIST Control register to enable */
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bctl |= (1 << TXC_BIST_CTRL_ENAB_LBN);
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efx_mdio_write(efx, mmd, TXC_BIST_CTL, bctl);
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/* Set the BSTRT bit in the BIST Control register */
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efx_mdio_write(efx, mmd, TXC_BIST_CTL,
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bctl | (1 << TXC_BIST_CTRL_STRT_LBN));
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/* Wait. */
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udelay(TXC_BIST_DURATION);
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/* Set the BSTOP bit in the BIST Control register */
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bctl |= (1 << TXC_BIST_CTRL_STOP_LBN);
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efx_mdio_write(efx, mmd, TXC_BIST_CTL, bctl);
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/* The STOP bit should go off when things have stopped */
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while (bctl & (1 << TXC_BIST_CTRL_STOP_LBN))
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bctl = efx_mdio_read(efx, mmd, TXC_BIST_CTL);
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/* Check all the error counts are 0 and all the frame counts are
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non-zero */
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for (lane = 0; lane < 4; lane++) {
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int count = efx_mdio_read(efx, mmd, TXC_BIST_RX0ERRCNT + lane);
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if (count != 0) {
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netif_err(efx, hw, efx->net_dev, TXCNAME": BIST error. "
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"Lane %d had %d errs\n", lane, count);
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rc = -EIO;
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}
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count = efx_mdio_read(efx, mmd, TXC_BIST_RX0FRMCNT + lane);
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if (count == 0) {
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netif_err(efx, hw, efx->net_dev, TXCNAME": BIST error. "
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"Lane %d got 0 frames\n", lane);
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rc = -EIO;
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}
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||||
}
|
||||
|
||||
if (rc == 0)
|
||||
netif_info(efx, hw, efx->net_dev, TXCNAME": BIST pass\n");
|
||||
|
||||
/* Disable BIST */
|
||||
efx_mdio_write(efx, mmd, TXC_BIST_CTL, 0);
|
||||
|
||||
/* Turn off loopback */
|
||||
ctrl &= ~(1 << TXC_MTDIABLO_CTRL_PMA_LOOP_LBN);
|
||||
efx_mdio_write(efx, MDIO_MMD_PCS, TXC_MTDIABLO_CTRL, ctrl);
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
static int txc_bist(struct efx_nic *efx)
|
||||
{
|
||||
return txc_bist_one(efx, MDIO_MMD_PCS, TXC_BIST_CTRL_TYPE_TSD);
|
||||
}
|
||||
|
||||
/* Push the non-configurable defaults into the PHY. This must be
|
||||
* done after every full reset */
|
||||
static void txc_apply_defaults(struct efx_nic *efx)
|
||||
{
|
||||
int mctrl;
|
||||
|
||||
/* Turn amplitude down and preemphasis off on the host side
|
||||
* (PHY<->MAC) as this is believed less likely to upset Falcon
|
||||
* and no adverse effects have been noted. It probably also
|
||||
* saves a picowatt or two */
|
||||
|
||||
/* Turn off preemphasis */
|
||||
efx_mdio_write(efx, MDIO_MMD_PHYXS, TXC_ALRGS_ATXPRE0, TXC_ATXPRE_NONE);
|
||||
efx_mdio_write(efx, MDIO_MMD_PHYXS, TXC_ALRGS_ATXPRE1, TXC_ATXPRE_NONE);
|
||||
|
||||
/* Turn down the amplitude */
|
||||
efx_mdio_write(efx, MDIO_MMD_PHYXS,
|
||||
TXC_ALRGS_ATXAMP0, TXC_ATXAMP_0820_BOTH);
|
||||
efx_mdio_write(efx, MDIO_MMD_PHYXS,
|
||||
TXC_ALRGS_ATXAMP1, TXC_ATXAMP_0820_BOTH);
|
||||
|
||||
/* Set the line side amplitude and preemphasis to the databook
|
||||
* defaults as an erratum causes them to be 0 on at least some
|
||||
* PHY rev.s */
|
||||
efx_mdio_write(efx, MDIO_MMD_PMAPMD,
|
||||
TXC_ALRGS_ATXPRE0, TXC_ATXPRE_DEFAULT);
|
||||
efx_mdio_write(efx, MDIO_MMD_PMAPMD,
|
||||
TXC_ALRGS_ATXPRE1, TXC_ATXPRE_DEFAULT);
|
||||
efx_mdio_write(efx, MDIO_MMD_PMAPMD,
|
||||
TXC_ALRGS_ATXAMP0, TXC_ATXAMP_DEFAULT);
|
||||
efx_mdio_write(efx, MDIO_MMD_PMAPMD,
|
||||
TXC_ALRGS_ATXAMP1, TXC_ATXAMP_DEFAULT);
|
||||
|
||||
/* Set up the LEDs */
|
||||
mctrl = efx_mdio_read(efx, MDIO_MMD_PHYXS, TXC_MRGS_CTL);
|
||||
|
||||
/* Set the Green and Red LEDs to their default modes */
|
||||
mctrl &= ~((1 << TXC_MCTL_TXLED_LBN) | (1 << TXC_MCTL_RXLED_LBN));
|
||||
efx_mdio_write(efx, MDIO_MMD_PHYXS, TXC_MRGS_CTL, mctrl);
|
||||
|
||||
/* Databook recommends doing this after configuration changes */
|
||||
txc_reset_logic(efx);
|
||||
|
||||
falcon_board(efx)->type->init_phy(efx);
|
||||
}
|
||||
|
||||
static int txc43128_phy_probe(struct efx_nic *efx)
|
||||
{
|
||||
struct txc43128_data *phy_data;
|
||||
|
||||
/* Allocate phy private storage */
|
||||
phy_data = kzalloc(sizeof(*phy_data), GFP_KERNEL);
|
||||
if (!phy_data)
|
||||
return -ENOMEM;
|
||||
efx->phy_data = phy_data;
|
||||
phy_data->phy_mode = efx->phy_mode;
|
||||
|
||||
efx->mdio.mmds = TXC_REQUIRED_DEVS;
|
||||
efx->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
|
||||
|
||||
efx->loopback_modes = TXC_LOOPBACKS | FALCON_XMAC_LOOPBACKS;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Initialisation entry point for this PHY driver */
|
||||
static int txc43128_phy_init(struct efx_nic *efx)
|
||||
{
|
||||
int rc;
|
||||
|
||||
rc = txc_reset_phy(efx);
|
||||
if (rc < 0)
|
||||
return rc;
|
||||
|
||||
rc = txc_bist(efx);
|
||||
if (rc < 0)
|
||||
return rc;
|
||||
|
||||
txc_apply_defaults(efx);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Set the lane power down state in the global registers */
|
||||
static void txc_glrgs_lane_power(struct efx_nic *efx, int mmd)
|
||||
{
|
||||
int pd = (1 << TXC_GLCMD_L01PD_LBN) | (1 << TXC_GLCMD_L23PD_LBN);
|
||||
int ctl = efx_mdio_read(efx, mmd, TXC_GLRGS_GLCMD);
|
||||
|
||||
if (!(efx->phy_mode & PHY_MODE_LOW_POWER))
|
||||
ctl &= ~pd;
|
||||
else
|
||||
ctl |= pd;
|
||||
|
||||
efx_mdio_write(efx, mmd, TXC_GLRGS_GLCMD, ctl);
|
||||
}
|
||||
|
||||
/* Set the lane power down state in the analog control registers */
|
||||
static void txc_analog_lane_power(struct efx_nic *efx, int mmd)
|
||||
{
|
||||
int txpd = (1 << TXC_ATXCTL_TXPD3_LBN) | (1 << TXC_ATXCTL_TXPD2_LBN)
|
||||
| (1 << TXC_ATXCTL_TXPD1_LBN) | (1 << TXC_ATXCTL_TXPD0_LBN);
|
||||
int rxpd = (1 << TXC_ARXCTL_RXPD3_LBN) | (1 << TXC_ARXCTL_RXPD2_LBN)
|
||||
| (1 << TXC_ARXCTL_RXPD1_LBN) | (1 << TXC_ARXCTL_RXPD0_LBN);
|
||||
int txctl = efx_mdio_read(efx, mmd, TXC_ALRGS_ATXCTL);
|
||||
int rxctl = efx_mdio_read(efx, mmd, TXC_ALRGS_ARXCTL);
|
||||
|
||||
if (!(efx->phy_mode & PHY_MODE_LOW_POWER)) {
|
||||
txctl &= ~txpd;
|
||||
rxctl &= ~rxpd;
|
||||
} else {
|
||||
txctl |= txpd;
|
||||
rxctl |= rxpd;
|
||||
}
|
||||
|
||||
efx_mdio_write(efx, mmd, TXC_ALRGS_ATXCTL, txctl);
|
||||
efx_mdio_write(efx, mmd, TXC_ALRGS_ARXCTL, rxctl);
|
||||
}
|
||||
|
||||
static void txc_set_power(struct efx_nic *efx)
|
||||
{
|
||||
/* According to the data book, all the MMDs can do low power */
|
||||
efx_mdio_set_mmds_lpower(efx,
|
||||
!!(efx->phy_mode & PHY_MODE_LOW_POWER),
|
||||
TXC_REQUIRED_DEVS);
|
||||
|
||||
/* Global register bank is in PCS, PHY XS. These control the host
|
||||
* side and line side settings respectively. */
|
||||
txc_glrgs_lane_power(efx, MDIO_MMD_PCS);
|
||||
txc_glrgs_lane_power(efx, MDIO_MMD_PHYXS);
|
||||
|
||||
/* Analog register bank in PMA/PMD, PHY XS */
|
||||
txc_analog_lane_power(efx, MDIO_MMD_PMAPMD);
|
||||
txc_analog_lane_power(efx, MDIO_MMD_PHYXS);
|
||||
}
|
||||
|
||||
static void txc_reset_logic_mmd(struct efx_nic *efx, int mmd)
|
||||
{
|
||||
int val = efx_mdio_read(efx, mmd, TXC_GLRGS_GLCMD);
|
||||
int tries = 50;
|
||||
|
||||
val |= (1 << TXC_GLCMD_LMTSWRST_LBN);
|
||||
efx_mdio_write(efx, mmd, TXC_GLRGS_GLCMD, val);
|
||||
while (tries--) {
|
||||
val = efx_mdio_read(efx, mmd, TXC_GLRGS_GLCMD);
|
||||
if (!(val & (1 << TXC_GLCMD_LMTSWRST_LBN)))
|
||||
break;
|
||||
udelay(1);
|
||||
}
|
||||
if (!tries)
|
||||
netif_info(efx, hw, efx->net_dev,
|
||||
TXCNAME " Logic reset timed out!\n");
|
||||
}
|
||||
|
||||
/* Perform a logic reset. This preserves the configuration registers
|
||||
* and is needed for some configuration changes to take effect */
|
||||
static void txc_reset_logic(struct efx_nic *efx)
|
||||
{
|
||||
/* The data sheet claims we can do the logic reset on either the
|
||||
* PCS or the PHYXS and the result is a reset of both host- and
|
||||
* line-side logic. */
|
||||
txc_reset_logic_mmd(efx, MDIO_MMD_PCS);
|
||||
}
|
||||
|
||||
static bool txc43128_phy_read_link(struct efx_nic *efx)
|
||||
{
|
||||
return efx_mdio_links_ok(efx, TXC_REQUIRED_DEVS);
|
||||
}
|
||||
|
||||
static int txc43128_phy_reconfigure(struct efx_nic *efx)
|
||||
{
|
||||
struct txc43128_data *phy_data = efx->phy_data;
|
||||
enum efx_phy_mode mode_change = efx->phy_mode ^ phy_data->phy_mode;
|
||||
bool loop_change = LOOPBACK_CHANGED(phy_data, efx, TXC_LOOPBACKS);
|
||||
|
||||
if (efx->phy_mode & mode_change & PHY_MODE_TX_DISABLED) {
|
||||
txc_reset_phy(efx);
|
||||
txc_apply_defaults(efx);
|
||||
falcon_reset_xaui(efx);
|
||||
mode_change &= ~PHY_MODE_TX_DISABLED;
|
||||
}
|
||||
|
||||
efx_mdio_transmit_disable(efx);
|
||||
efx_mdio_phy_reconfigure(efx);
|
||||
if (mode_change & PHY_MODE_LOW_POWER)
|
||||
txc_set_power(efx);
|
||||
|
||||
/* The data sheet claims this is required after every reconfiguration
|
||||
* (note at end of 7.1), but we mustn't do it when nothing changes as
|
||||
* it glitches the link, and reconfigure gets called on link change,
|
||||
* so we get an IRQ storm on link up. */
|
||||
if (loop_change || mode_change)
|
||||
txc_reset_logic(efx);
|
||||
|
||||
phy_data->phy_mode = efx->phy_mode;
|
||||
phy_data->loopback_mode = efx->loopback_mode;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void txc43128_phy_fini(struct efx_nic *efx)
|
||||
{
|
||||
/* Disable link events */
|
||||
efx_mdio_write(efx, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_CTRL, 0);
|
||||
}
|
||||
|
||||
static void txc43128_phy_remove(struct efx_nic *efx)
|
||||
{
|
||||
kfree(efx->phy_data);
|
||||
efx->phy_data = NULL;
|
||||
}
|
||||
|
||||
/* Periodic callback: this exists mainly to poll link status as we
|
||||
* don't use LASI interrupts */
|
||||
static bool txc43128_phy_poll(struct efx_nic *efx)
|
||||
{
|
||||
struct txc43128_data *data = efx->phy_data;
|
||||
bool was_up = efx->link_state.up;
|
||||
|
||||
efx->link_state.up = txc43128_phy_read_link(efx);
|
||||
efx->link_state.speed = 10000;
|
||||
efx->link_state.fd = true;
|
||||
efx->link_state.fc = efx->wanted_fc;
|
||||
|
||||
if (efx->link_state.up || (efx->loopback_mode != LOOPBACK_NONE)) {
|
||||
data->bug10934_timer = jiffies;
|
||||
} else {
|
||||
if (time_after_eq(jiffies, (data->bug10934_timer +
|
||||
BUG10934_RESET_INTERVAL))) {
|
||||
data->bug10934_timer = jiffies;
|
||||
txc_reset_logic(efx);
|
||||
}
|
||||
}
|
||||
|
||||
return efx->link_state.up != was_up;
|
||||
}
|
||||
|
||||
static const char *txc43128_test_names[] = {
|
||||
"bist"
|
||||
};
|
||||
|
||||
static const char *txc43128_test_name(struct efx_nic *efx, unsigned int index)
|
||||
{
|
||||
if (index < ARRAY_SIZE(txc43128_test_names))
|
||||
return txc43128_test_names[index];
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static int txc43128_run_tests(struct efx_nic *efx, int *results, unsigned flags)
|
||||
{
|
||||
int rc;
|
||||
|
||||
if (!(flags & ETH_TEST_FL_OFFLINE))
|
||||
return 0;
|
||||
|
||||
rc = txc_reset_phy(efx);
|
||||
if (rc < 0)
|
||||
return rc;
|
||||
|
||||
rc = txc_bist(efx);
|
||||
txc_apply_defaults(efx);
|
||||
results[0] = rc ? -1 : 1;
|
||||
return rc;
|
||||
}
|
||||
|
||||
static void txc43128_get_settings(struct efx_nic *efx, struct ethtool_cmd *ecmd)
|
||||
{
|
||||
mdio45_ethtool_gset(&efx->mdio, ecmd);
|
||||
}
|
||||
|
||||
struct efx_phy_operations falcon_txc_phy_ops = {
|
||||
.probe = txc43128_phy_probe,
|
||||
.init = txc43128_phy_init,
|
||||
.reconfigure = txc43128_phy_reconfigure,
|
||||
.poll = txc43128_phy_poll,
|
||||
.fini = txc43128_phy_fini,
|
||||
.remove = txc43128_phy_remove,
|
||||
.get_settings = txc43128_get_settings,
|
||||
.set_settings = efx_mdio_set_settings,
|
||||
.test_alive = efx_mdio_test_alive,
|
||||
.run_tests = txc43128_run_tests,
|
||||
.test_name = txc43128_test_name,
|
||||
};
|
||||
Loading…
Reference in a new issue