ARM: SoC fixes for 3.4-rc
Things have slowed down a lot for us, but we have five more fixes for omap and kirkwood below. Three are for boards setup issues, two are SoC-level fixes. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIcBAABAgAGBQJPqpiAAAoJEIwa5zzehBx36WcP/A3yfgwccYQPAGiazDWMoxj+ bLdr49L4tgFf8dwRno+IeAKjhhBDYUJgNoz46Tnqfh1L7ImIvGUlPDtqfQGb5+HK HZ+mz46ZUoJPdvBS8CY7Xf5lP/5iiMI+wBeE33bu+EyKhgbD8wYmQDCsJJhjjRLW TqR/a74Mz/yX9sCL5pZ/ktKhxV/FvBMT3pqpU8Eb50hDtStTouf25EmyLv0iVmJx 45pwG3+nx6R+/Lu2rwCroKUTl/cNR95L9+EGMzb99aZXSsGS5zmiAEQ2TNcp0lxb JMR3bB9zTDWmY1VZ83os2NI1GDOj1Zdvqns/iiBRKLUBvFN447tMdRvZMomvM3VQ whiKd5R0aFa42KROZq7V+t540FeLqgDvHY4zeOPDRGrh1Y9ElgCJnciX4Hxm779n KH9VlnHrUW3tNHqlLKXTJ1tuvNSbNUE2FtG/m+oJLyUyH4CJzNi1R1rofZEEHEH/ 8zeJzw6amwpSWyLEi1HjyhFOJ8WqOnY17LMWilQeeYbqHGwXGKTOmm9P8PKPk4cx dFlwCeJgd7VL+L5rn8LVOjvov7j1iakKZhtSjLMjF4k088MejDVOfTj21Qs5MiHI nl03BOvtmwEGXUbYHKromzeHMvoXXWuQyK13cWmgBXAiAGgX76mNU9GukwXU3rqm TGrRTsiuGzYQn9w3EVFL =GX6x -----END PGP SIGNATURE----- Merge tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM: SoC fixes from Olof Johansson: "Things have slowed down a lot for us, but we have five more fixes for omap and kirkwood below. Three are for boards setup issues, two are SoC-level fixes." * tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: ARM: OMAP: igep0020: fix smsc911x dummy regulator id ARM: orion5x: Fix GPIO enable bits for MPP9 ARM: kirkwood: add missing kexec.h include ARM: OMAP: Revert "ARM: OMAP: ctrl: Fix CONTROL_DSIPHY register fields" ARM: OMAP1: Amstrad Delta: Fix wrong IRQ base in FIQ handler
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commit
7ee94d97aa
5 changed files with 9 additions and 8 deletions
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@ -14,6 +14,7 @@
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#include <linux/init.h>
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#include <linux/of.h>
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#include <linux/of_platform.h>
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#include <linux/kexec.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <mach/bridge-regs.h>
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@ -48,7 +48,7 @@ static irqreturn_t deferred_fiq(int irq, void *dev_id)
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struct irq_chip *irq_chip = NULL;
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int gpio, irq_num, fiq_count;
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irq_desc = irq_to_desc(IH_GPIO_BASE);
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irq_desc = irq_to_desc(gpio_to_irq(AMS_DELTA_GPIO_PIN_KEYBRD_CLK));
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if (irq_desc)
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irq_chip = irq_desc->irq_data.chip;
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@ -641,7 +641,7 @@ static struct regulator_consumer_supply dummy_supplies[] = {
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static void __init igep_init(void)
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{
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regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
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regulator_register_fixed(1, dummy_supplies, ARRAY_SIZE(dummy_supplies));
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omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
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/* Get IGEP2 hardware revision */
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@ -941,10 +941,10 @@
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#define OMAP4_DSI2_LANEENABLE_MASK (0x7 << 29)
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#define OMAP4_DSI1_LANEENABLE_SHIFT 24
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#define OMAP4_DSI1_LANEENABLE_MASK (0x1f << 24)
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#define OMAP4_DSI2_PIPD_SHIFT 19
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#define OMAP4_DSI2_PIPD_MASK (0x1f << 19)
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#define OMAP4_DSI1_PIPD_SHIFT 14
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#define OMAP4_DSI1_PIPD_MASK (0x1f << 14)
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#define OMAP4_DSI1_PIPD_SHIFT 19
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#define OMAP4_DSI1_PIPD_MASK (0x1f << 19)
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#define OMAP4_DSI2_PIPD_SHIFT 14
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#define OMAP4_DSI2_PIPD_MASK (0x1f << 14)
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/* CONTROL_MCBSPLP */
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#define OMAP4_ALBCTRLRX_FSX_SHIFT 31
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@ -65,8 +65,8 @@
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#define MPP8_GIGE MPP(8, 0x1, 0, 0, 1, 1, 1)
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#define MPP9_UNUSED MPP(9, 0x0, 0, 0, 1, 1, 1)
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#define MPP9_GPIO MPP(9, 0x0, 0, 0, 1, 1, 1)
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#define MPP9_GIGE MPP(9, 0x1, 1, 1, 1, 1, 1)
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#define MPP9_GPIO MPP(9, 0x0, 1, 1, 1, 1, 1)
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#define MPP9_GIGE MPP(9, 0x1, 0, 0, 1, 1, 1)
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#define MPP10_UNUSED MPP(10, 0x0, 0, 0, 1, 1, 1)
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#define MPP10_GPIO MPP(10, 0x0, 1, 1, 1, 1, 1)
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