ARM: mmp: remove unused definition in APBC and APMU
Signed-off-by: Chao Xie <xiechao.mail@gmail.com> Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
This commit is contained in:
Chao Xie
Haojian Zhuang
parent
8430305dc3
commit
7f744b1714
2 changed files with 0 additions and 110 deletions
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@ -13,101 +13,6 @@
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#include <mach/addr-map.h>
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/*
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* APB clock register offsets for PXA168
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*/
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#define APBC_PXA168_UART1 APBC_REG(0x000)
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#define APBC_PXA168_UART2 APBC_REG(0x004)
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#define APBC_PXA168_GPIO APBC_REG(0x008)
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#define APBC_PXA168_PWM1 APBC_REG(0x00c)
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#define APBC_PXA168_PWM2 APBC_REG(0x010)
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#define APBC_PXA168_PWM3 APBC_REG(0x014)
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#define APBC_PXA168_PWM4 APBC_REG(0x018)
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#define APBC_PXA168_RTC APBC_REG(0x028)
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#define APBC_PXA168_TWSI0 APBC_REG(0x02c)
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#define APBC_PXA168_KPC APBC_REG(0x030)
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#define APBC_PXA168_TIMERS APBC_REG(0x034)
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#define APBC_PXA168_AIB APBC_REG(0x03c)
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#define APBC_PXA168_SW_JTAG APBC_REG(0x040)
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#define APBC_PXA168_ONEWIRE APBC_REG(0x048)
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#define APBC_PXA168_ASFAR APBC_REG(0x050)
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#define APBC_PXA168_ASSAR APBC_REG(0x054)
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#define APBC_PXA168_TWSI1 APBC_REG(0x06c)
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#define APBC_PXA168_UART3 APBC_REG(0x070)
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#define APBC_PXA168_AC97 APBC_REG(0x084)
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#define APBC_PXA168_SSP1 APBC_REG(0x81c)
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#define APBC_PXA168_SSP2 APBC_REG(0x820)
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#define APBC_PXA168_SSP3 APBC_REG(0x84c)
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#define APBC_PXA168_SSP4 APBC_REG(0x858)
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#define APBC_PXA168_SSP5 APBC_REG(0x85c)
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/*
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* APB Clock register offsets for PXA910
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*/
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#define APBC_PXA910_UART0 APBC_REG(0x000)
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#define APBC_PXA910_UART1 APBC_REG(0x004)
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#define APBC_PXA910_GPIO APBC_REG(0x008)
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#define APBC_PXA910_PWM1 APBC_REG(0x00c)
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#define APBC_PXA910_PWM2 APBC_REG(0x010)
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#define APBC_PXA910_PWM3 APBC_REG(0x014)
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#define APBC_PXA910_PWM4 APBC_REG(0x018)
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#define APBC_PXA910_SSP1 APBC_REG(0x01c)
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#define APBC_PXA910_SSP2 APBC_REG(0x020)
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#define APBC_PXA910_IPC APBC_REG(0x024)
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#define APBC_PXA910_RTC APBC_REG(0x028)
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#define APBC_PXA910_TWSI0 APBC_REG(0x02c)
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#define APBC_PXA910_KPC APBC_REG(0x030)
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#define APBC_PXA910_TIMERS APBC_REG(0x034)
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#define APBC_PXA910_TBROT APBC_REG(0x038)
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#define APBC_PXA910_AIB APBC_REG(0x03c)
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#define APBC_PXA910_SW_JTAG APBC_REG(0x040)
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#define APBC_PXA910_TIMERS1 APBC_REG(0x044)
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#define APBC_PXA910_ONEWIRE APBC_REG(0x048)
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#define APBC_PXA910_SSP3 APBC_REG(0x04c)
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#define APBC_PXA910_ASFAR APBC_REG(0x050)
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#define APBC_PXA910_ASSAR APBC_REG(0x054)
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/*
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* APB Clock register offsets for MMP2
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*/
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#define APBC_MMP2_RTC APBC_REG(0x000)
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#define APBC_MMP2_TWSI1 APBC_REG(0x004)
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#define APBC_MMP2_TWSI2 APBC_REG(0x008)
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#define APBC_MMP2_TWSI3 APBC_REG(0x00c)
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#define APBC_MMP2_TWSI4 APBC_REG(0x010)
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#define APBC_MMP2_ONEWIRE APBC_REG(0x014)
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#define APBC_MMP2_KPC APBC_REG(0x018)
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#define APBC_MMP2_TB_ROTARY APBC_REG(0x01c)
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#define APBC_MMP2_SW_JTAG APBC_REG(0x020)
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#define APBC_MMP2_TIMERS APBC_REG(0x024)
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#define APBC_MMP2_UART1 APBC_REG(0x02c)
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#define APBC_MMP2_UART2 APBC_REG(0x030)
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#define APBC_MMP2_UART3 APBC_REG(0x034)
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#define APBC_MMP2_GPIO APBC_REG(0x038)
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#define APBC_MMP2_PWM0 APBC_REG(0x03c)
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#define APBC_MMP2_PWM1 APBC_REG(0x040)
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#define APBC_MMP2_PWM2 APBC_REG(0x044)
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#define APBC_MMP2_PWM3 APBC_REG(0x048)
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#define APBC_MMP2_SSP0 APBC_REG(0x04c)
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#define APBC_MMP2_SSP1 APBC_REG(0x050)
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#define APBC_MMP2_SSP2 APBC_REG(0x054)
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#define APBC_MMP2_SSP3 APBC_REG(0x058)
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#define APBC_MMP2_SSP4 APBC_REG(0x05c)
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#define APBC_MMP2_SSP5 APBC_REG(0x060)
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#define APBC_MMP2_AIB APBC_REG(0x064)
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#define APBC_MMP2_ASFAR APBC_REG(0x068)
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#define APBC_MMP2_ASSAR APBC_REG(0x06c)
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#define APBC_MMP2_USIM APBC_REG(0x070)
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#define APBC_MMP2_MPMU APBC_REG(0x074)
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#define APBC_MMP2_IPC APBC_REG(0x078)
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#define APBC_MMP2_TWSI5 APBC_REG(0x07c)
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#define APBC_MMP2_TWSI6 APBC_REG(0x080)
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#define APBC_MMP2_TWSI_INTSTS APBC_REG(0x084)
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#define APBC_MMP2_UART4 APBC_REG(0x088)
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#define APBC_MMP2_RIPC APBC_REG(0x08c)
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#define APBC_MMP2_THSENS1 APBC_REG(0x090) /* Thermal Sensor */
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#define APBC_MMP2_THSENS_INTSTS APBC_REG(0x0a4)
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/* Common APB clock register bit definitions */
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#define APBC_APBCLK (1 << 0) /* APB Bus Clock Enable */
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#define APBC_FNCLK (1 << 1) /* Functional Clock Enable */
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@ -13,21 +13,6 @@
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#include <mach/addr-map.h>
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/* Clock Reset Control */
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#define APMU_IRE APMU_REG(0x048)
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#define APMU_LCD APMU_REG(0x04c)
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#define APMU_CCIC APMU_REG(0x050)
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#define APMU_SDH0 APMU_REG(0x054)
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#define APMU_SDH1 APMU_REG(0x058)
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#define APMU_USB APMU_REG(0x05c)
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#define APMU_NAND APMU_REG(0x060)
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#define APMU_DMA APMU_REG(0x064)
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#define APMU_GEU APMU_REG(0x068)
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#define APMU_BUS APMU_REG(0x06c)
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#define APMU_SDH2 APMU_REG(0x0e8)
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#define APMU_SDH3 APMU_REG(0x0ec)
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#define APMU_ETH APMU_REG(0x0fc)
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#define APMU_FNCLK_EN (1 << 4)
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#define APMU_AXICLK_EN (1 << 3)
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#define APMU_FNRST_DIS (1 << 1)
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