[PATCH] spi: use linked lists rather than an array
This makes the SPI core and its users access transfers in the SPI message structure as linked list not as an array, as discussed on LKML. From: David Brownell <dbrownell@users.sourceforge.net> Updates including doc, bugfixes to the list code, add spi_message_add_tail(). Plus, initialize things _before_ grabbing the locks in some cases (in case it grows more expensive). This also merges some bitbang updates of mine that didn't yet make it into the mm tree. Signed-off-by: Vitaly Wool <vwool@ru.mvista.com> Signed-off-by: Dmitry Pervushin <dpervushin@gmail.com> Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
Vitaly Wool
Greg Kroah-Hartman
parent
2f9f762879
commit
8275c642cc
7 changed files with 180 additions and 113 deletions
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@ -155,10 +155,13 @@ static int ads7846_read12_ser(struct device *dev, unsigned command)
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struct ser_req *req = kzalloc(sizeof *req, SLAB_KERNEL);
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int status;
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int sample;
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int i;
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if (!req)
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return -ENOMEM;
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INIT_LIST_HEAD(&req->msg.transfers);
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/* activate reference, so it has time to settle; */
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req->xfer[0].tx_buf = &ref_on;
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req->xfer[0].len = 1;
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@ -192,8 +195,8 @@ static int ads7846_read12_ser(struct device *dev, unsigned command)
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/* group all the transfers together, so we can't interfere with
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* reading touchscreen state; disable penirq while sampling
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*/
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req->msg.transfers = req->xfer;
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req->msg.n_transfer = 6;
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for (i = 0; i < 6; i++)
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spi_message_add_tail(&req->xfer[i], &req->msg);
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disable_irq(spi->irq);
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status = spi_sync(spi, &req->msg);
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@ -398,6 +401,7 @@ static int __devinit ads7846_probe(struct spi_device *spi)
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struct ads7846 *ts;
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struct ads7846_platform_data *pdata = spi->dev.platform_data;
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struct spi_transfer *x;
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int i;
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if (!spi->irq) {
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dev_dbg(&spi->dev, "no IRQ?\n");
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@ -500,8 +504,8 @@ static int __devinit ads7846_probe(struct spi_device *spi)
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CS_CHANGE(x[-1]);
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ts->msg.transfers = ts->xfer;
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ts->msg.n_transfer = x - ts->xfer;
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for (i = 0; i < x - ts->xfer; i++)
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spi_message_add_tail(&ts->xfer[i], &ts->msg);
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ts->msg.complete = ads7846_rx;
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ts->msg.context = ts;
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@ -245,6 +245,21 @@ static int m25p80_read(struct mtd_info *mtd, loff_t from, size_t len,
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if (from + len > flash->mtd.size)
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return -EINVAL;
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spi_message_init(&m);
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memset(t, 0, (sizeof t));
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t[0].tx_buf = flash->command;
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t[0].len = sizeof(flash->command);
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spi_message_add_tail(&t[0], &m);
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t[1].rx_buf = buf;
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t[1].len = len;
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spi_message_add_tail(&t[1], &m);
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/* Byte count starts at zero. */
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if (retlen)
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*retlen = 0;
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down(&flash->lock);
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/* Wait till previous write/erase is done. */
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@ -254,8 +269,6 @@ static int m25p80_read(struct mtd_info *mtd, loff_t from, size_t len,
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return 1;
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}
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memset(t, 0, (sizeof t));
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/* NOTE: OPCODE_FAST_READ (if available) is faster... */
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/* Set up the write data buffer. */
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@ -264,19 +277,6 @@ static int m25p80_read(struct mtd_info *mtd, loff_t from, size_t len,
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flash->command[2] = from >> 8;
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flash->command[3] = from;
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/* Byte count starts at zero. */
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if (retlen)
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*retlen = 0;
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t[0].tx_buf = flash->command;
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t[0].len = sizeof(flash->command);
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t[1].rx_buf = buf;
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t[1].len = len;
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m.transfers = t;
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m.n_transfer = 2;
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spi_sync(flash->spi, &m);
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*retlen = m.actual_length - sizeof(flash->command);
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@ -313,6 +313,16 @@ static int m25p80_write(struct mtd_info *mtd, loff_t to, size_t len,
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if (to + len > flash->mtd.size)
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return -EINVAL;
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spi_message_init(&m);
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memset(t, 0, (sizeof t));
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t[0].tx_buf = flash->command;
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t[0].len = sizeof(flash->command);
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spi_message_add_tail(&t[0], &m);
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t[1].tx_buf = buf;
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spi_message_add_tail(&t[1], &m);
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down(&flash->lock);
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/* Wait until finished previous write command. */
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@ -321,26 +331,17 @@ static int m25p80_write(struct mtd_info *mtd, loff_t to, size_t len,
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write_enable(flash);
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memset(t, 0, (sizeof t));
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/* Set up the opcode in the write buffer. */
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flash->command[0] = OPCODE_PP;
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flash->command[1] = to >> 16;
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flash->command[2] = to >> 8;
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flash->command[3] = to;
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t[0].tx_buf = flash->command;
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t[0].len = sizeof(flash->command);
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m.transfers = t;
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m.n_transfer = 2;
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/* what page do we start with? */
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page_offset = to % FLASH_PAGESIZE;
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/* do all the bytes fit onto one page? */
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if (page_offset + len <= FLASH_PAGESIZE) {
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t[1].tx_buf = buf;
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t[1].len = len;
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spi_sync(flash->spi, &m);
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@ -352,7 +353,6 @@ static int m25p80_write(struct mtd_info *mtd, loff_t to, size_t len,
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/* the size of data remaining on the first page */
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page_size = FLASH_PAGESIZE - page_offset;
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t[1].tx_buf = buf;
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t[1].len = page_size;
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spi_sync(flash->spi, &m);
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@ -147,7 +147,7 @@ static int dataflash_erase(struct mtd_info *mtd, struct erase_info *instr)
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{
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struct dataflash *priv = (struct dataflash *)mtd->priv;
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struct spi_device *spi = priv->spi;
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struct spi_transfer x[1] = { { .tx_dma = 0, }, };
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struct spi_transfer x = { .tx_dma = 0, };
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struct spi_message msg;
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unsigned blocksize = priv->page_size << 3;
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u8 *command;
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@ -162,10 +162,11 @@ static int dataflash_erase(struct mtd_info *mtd, struct erase_info *instr)
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|| (instr->addr % priv->page_size) != 0)
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return -EINVAL;
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x[0].tx_buf = command = priv->command;
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x[0].len = 4;
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msg.transfers = x;
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msg.n_transfer = 1;
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spi_message_init(&msg);
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x.tx_buf = command = priv->command;
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x.len = 4;
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spi_message_add_tail(&x, &msg);
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down(&priv->lock);
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while (instr->len > 0) {
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@ -256,12 +257,15 @@ static int dataflash_read(struct mtd_info *mtd, loff_t from, size_t len,
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DEBUG(MTD_DEBUG_LEVEL3, "READ: (%x) %x %x %x\n",
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command[0], command[1], command[2], command[3]);
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spi_message_init(&msg);
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x[0].tx_buf = command;
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x[0].len = 8;
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spi_message_add_tail(&x[0], &msg);
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x[1].rx_buf = buf;
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x[1].len = len;
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msg.transfers = x;
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msg.n_transfer = 2;
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spi_message_add_tail(&x[1], &msg);
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down(&priv->lock);
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@ -320,9 +324,11 @@ static int dataflash_write(struct mtd_info *mtd, loff_t to, size_t len,
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if ((to + len) > mtd->size)
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return -EINVAL;
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spi_message_init(&msg);
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x[0].tx_buf = command = priv->command;
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x[0].len = 4;
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msg.transfers = x;
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spi_message_add_tail(&x[0], &msg);
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pageaddr = ((unsigned)to / priv->page_size);
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offset = ((unsigned)to % priv->page_size);
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@ -364,7 +370,6 @@ static int dataflash_write(struct mtd_info *mtd, loff_t to, size_t len,
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DEBUG(MTD_DEBUG_LEVEL3, "TRANSFER: (%x) %x %x %x\n",
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command[0], command[1], command[2], command[3]);
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msg.n_transfer = 1;
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status = spi_sync(spi, &msg);
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if (status < 0)
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DEBUG(MTD_DEBUG_LEVEL1, "%s: xfer %u -> %d \n",
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@ -385,14 +390,16 @@ static int dataflash_write(struct mtd_info *mtd, loff_t to, size_t len,
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x[1].tx_buf = writebuf;
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x[1].len = writelen;
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msg.n_transfer = 2;
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spi_message_add_tail(x + 1, &msg);
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status = spi_sync(spi, &msg);
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spi_transfer_del(x + 1);
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if (status < 0)
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DEBUG(MTD_DEBUG_LEVEL1, "%s: pgm %u/%u -> %d \n",
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spi->dev.bus_id, addr, writelen, status);
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(void) dataflash_waitready(priv->spi);
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#ifdef CONFIG_DATAFLASH_WRITE_VERIFY
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/* (3) Compare to Buffer1 */
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@ -405,7 +412,6 @@ static int dataflash_write(struct mtd_info *mtd, loff_t to, size_t len,
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DEBUG(MTD_DEBUG_LEVEL3, "COMPARE: (%x) %x %x %x\n",
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command[0], command[1], command[2], command[3]);
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msg.n_transfer = 1;
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status = spi_sync(spi, &msg);
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if (status < 0)
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DEBUG(MTD_DEBUG_LEVEL1, "%s: compare %u -> %d \n",
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@ -557,6 +557,17 @@ int spi_write_then_read(struct spi_device *spi,
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if ((n_tx + n_rx) > SPI_BUFSIZ)
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return -EINVAL;
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spi_message_init(&message);
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memset(x, 0, sizeof x);
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if (n_tx) {
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x[0].len = n_tx;
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spi_message_add_tail(&x[0], &message);
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}
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if (n_rx) {
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x[1].len = n_rx;
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spi_message_add_tail(&x[1], &message);
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}
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/* ... unless someone else is using the pre-allocated buffer */
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if (down_trylock(&lock)) {
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local_buf = kmalloc(SPI_BUFSIZ, GFP_KERNEL);
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@ -565,18 +576,11 @@ int spi_write_then_read(struct spi_device *spi,
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} else
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local_buf = buf;
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memset(x, 0, sizeof x);
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memcpy(local_buf, txbuf, n_tx);
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x[0].tx_buf = local_buf;
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x[0].len = n_tx;
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x[1].rx_buf = local_buf + n_tx;
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x[1].len = n_rx;
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/* do the i/o */
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message.transfers = x;
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message.n_transfer = ARRAY_SIZE(x);
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status = spi_sync(spi, &message);
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if (status == 0) {
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memcpy(rxbuf, x[1].rx_buf, n_rx);
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@ -146,6 +146,9 @@ int spi_bitbang_setup(struct spi_device *spi)
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struct spi_bitbang_cs *cs = spi->controller_state;
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struct spi_bitbang *bitbang;
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if (!spi->max_speed_hz)
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return -EINVAL;
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if (!cs) {
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cs = kzalloc(sizeof *cs, SLAB_KERNEL);
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if (!cs)
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@ -172,13 +175,8 @@ int spi_bitbang_setup(struct spi_device *spi)
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if (!cs->txrx_word)
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return -EINVAL;
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if (!spi->max_speed_hz)
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spi->max_speed_hz = 500 * 1000;
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/* nsecs = max(50, (clock period)/2), be optimistic */
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/* nsecs = (clock period)/2 */
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cs->nsecs = (1000000000/2) / (spi->max_speed_hz);
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if (cs->nsecs < 50)
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cs->nsecs = 50;
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if (cs->nsecs > MAX_UDELAY_MS * 1000)
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return -EINVAL;
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@ -194,7 +192,7 @@ int spi_bitbang_setup(struct spi_device *spi)
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/* deselect chip (low or high) */
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spin_lock(&bitbang->lock);
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if (!bitbang->busy) {
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bitbang->chipselect(spi, 0);
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bitbang->chipselect(spi, BITBANG_CS_INACTIVE);
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ndelay(cs->nsecs);
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}
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spin_unlock(&bitbang->lock);
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@ -244,9 +242,9 @@ static void bitbang_work(void *_bitbang)
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struct spi_message *m;
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struct spi_device *spi;
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unsigned nsecs;
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struct spi_transfer *t;
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struct spi_transfer *t = NULL;
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unsigned tmp;
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unsigned chipselect;
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unsigned cs_change;
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int status;
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m = container_of(bitbang->queue.next, struct spi_message,
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@ -254,37 +252,49 @@ static void bitbang_work(void *_bitbang)
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list_del_init(&m->queue);
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spin_unlock_irqrestore(&bitbang->lock, flags);
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// FIXME this is made-up
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nsecs = 100;
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/* FIXME this is made-up ... the correct value is known to
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* word-at-a-time bitbang code, and presumably chipselect()
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* should enforce these requirements too?
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*/
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nsecs = 100;
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spi = m->spi;
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t = m->transfers;
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tmp = 0;
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chipselect = 0;
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cs_change = 1;
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status = 0;
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for (;;t++) {
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list_for_each_entry (t, &m->transfers, transfer_list) {
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if (bitbang->shutdown) {
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status = -ESHUTDOWN;
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break;
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}
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/* set up default clock polarity, and activate chip */
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if (!chipselect) {
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bitbang->chipselect(spi, 1);
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/* set up default clock polarity, and activate chip;
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* this implicitly updates clock and spi modes as
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* previously recorded for this device via setup().
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* (and also deselects any other chip that might be
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* selected ...)
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*/
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if (cs_change) {
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bitbang->chipselect(spi, BITBANG_CS_ACTIVE);
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ndelay(nsecs);
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}
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cs_change = t->cs_change;
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if (!t->tx_buf && !t->rx_buf && t->len) {
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status = -EINVAL;
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break;
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}
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/* transfer data */
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/* transfer data. the lower level code handles any
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* new dma mappings it needs. our caller always gave
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* us dma-safe buffers.
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*/
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if (t->len) {
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/* FIXME if bitbang->use_dma, dma_map_single()
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* before the transfer, and dma_unmap_single()
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* afterwards, for either or both buffers...
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/* REVISIT dma API still needs a designated
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* DMA_ADDR_INVALID; ~0 might be better.
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*/
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if (!m->is_dma_mapped)
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t->rx_dma = t->tx_dma = 0;
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status = bitbang->txrx_bufs(spi, t);
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}
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if (status != t->len) {
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@ -299,29 +309,31 @@ nsecs = 100;
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if (t->delay_usecs)
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udelay(t->delay_usecs);
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tmp++;
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if (tmp >= m->n_transfer)
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if (!cs_change)
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continue;
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if (t->transfer_list.next == &m->transfers)
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break;
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chipselect = !t->cs_change;
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if (chipselect);
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continue;
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bitbang->chipselect(spi, 0);
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/* REVISIT do we want the udelay here instead? */
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msleep(1);
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/* sometimes a short mid-message deselect of the chip
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* may be needed to terminate a mode or command
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*/
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ndelay(nsecs);
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bitbang->chipselect(spi, BITBANG_CS_INACTIVE);
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ndelay(nsecs);
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}
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tmp = m->n_transfer - 1;
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tmp = m->transfers[tmp].cs_change;
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m->status = status;
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m->complete(m->context);
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ndelay(2 * nsecs);
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bitbang->chipselect(spi, status == 0 && tmp);
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ndelay(nsecs);
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/* normally deactivate chipselect ... unless no error and
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* cs_change has hinted that the next message will probably
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* be for this chip too.
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*/
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if (!(status == 0 && cs_change)) {
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ndelay(nsecs);
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bitbang->chipselect(spi, BITBANG_CS_INACTIVE);
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ndelay(nsecs);
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||||
}
|
||||
|
||||
spin_lock_irqsave(&bitbang->lock, flags);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -263,15 +263,16 @@ extern struct spi_master *spi_busnum_to_master(u16 busnum);
|
|||
|
||||
/**
|
||||
* struct spi_transfer - a read/write buffer pair
|
||||
* @tx_buf: data to be written (dma-safe address), or NULL
|
||||
* @rx_buf: data to be read (dma-safe address), or NULL
|
||||
* @tx_dma: DMA address of buffer, if spi_message.is_dma_mapped
|
||||
* @rx_dma: DMA address of buffer, if spi_message.is_dma_mapped
|
||||
* @tx_buf: data to be written (dma-safe memory), or NULL
|
||||
* @rx_buf: data to be read (dma-safe memory), or NULL
|
||||
* @tx_dma: DMA address of tx_buf, if spi_message.is_dma_mapped
|
||||
* @rx_dma: DMA address of rx_buf, if spi_message.is_dma_mapped
|
||||
* @len: size of rx and tx buffers (in bytes)
|
||||
* @cs_change: affects chipselect after this transfer completes
|
||||
* @delay_usecs: microseconds to delay after this transfer before
|
||||
* (optionally) changing the chipselect status, then starting
|
||||
* the next transfer or completing this spi_message.
|
||||
* @transfer_list: transfers are sequenced through spi_message.transfers
|
||||
*
|
||||
* SPI transfers always write the same number of bytes as they read.
|
||||
* Protocol drivers should always provide rx_buf and/or tx_buf.
|
||||
|
|
@ -279,11 +280,16 @@ extern struct spi_master *spi_busnum_to_master(u16 busnum);
|
|||
* the data being transferred; that may reduce overhead, when the
|
||||
* underlying driver uses dma.
|
||||
*
|
||||
* All SPI transfers start with the relevant chipselect active. Drivers
|
||||
* can change behavior of the chipselect after the transfer finishes
|
||||
* (including any mandatory delay). The normal behavior is to leave it
|
||||
* selected, except for the last transfer in a message. Setting cs_change
|
||||
* allows two additional behavior options:
|
||||
* If the transmit buffer is null, undefined data will be shifted out
|
||||
* while filling rx_buf. If the receive buffer is null, the data
|
||||
* shifted in will be discarded. Only "len" bytes shift out (or in).
|
||||
* It's an error to try to shift out a partial word. (For example, by
|
||||
* shifting out three bytes with word size of sixteen or twenty bits;
|
||||
* the former uses two bytes per word, the latter uses four bytes.)
|
||||
*
|
||||
* All SPI transfers start with the relevant chipselect active. Normally
|
||||
* it stays selected until after the last transfer in a message. Drivers
|
||||
* can affect the chipselect signal using cs_change:
|
||||
*
|
||||
* (i) If the transfer isn't the last one in the message, this flag is
|
||||
* used to make the chipselect briefly go inactive in the middle of the
|
||||
|
|
@ -299,7 +305,8 @@ extern struct spi_master *spi_busnum_to_master(u16 busnum);
|
|||
* The code that submits an spi_message (and its spi_transfers)
|
||||
* to the lower layers is responsible for managing its memory.
|
||||
* Zero-initialize every field you don't set up explicitly, to
|
||||
* insulate against future API updates.
|
||||
* insulate against future API updates. After you submit a message
|
||||
* and its transfers, ignore them until its completion callback.
|
||||
*/
|
||||
struct spi_transfer {
|
||||
/* it's ok if tx_buf == rx_buf (right?)
|
||||
|
|
@ -316,12 +323,13 @@ struct spi_transfer {
|
|||
|
||||
unsigned cs_change:1;
|
||||
u16 delay_usecs;
|
||||
|
||||
struct list_head transfer_list;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct spi_message - one multi-segment SPI transaction
|
||||
* @transfers: the segements of the transaction
|
||||
* @n_transfer: how many segments
|
||||
* @transfers: list of transfer segments in this transaction
|
||||
* @spi: SPI device to which the transaction is queued
|
||||
* @is_dma_mapped: if true, the caller provided both dma and cpu virtual
|
||||
* addresses for each transfer buffer
|
||||
|
|
@ -333,14 +341,22 @@ struct spi_transfer {
|
|||
* @queue: for use by whichever driver currently owns the message
|
||||
* @state: for use by whichever driver currently owns the message
|
||||
*
|
||||
* An spi_message is used to execute an atomic sequence of data transfers,
|
||||
* each represented by a struct spi_transfer. The sequence is "atomic"
|
||||
* in the sense that no other spi_message may use that SPI bus until that
|
||||
* sequence completes. On some systems, many such sequences can execute as
|
||||
* as single programmed DMA transfer. On all systems, these messages are
|
||||
* queued, and might complete after transactions to other devices. Messages
|
||||
* sent to a given spi_device are alway executed in FIFO order.
|
||||
*
|
||||
* The code that submits an spi_message (and its spi_transfers)
|
||||
* to the lower layers is responsible for managing its memory.
|
||||
* Zero-initialize every field you don't set up explicitly, to
|
||||
* insulate against future API updates.
|
||||
* insulate against future API updates. After you submit a message
|
||||
* and its transfers, ignore them until its completion callback.
|
||||
*/
|
||||
struct spi_message {
|
||||
struct spi_transfer *transfers;
|
||||
unsigned n_transfer;
|
||||
struct list_head transfers;
|
||||
|
||||
struct spi_device *spi;
|
||||
|
||||
|
|
@ -371,6 +387,24 @@ struct spi_message {
|
|||
void *state;
|
||||
};
|
||||
|
||||
static inline void spi_message_init(struct spi_message *m)
|
||||
{
|
||||
memset(m, 0, sizeof *m);
|
||||
INIT_LIST_HEAD(&m->transfers);
|
||||
}
|
||||
|
||||
static inline void
|
||||
spi_message_add_tail(struct spi_transfer *t, struct spi_message *m)
|
||||
{
|
||||
list_add_tail(&t->transfer_list, &m->transfers);
|
||||
}
|
||||
|
||||
static inline void
|
||||
spi_transfer_del(struct spi_transfer *t)
|
||||
{
|
||||
list_del(&t->transfer_list);
|
||||
}
|
||||
|
||||
/* It's fine to embed message and transaction structures in other data
|
||||
* structures so long as you don't free them while they're in use.
|
||||
*/
|
||||
|
|
@ -383,8 +417,12 @@ static inline struct spi_message *spi_message_alloc(unsigned ntrans, gfp_t flags
|
|||
+ ntrans * sizeof(struct spi_transfer),
|
||||
flags);
|
||||
if (m) {
|
||||
m->transfers = (void *)(m + 1);
|
||||
m->n_transfer = ntrans;
|
||||
int i;
|
||||
struct spi_transfer *t = (struct spi_transfer *)(m + 1);
|
||||
|
||||
INIT_LIST_HEAD(&m->transfers);
|
||||
for (i = 0; i < ntrans; i++, t++)
|
||||
spi_message_add_tail(t, m);
|
||||
}
|
||||
return m;
|
||||
}
|
||||
|
|
@ -402,6 +440,8 @@ static inline void spi_message_free(struct spi_message *m)
|
|||
* device doesn't work with the mode 0 default. They may likewise need
|
||||
* to update clock rates or word sizes from initial values. This function
|
||||
* changes those settings, and must be called from a context that can sleep.
|
||||
* The changes take effect the next time the device is selected and data
|
||||
* is transferred to or from it.
|
||||
*/
|
||||
static inline int
|
||||
spi_setup(struct spi_device *spi)
|
||||
|
|
@ -468,15 +508,12 @@ spi_write(struct spi_device *spi, const u8 *buf, size_t len)
|
|||
{
|
||||
struct spi_transfer t = {
|
||||
.tx_buf = buf,
|
||||
.rx_buf = NULL,
|
||||
.len = len,
|
||||
.cs_change = 0,
|
||||
};
|
||||
struct spi_message m = {
|
||||
.transfers = &t,
|
||||
.n_transfer = 1,
|
||||
};
|
||||
struct spi_message m;
|
||||
|
||||
spi_message_init(&m);
|
||||
spi_message_add_tail(&t, &m);
|
||||
return spi_sync(spi, &m);
|
||||
}
|
||||
|
||||
|
|
@ -493,16 +530,13 @@ static inline int
|
|||
spi_read(struct spi_device *spi, u8 *buf, size_t len)
|
||||
{
|
||||
struct spi_transfer t = {
|
||||
.tx_buf = NULL,
|
||||
.rx_buf = buf,
|
||||
.len = len,
|
||||
.cs_change = 0,
|
||||
};
|
||||
struct spi_message m = {
|
||||
.transfers = &t,
|
||||
.n_transfer = 1,
|
||||
};
|
||||
struct spi_message m;
|
||||
|
||||
spi_message_init(&m);
|
||||
spi_message_add_tail(&t, &m);
|
||||
return spi_sync(spi, &m);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -31,8 +31,15 @@ struct spi_bitbang {
|
|||
struct spi_master *master;
|
||||
|
||||
void (*chipselect)(struct spi_device *spi, int is_on);
|
||||
#define BITBANG_CS_ACTIVE 1 /* normally nCS, active low */
|
||||
#define BITBANG_CS_INACTIVE 0
|
||||
|
||||
/* txrx_bufs() may handle dma mapping for transfers that don't
|
||||
* already have one (transfer.{tx,rx}_dma is zero), or use PIO
|
||||
*/
|
||||
int (*txrx_bufs)(struct spi_device *spi, struct spi_transfer *t);
|
||||
|
||||
/* txrx_word[SPI_MODE_*]() just looks like a shift register */
|
||||
u32 (*txrx_word[4])(struct spi_device *spi,
|
||||
unsigned nsecs,
|
||||
u32 word, u8 bits);
|
||||
|
|
|
|||
Loading…
Reference in a new issue