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drm: rcar-du: lvds: Adjust operating frequency for D3 and E3

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The D3 and E3 SoCs have different pixel clock frequency limits for the
LVDS encoder than the other SoCs in the Gen3 family. Adjust the mode
fixup implementation accordingly.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Reviewed-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
This commit is contained in:
Laurent Pinchart 2019-03-03 22:29:21 +02:00
parent b764f2f66e
commit 8713703086
1 changed files with 7 additions and 2 deletions
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9
drivers/gpu/drm/rcar-du/rcar_lvds.c
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@ -531,11 +531,16 @@ static bool rcar_lvds_mode_fixup(struct drm_bridge *bridge,
const struct drm_display_mode *mode,
struct drm_display_mode *adjusted_mode)
{
struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
int min_freq;
/*
* The internal LVDS encoder has a restricted clock frequency operating
* range (31MHz to 148.5MHz). Clamp the clock accordingly.
* range, from 5MHz to 148.5MHz on D3 and E3, and from 31MHz to
* 148.5MHz on all other platforms. Clamp the clock accordingly.
*/
adjusted_mode->clock = clamp(adjusted_mode->clock, 31000, 148500);
min_freq = lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL ? 5000 : 31000;
adjusted_mode->clock = clamp(adjusted_mode->clock, min_freq, 148500);
return true;
}