clk: mdm9615: Add EBI2 clock
Add definition of EBI2 clock used by MDM9615 NAND controller. Cc: Andy Gross <andy.gross@linaro.org> Cc: David Brown <david.brown@linaro.org> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: linux-arm-msm@vger.kernel.org Cc: linux-soc@vger.kernel.org Cc: linux-clk@vger.kernel.org Cc: devicetree@vger.kernel.org Signed-off-by: Zoran Markovic <zmarkovic@sierrawireless.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com> [sboyd@codeaurora.org: ebi2_clk halt bit is 24 not 23] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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@ -1563,6 +1563,34 @@ static struct clk_branch rpm_msg_ram_h_clk = {
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},
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};
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static struct clk_branch ebi2_clk = {
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.hwcg_reg = 0x2664,
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.hwcg_bit = 6,
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.halt_reg = 0x2fcc,
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.halt_bit = 24,
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.clkr = {
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.enable_reg = 0x2664,
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.enable_mask = BIT(6) | BIT(4),
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.hw.init = &(struct clk_init_data){
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.name = "ebi2_clk",
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.ops = &clk_branch_ops,
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},
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},
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};
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static struct clk_branch ebi2_aon_clk = {
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.halt_reg = 0x2fcc,
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.halt_bit = 23,
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.clkr = {
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.enable_reg = 0x2664,
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.enable_mask = BIT(8),
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.hw.init = &(struct clk_init_data){
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.name = "ebi2_aon_clk",
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.ops = &clk_branch_ops,
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},
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},
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};
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static struct clk_hw *gcc_mdm9615_hws[] = {
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&cxo.hw,
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};
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@ -1637,6 +1665,8 @@ static struct clk_regmap *gcc_mdm9615_clks[] = {
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[PMIC_ARB1_H_CLK] = &pmic_arb1_h_clk.clkr,
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[PMIC_SSBI2_CLK] = &pmic_ssbi2_clk.clkr,
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[RPM_MSG_RAM_H_CLK] = &rpm_msg_ram_h_clk.clkr,
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[EBI2_CLK] = &ebi2_clk.clkr,
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[EBI2_AON_CLK] = &ebi2_aon_clk.clkr,
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};
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static const struct qcom_reset_map gcc_mdm9615_resets[] = {
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@ -323,5 +323,7 @@
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#define CE3_H_CLK 305
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#define USB_HS1_SYSTEM_CLK_SRC 306
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#define USB_HS1_SYSTEM_CLK 307
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#define EBI2_CLK 308
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#define EBI2_AON_CLK 309
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#endif
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