rt2800: 5592: channel config stub
Based on: RT5592_ChipSwitchChannel() from: DPO_RT5572_LinuxSTA_2.6.1.3_20121022/chips/rt5592.c Signed-off-by: Stanislaw Gruszka <stf_xl@wp.pl> Tested-by: Wanlong Gao <gaowanlong@cn.fujitsu.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Stanislaw Gruszka
John W. Linville
parent
7848b23131
commit
8f821098ce
2 changed files with 266 additions and 0 deletions
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@ -2029,10 +2029,19 @@ struct mac_iveiv_entry {
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#define RFCSR7_BIT5 FIELD8(0x20)
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#define RFCSR7_BITS67 FIELD8(0xc0)
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/*
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* RFCSR 9:
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*/
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#define RFCSR9_K FIELD8(0x0f)
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#define RFCSR9_N FIELD8(0x10)
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#define RFCSR9_UNKNOWN FIELD8(0x60)
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#define RFCSR9_MOD FIELD8(0x80)
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/*
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* RFCSR 11:
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*/
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#define RFCSR11_R FIELD8(0x03)
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#define RFCSR11_MOD FIELD8(0xc0)
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/*
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* RFCSR 12:
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@ -2138,11 +2147,13 @@ struct mac_iveiv_entry {
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* RFCSR 49:
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*/
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#define RFCSR49_TX FIELD8(0x3f)
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#define RFCSR49_EP FIELD8(0xc0)
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/*
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* RFCSR 50:
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*/
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#define RFCSR50_TX FIELD8(0x3f)
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#define RFCSR50_EP FIELD8(0xc0)
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/*
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* RF registers
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@ -1988,6 +1988,7 @@ static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev,
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}
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#define POWER_BOUND 0x27
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#define POWER_BOUND_5G 0x2b
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#define FREQ_OFFSET_BOUND 0x5f
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static void rt2800_config_channel_rf3290(struct rt2x00_dev *rt2x00dev,
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@ -2184,6 +2185,257 @@ static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev,
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}
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}
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static void rt2800_config_channel_rf55xx(struct rt2x00_dev *rt2x00dev,
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struct ieee80211_conf *conf,
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struct rf_channel *rf,
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struct channel_info *info)
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{
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u8 rfcsr, ep_reg;
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int power_bound;
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/* TODO */
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const bool is_11b = false;
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const bool is_type_ep = false;
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/* Order of values on rf_channel entry: N, K, mod, R */
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rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1 & 0xff);
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rt2800_rfcsr_read(rt2x00dev, 9, &rfcsr);
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rt2x00_set_field8(&rfcsr, RFCSR9_K, rf->rf2 & 0xf);
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rt2x00_set_field8(&rfcsr, RFCSR9_N, (rf->rf1 & 0x100) >> 8);
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rt2x00_set_field8(&rfcsr, RFCSR9_MOD, ((rf->rf3 - 8) & 0x4) >> 2);
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rt2800_rfcsr_write(rt2x00dev, 9, rfcsr);
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rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
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rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf4 - 1);
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rt2x00_set_field8(&rfcsr, RFCSR11_MOD, (rf->rf3 - 8) & 0x3);
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rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
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if (rf->channel <= 14) {
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rt2800_rfcsr_write(rt2x00dev, 10, 0x90);
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/* FIXME: RF11 owerwrite ? */
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rt2800_rfcsr_write(rt2x00dev, 11, 0x4A);
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rt2800_rfcsr_write(rt2x00dev, 12, 0x52);
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rt2800_rfcsr_write(rt2x00dev, 13, 0x42);
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rt2800_rfcsr_write(rt2x00dev, 22, 0x40);
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rt2800_rfcsr_write(rt2x00dev, 24, 0x4A);
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rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
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rt2800_rfcsr_write(rt2x00dev, 27, 0x42);
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rt2800_rfcsr_write(rt2x00dev, 36, 0x80);
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rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
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rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
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rt2800_rfcsr_write(rt2x00dev, 39, 0x1B);
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rt2800_rfcsr_write(rt2x00dev, 40, 0x0D);
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rt2800_rfcsr_write(rt2x00dev, 41, 0x9B);
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rt2800_rfcsr_write(rt2x00dev, 42, 0xD5);
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rt2800_rfcsr_write(rt2x00dev, 43, 0x72);
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rt2800_rfcsr_write(rt2x00dev, 44, 0x0E);
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rt2800_rfcsr_write(rt2x00dev, 45, 0xA2);
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rt2800_rfcsr_write(rt2x00dev, 46, 0x6B);
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rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
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rt2800_rfcsr_write(rt2x00dev, 51, 0x3E);
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rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
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rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
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rt2800_rfcsr_write(rt2x00dev, 56, 0xA1);
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rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
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rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
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rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
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rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
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rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
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/* TODO RF27 <- tssi */
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rfcsr = rf->channel <= 10 ? 0x07 : 0x06;
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rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
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rt2800_rfcsr_write(rt2x00dev, 59, rfcsr);
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if (is_11b) {
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/* CCK */
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rt2800_rfcsr_write(rt2x00dev, 31, 0xF8);
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rt2800_rfcsr_write(rt2x00dev, 32, 0xC0);
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if (is_type_ep)
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rt2800_rfcsr_write(rt2x00dev, 55, 0x06);
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else
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rt2800_rfcsr_write(rt2x00dev, 55, 0x47);
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} else {
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/* OFDM */
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if (is_type_ep)
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rt2800_rfcsr_write(rt2x00dev, 55, 0x03);
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else
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rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
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}
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power_bound = POWER_BOUND;
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ep_reg = 0x2;
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} else {
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rt2800_rfcsr_write(rt2x00dev, 10, 0x97);
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/* FIMXE: RF11 overwrite */
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rt2800_rfcsr_write(rt2x00dev, 11, 0x40);
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rt2800_rfcsr_write(rt2x00dev, 25, 0xBF);
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rt2800_rfcsr_write(rt2x00dev, 27, 0x42);
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rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
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rt2800_rfcsr_write(rt2x00dev, 37, 0x04);
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rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
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rt2800_rfcsr_write(rt2x00dev, 40, 0x42);
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rt2800_rfcsr_write(rt2x00dev, 41, 0xBB);
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rt2800_rfcsr_write(rt2x00dev, 42, 0xD7);
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rt2800_rfcsr_write(rt2x00dev, 45, 0x41);
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rt2800_rfcsr_write(rt2x00dev, 48, 0x00);
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rt2800_rfcsr_write(rt2x00dev, 57, 0x77);
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rt2800_rfcsr_write(rt2x00dev, 60, 0x05);
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rt2800_rfcsr_write(rt2x00dev, 61, 0x01);
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/* TODO RF27 <- tssi */
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if (rf->channel >= 36 && rf->channel <= 64) {
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rt2800_rfcsr_write(rt2x00dev, 12, 0x2E);
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rt2800_rfcsr_write(rt2x00dev, 13, 0x22);
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rt2800_rfcsr_write(rt2x00dev, 22, 0x60);
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rt2800_rfcsr_write(rt2x00dev, 23, 0x7F);
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if (rf->channel <= 50)
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rt2800_rfcsr_write(rt2x00dev, 24, 0x09);
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else if (rf->channel >= 52)
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rt2800_rfcsr_write(rt2x00dev, 24, 0x07);
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rt2800_rfcsr_write(rt2x00dev, 39, 0x1C);
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rt2800_rfcsr_write(rt2x00dev, 43, 0x5B);
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rt2800_rfcsr_write(rt2x00dev, 44, 0X40);
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rt2800_rfcsr_write(rt2x00dev, 46, 0X00);
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rt2800_rfcsr_write(rt2x00dev, 51, 0xFE);
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rt2800_rfcsr_write(rt2x00dev, 52, 0x0C);
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rt2800_rfcsr_write(rt2x00dev, 54, 0xF8);
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if (rf->channel <= 50) {
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rt2800_rfcsr_write(rt2x00dev, 55, 0x06),
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rt2800_rfcsr_write(rt2x00dev, 56, 0xD3);
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} else if (rf->channel >= 52) {
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rt2800_rfcsr_write(rt2x00dev, 55, 0x04);
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rt2800_rfcsr_write(rt2x00dev, 56, 0xBB);
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}
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rt2800_rfcsr_write(rt2x00dev, 58, 0x15);
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rt2800_rfcsr_write(rt2x00dev, 59, 0x7F);
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rt2800_rfcsr_write(rt2x00dev, 62, 0x15);
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} else if (rf->channel >= 100 && rf->channel <= 165) {
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rt2800_rfcsr_write(rt2x00dev, 12, 0x0E);
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rt2800_rfcsr_write(rt2x00dev, 13, 0x42);
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rt2800_rfcsr_write(rt2x00dev, 22, 0x40);
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if (rf->channel <= 153) {
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rt2800_rfcsr_write(rt2x00dev, 23, 0x3C);
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rt2800_rfcsr_write(rt2x00dev, 24, 0x06);
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} else if (rf->channel >= 155) {
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rt2800_rfcsr_write(rt2x00dev, 23, 0x38);
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rt2800_rfcsr_write(rt2x00dev, 24, 0x05);
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}
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if (rf->channel <= 138) {
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rt2800_rfcsr_write(rt2x00dev, 39, 0x1A);
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rt2800_rfcsr_write(rt2x00dev, 43, 0x3B);
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rt2800_rfcsr_write(rt2x00dev, 44, 0x20);
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rt2800_rfcsr_write(rt2x00dev, 46, 0x18);
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} else if (rf->channel >= 140) {
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rt2800_rfcsr_write(rt2x00dev, 39, 0x18);
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rt2800_rfcsr_write(rt2x00dev, 43, 0x1B);
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rt2800_rfcsr_write(rt2x00dev, 44, 0x10);
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rt2800_rfcsr_write(rt2x00dev, 46, 0X08);
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}
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if (rf->channel <= 124)
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rt2800_rfcsr_write(rt2x00dev, 51, 0xFC);
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else if (rf->channel >= 126)
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rt2800_rfcsr_write(rt2x00dev, 51, 0xEC);
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if (rf->channel <= 138)
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rt2800_rfcsr_write(rt2x00dev, 52, 0x06);
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else if (rf->channel >= 140)
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rt2800_rfcsr_write(rt2x00dev, 52, 0x06);
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rt2800_rfcsr_write(rt2x00dev, 54, 0xEB);
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if (rf->channel <= 138)
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rt2800_rfcsr_write(rt2x00dev, 55, 0x01);
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else if (rf->channel >= 140)
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rt2800_rfcsr_write(rt2x00dev, 55, 0x00);
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if (rf->channel <= 128)
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rt2800_rfcsr_write(rt2x00dev, 56, 0xBB);
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else if (rf->channel >= 130)
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rt2800_rfcsr_write(rt2x00dev, 56, 0xAB);
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if (rf->channel <= 116)
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rt2800_rfcsr_write(rt2x00dev, 58, 0x1D);
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else if (rf->channel >= 118)
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rt2800_rfcsr_write(rt2x00dev, 58, 0x15);
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if (rf->channel <= 138)
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rt2800_rfcsr_write(rt2x00dev, 59, 0x3F);
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else if (rf->channel >= 140)
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rt2800_rfcsr_write(rt2x00dev, 59, 0x7C);
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if (rf->channel <= 116)
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rt2800_rfcsr_write(rt2x00dev, 62, 0x1D);
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else if (rf->channel >= 118)
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rt2800_rfcsr_write(rt2x00dev, 62, 0x15);
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}
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power_bound = POWER_BOUND_5G;
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ep_reg = 0x3;
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}
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rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
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if (info->default_power1 > power_bound)
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rt2x00_set_field8(&rfcsr, RFCSR49_TX, power_bound);
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else
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rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
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if (is_type_ep)
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rt2x00_set_field8(&rfcsr, RFCSR49_EP, ep_reg);
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rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
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rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
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if (info->default_power1 > power_bound)
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rt2x00_set_field8(&rfcsr, RFCSR50_TX, power_bound);
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else
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rt2x00_set_field8(&rfcsr, RFCSR50_TX, info->default_power2);
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if (is_type_ep)
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rt2x00_set_field8(&rfcsr, RFCSR50_EP, ep_reg);
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rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
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rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
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rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
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rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
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rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD,
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rt2x00dev->default_ant.tx_chain_num >= 1);
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rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
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rt2x00dev->default_ant.tx_chain_num == 2);
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rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
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rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD,
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rt2x00dev->default_ant.rx_chain_num >= 1);
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rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
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rt2x00dev->default_ant.rx_chain_num == 2);
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rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
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rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
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rt2800_rfcsr_write(rt2x00dev, 6, 0xe4);
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if (conf_is_ht40(conf))
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rt2800_rfcsr_write(rt2x00dev, 30, 0x16);
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else
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rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
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if (!is_11b) {
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rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
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rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
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}
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/* TODO proper frequency adjustment */
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rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
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if (rt2x00dev->freq_offset > FREQ_OFFSET_BOUND)
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rt2x00_set_field8(&rfcsr, RFCSR17_CODE, FREQ_OFFSET_BOUND);
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else
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rt2x00_set_field8(&rfcsr, RFCSR17_CODE, rt2x00dev->freq_offset);
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rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
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/* TODO merge with others */
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rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
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rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
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rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
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}
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static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
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struct ieee80211_conf *conf,
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struct rf_channel *rf,
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@ -2225,6 +2477,9 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
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case RF5392:
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rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info);
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break;
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case RF5592:
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rt2800_config_channel_rf55xx(rt2x00dev, conf, rf, info);
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break;
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default:
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rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
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}
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