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drm/radeon/dpm: pull in phase shedding limits from atom

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Required for dpm on SI.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Deucher 2013-03-20 12:30:25 -04:00
parent 32ce4652dc
commit 929ee7a8b3
2 changed files with 41 additions and 1 deletions
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30
drivers/gpu/drm/radeon/r600_dpm.c
View file

@ -806,7 +806,7 @@ int r600_parse_extended_power_table(struct radeon_device *rdev)
} }
} }
/* clock dependancy tables */ /* clock dependancy tables, shedding tables */
if (power_info->pplib.usTableSize >= sizeof(struct _ATOM_PPLIB_POWERPLAYTABLE4)) { if (power_info->pplib.usTableSize >= sizeof(struct _ATOM_PPLIB_POWERPLAYTABLE4)) {
if (power_info->pplib4.usVddcDependencyOnSCLKOffset) { if (power_info->pplib4.usVddcDependencyOnSCLKOffset) {
dep_table = (ATOM_PPLIB_Clock_Voltage_Dependency_Table *) dep_table = (ATOM_PPLIB_Clock_Voltage_Dependency_Table *)
@ -858,6 +858,32 @@ int r600_parse_extended_power_table(struct radeon_device *rdev)
le16_to_cpu(clk_v->entries[0].usVddci); le16_to_cpu(clk_v->entries[0].usVddci);
} }
} }
if (power_info->pplib4.usVddcPhaseShedLimitsTableOffset) {
ATOM_PPLIB_PhaseSheddingLimits_Table *psl =
(ATOM_PPLIB_PhaseSheddingLimits_Table *)
(mode_info->atom_context->bios + data_offset +
le16_to_cpu(power_info->pplib4.usVddcPhaseShedLimitsTableOffset));
rdev->pm.dpm.dyn_state.phase_shedding_limits_table.entries =
kzalloc(psl->ucNumEntries *
sizeof(struct radeon_phase_shedding_limits_entry),
GFP_KERNEL);
if (!rdev->pm.dpm.dyn_state.phase_shedding_limits_table.entries)
return -ENOMEM;
for (i = 0; i < psl->ucNumEntries; i++) {
rdev->pm.dpm.dyn_state.phase_shedding_limits_table.entries[i].sclk =
le16_to_cpu(psl->entries[i].usSclkLow) |
(psl->entries[i].ucSclkHigh << 16);
rdev->pm.dpm.dyn_state.phase_shedding_limits_table.entries[i].mclk =
le16_to_cpu(psl->entries[i].usMclkLow) |
(psl->entries[i].ucMclkHigh << 16);
rdev->pm.dpm.dyn_state.phase_shedding_limits_table.entries[i].voltage =
le16_to_cpu(psl->entries[i].usVoltage);
}
rdev->pm.dpm.dyn_state.phase_shedding_limits_table.count =
psl->ucNumEntries;
}
} }
/* cac data */ /* cac data */
@ -909,4 +935,6 @@ void r600_free_extended_power_table(struct radeon_device *rdev)
kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries); kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries);
if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries)
kfree(rdev->pm.dpm.dyn_state.cac_leakage_table.entries); kfree(rdev->pm.dpm.dyn_state.cac_leakage_table.entries);
if (rdev->pm.dpm.dyn_state.phase_shedding_limits_table.entries)
kfree(rdev->pm.dpm.dyn_state.phase_shedding_limits_table.entries);
} }

12
drivers/gpu/drm/radeon/radeon.h
View file

@ -1270,6 +1270,17 @@ struct radeon_cac_leakage_table {
struct radeon_cac_leakage_entry *entries; struct radeon_cac_leakage_entry *entries;
}; };
struct radeon_phase_shedding_limits_entry {
u16 voltage;
u32 sclk;
u32 mclk;
};
struct radeon_phase_shedding_limits_table {
u32 count;
struct radeon_phase_shedding_limits_entry *entries;
};
struct radeon_dpm_dynamic_state { struct radeon_dpm_dynamic_state {
struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk; struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk;
struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk; struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk;
@ -1283,6 +1294,7 @@ struct radeon_dpm_dynamic_state {
u16 vddc_vddci_delta; u16 vddc_vddci_delta;
u16 min_vddc_for_pcie_gen2; u16 min_vddc_for_pcie_gen2;
struct radeon_cac_leakage_table cac_leakage_table; struct radeon_cac_leakage_table cac_leakage_table;
struct radeon_phase_shedding_limits_table phase_shedding_limits_table;
}; };
struct radeon_dpm_fan { struct radeon_dpm_fan {