iommu/vt-d: Add per-device IOMMU feature ops entries
This adds the iommu ops entries for aux-domain per-device feature query and enable/disable. Cc: Ashok Raj <ashok.raj@intel.com> Cc: Jacob Pan <jacob.jun.pan@linux.intel.com> Cc: Kevin Tian <kevin.tian@intel.com> Signed-off-by: Sanjay Kumar <sanjay.k.kumar@intel.com> Signed-off-by: Liu Yi L <yi.l.liu@intel.com> Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
This commit is contained in:
Lu Baolu
Joerg Roedel
parent
d7cbc0f322
commit
95587a75de
2 changed files with 160 additions and 0 deletions
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@ -2485,6 +2485,7 @@ static struct dmar_domain *dmar_insert_one_dev_info(struct intel_iommu *iommu,
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info->domain = domain;
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info->iommu = iommu;
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info->pasid_table = NULL;
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info->auxd_enabled = 0;
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if (dev && dev_is_pci(dev)) {
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struct pci_dev *pdev = to_pci_dev(info->dev);
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@ -5223,6 +5224,42 @@ static phys_addr_t intel_iommu_iova_to_phys(struct iommu_domain *domain,
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return phys;
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}
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static inline bool scalable_mode_support(void)
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{
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struct dmar_drhd_unit *drhd;
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struct intel_iommu *iommu;
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bool ret = true;
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rcu_read_lock();
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for_each_active_iommu(iommu, drhd) {
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if (!sm_supported(iommu)) {
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ret = false;
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break;
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}
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}
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rcu_read_unlock();
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return ret;
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}
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static inline bool iommu_pasid_support(void)
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{
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struct dmar_drhd_unit *drhd;
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struct intel_iommu *iommu;
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bool ret = true;
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rcu_read_lock();
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for_each_active_iommu(iommu, drhd) {
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if (!pasid_supported(iommu)) {
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ret = false;
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break;
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}
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}
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rcu_read_unlock();
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return ret;
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}
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static bool intel_iommu_capable(enum iommu_cap cap)
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{
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if (cap == IOMMU_CAP_CACHE_COHERENCY)
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@ -5380,6 +5417,124 @@ struct intel_iommu *intel_svm_device_to_iommu(struct device *dev)
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}
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#endif /* CONFIG_INTEL_IOMMU_SVM */
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static int intel_iommu_enable_auxd(struct device *dev)
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{
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struct device_domain_info *info;
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struct intel_iommu *iommu;
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unsigned long flags;
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u8 bus, devfn;
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int ret;
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iommu = device_to_iommu(dev, &bus, &devfn);
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if (!iommu || dmar_disabled)
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return -EINVAL;
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if (!sm_supported(iommu) || !pasid_supported(iommu))
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return -EINVAL;
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ret = intel_iommu_enable_pasid(iommu, dev);
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if (ret)
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return -ENODEV;
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spin_lock_irqsave(&device_domain_lock, flags);
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info = dev->archdata.iommu;
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info->auxd_enabled = 1;
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spin_unlock_irqrestore(&device_domain_lock, flags);
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return 0;
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}
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static int intel_iommu_disable_auxd(struct device *dev)
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{
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struct device_domain_info *info;
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unsigned long flags;
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spin_lock_irqsave(&device_domain_lock, flags);
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info = dev->archdata.iommu;
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if (!WARN_ON(!info))
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info->auxd_enabled = 0;
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spin_unlock_irqrestore(&device_domain_lock, flags);
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return 0;
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}
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/*
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* A PCI express designated vendor specific extended capability is defined
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* in the section 3.7 of Intel scalable I/O virtualization technical spec
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* for system software and tools to detect endpoint devices supporting the
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* Intel scalable IO virtualization without host driver dependency.
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*
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* Returns the address of the matching extended capability structure within
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* the device's PCI configuration space or 0 if the device does not support
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* it.
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*/
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static int siov_find_pci_dvsec(struct pci_dev *pdev)
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{
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int pos;
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u16 vendor, id;
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pos = pci_find_next_ext_capability(pdev, 0, 0x23);
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while (pos) {
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pci_read_config_word(pdev, pos + 4, &vendor);
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pci_read_config_word(pdev, pos + 8, &id);
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if (vendor == PCI_VENDOR_ID_INTEL && id == 5)
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return pos;
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pos = pci_find_next_ext_capability(pdev, pos, 0x23);
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}
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return 0;
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}
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static bool
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intel_iommu_dev_has_feat(struct device *dev, enum iommu_dev_features feat)
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{
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if (feat == IOMMU_DEV_FEAT_AUX) {
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int ret;
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if (!dev_is_pci(dev) || dmar_disabled ||
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!scalable_mode_support() || !iommu_pasid_support())
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return false;
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ret = pci_pasid_features(to_pci_dev(dev));
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if (ret < 0)
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return false;
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return !!siov_find_pci_dvsec(to_pci_dev(dev));
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}
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return false;
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}
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static int
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intel_iommu_dev_enable_feat(struct device *dev, enum iommu_dev_features feat)
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{
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if (feat == IOMMU_DEV_FEAT_AUX)
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return intel_iommu_enable_auxd(dev);
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return -ENODEV;
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}
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static int
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intel_iommu_dev_disable_feat(struct device *dev, enum iommu_dev_features feat)
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{
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if (feat == IOMMU_DEV_FEAT_AUX)
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return intel_iommu_disable_auxd(dev);
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return -ENODEV;
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}
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static bool
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intel_iommu_dev_feat_enabled(struct device *dev, enum iommu_dev_features feat)
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{
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struct device_domain_info *info = dev->archdata.iommu;
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if (feat == IOMMU_DEV_FEAT_AUX)
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return scalable_mode_support() && info && info->auxd_enabled;
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return false;
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}
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const struct iommu_ops intel_iommu_ops = {
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.capable = intel_iommu_capable,
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.domain_alloc = intel_iommu_domain_alloc,
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@ -5394,6 +5549,10 @@ const struct iommu_ops intel_iommu_ops = {
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.get_resv_regions = intel_iommu_get_resv_regions,
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.put_resv_regions = intel_iommu_put_resv_regions,
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.device_group = pci_device_group,
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.dev_has_feat = intel_iommu_dev_has_feat,
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.dev_feat_enabled = intel_iommu_dev_feat_enabled,
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.dev_enable_feat = intel_iommu_dev_enable_feat,
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.dev_disable_feat = intel_iommu_dev_disable_feat,
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.pgsize_bitmap = INTEL_IOMMU_PGSIZES,
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};
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@ -568,6 +568,7 @@ struct device_domain_info {
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u8 pri_enabled:1;
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u8 ats_supported:1;
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u8 ats_enabled:1;
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u8 auxd_enabled:1; /* Multiple domains per device */
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u8 ats_qdep;
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struct device *dev; /* it's NULL for PCIe-to-PCI bridge */
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struct intel_iommu *iommu; /* IOMMU used by this device */
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