amd64_edac: Add support for interleaved region swapping
On revC3 and revE Fam10h machines and later, non-interleaved graphics framebuffer memory under the 16G mark can be swapped with a region located at the bottom of memory so that the GPU can use the interleaved region and thus two channels. Add support for that. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
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2 changed files with 40 additions and 0 deletions
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@ -1331,6 +1331,42 @@ static int f10_lookup_addr_in_dct(u64 in_addr, u32 nid, u8 dct)
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return cs_found;
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}
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/*
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* See F2x10C. Non-interleaved graphics framebuffer memory under the 16G is
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* swapped with a region located at the bottom of memory so that the GPU can use
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* the interleaved region and thus two channels.
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*/
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static u64 f10_swap_interleaved_region(struct amd64_pvt *pvt, u64 sys_addr)
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{
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u32 swap_reg, swap_base, swap_limit, rgn_size, tmp_addr;
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if (boot_cpu_data.x86 == 0x10) {
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/* only revC3 and revE have that feature */
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if (boot_cpu_data.x86_model < 4 ||
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(boot_cpu_data.x86_model < 0xa &&
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boot_cpu_data.x86_mask < 3))
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return sys_addr;
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}
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amd64_read_dct_pci_cfg(pvt, SWAP_INTLV_REG, &swap_reg);
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if (!(swap_reg & 0x1))
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return sys_addr;
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swap_base = (swap_reg >> 3) & 0x7f;
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swap_limit = (swap_reg >> 11) & 0x7f;
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rgn_size = (swap_reg >> 20) & 0x7f;
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tmp_addr = sys_addr >> 27;
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if (!(sys_addr >> 34) &&
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(((tmp_addr >= swap_base) &&
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(tmp_addr <= swap_limit)) ||
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(tmp_addr < rgn_size)))
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return sys_addr ^ (u64)swap_base << 27;
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return sys_addr;
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}
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/* For a given @dram_range, check if @sys_addr falls within it. */
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static int f10_match_to_this_node(struct amd64_pvt *pvt, int range,
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u64 sys_addr, int *nid, int *chan_sel)
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@ -1352,6 +1388,8 @@ static int f10_match_to_this_node(struct amd64_pvt *pvt, int range,
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(intlv_sel != ((sys_addr >> 12) & intlv_en)))
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return -EINVAL;
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sys_addr = f10_swap_interleaved_region(pvt, sys_addr);
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dct_sel_base = dct_sel_baseaddr(pvt);
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/*
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@ -239,6 +239,8 @@
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#define dct_dram_enabled(pvt) ((pvt)->dct_sel_lo & BIT(8))
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#define dct_memory_cleared(pvt) ((pvt)->dct_sel_lo & BIT(10))
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#define SWAP_INTLV_REG 0x10c
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#define DCT_SEL_HI 0x114
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/*
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