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ARM: mvebu: prefix coprocessor operand with p

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In every other instance where mrc is used the coprocessor operand
is prefix with p (e.g. p15). Use the p prefix in this case too.
This fixes a build issue when using LLVM's integrated assembler:
  arch/arm/mach-mvebu/coherency_ll.S:69:6: error: invalid operand for instruction
   mrc 15, 0, r3, cr0, cr0, 5
       ^
  arch/arm/mach-mvebu/pmsu_ll.S:19:6: error: invalid operand for instruction
   mrc 15, 0, r0, cr0, cr0, 5 @ get the CPU ID
       ^

Signed-off-by: Stefan Agner <stefan@agner.ch>
Acked-by: Nicolas Pitre <nico@fluxnic.net>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
This commit is contained in:
Stefan Agner 2019-04-11 09:54:03 +02:00 committed by Gregory CLEMENT
parent 3ab2b5fdd1
commit 969ad77c14
2 changed files with 2 additions and 2 deletions
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2
arch/arm/mach-mvebu/coherency_ll.S
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@ -66,7 +66,7 @@ ENDPROC(ll_get_coherency_base)
* fabric registers * fabric registers
*/ */
ENTRY(ll_get_coherency_cpumask) ENTRY(ll_get_coherency_cpumask)
mrc 15, 0, r3, cr0, cr0, 5 mrc p15, 0, r3, cr0, cr0, 5
and r3, r3, #15 and r3, r3, #15
mov r2, #(1 << 24) mov r2, #(1 << 24)
lsl r3, r2, r3 lsl r3, r2, r3

2
arch/arm/mach-mvebu/pmsu_ll.S
View file

@ -16,7 +16,7 @@
ENTRY(armada_38x_scu_power_up) ENTRY(armada_38x_scu_power_up)
mrc p15, 4, r1, c15, c0 @ get SCU base address mrc p15, 4, r1, c15, c0 @ get SCU base address
orr r1, r1, #0x8 @ SCU CPU Power Status Register orr r1, r1, #0x8 @ SCU CPU Power Status Register
mrc 15, 0, r0, cr0, cr0, 5 @ get the CPU ID mrc p15, 0, r0, cr0, cr0, 5 @ get the CPU ID
and r0, r0, #15 and r0, r0, #15
add r1, r1, r0 add r1, r1, r0
mov r0, #0x0 mov r0, #0x0