Merge branch 'net-mediatek-Add-MT7621-TRGMII-mode-support'
René van Dorst says: ==================== net: mediatek: Add MT7621 TRGMII mode support Like many other mediatek SOCs, the MT7621 SOC and the internal MT7530 switch both supports TRGMII mode. MT7621 TRGMII speed is fix 1200MBit. v1->v2: - Fix breakage on non MT7621 SOC - Support 25MHz and 40MHz XTAL as MT7530 clocksource ==================== Tested-by: "Frank Wunderlich" <frank-w@public-files.de> Acked-by: Sean Wang <sean.wang@kernel.org> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
commit
969b15b002
4 changed files with 86 additions and 15 deletions
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@ -428,24 +428,48 @@ static int
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mt7530_pad_clk_setup(struct dsa_switch *ds, int mode)
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{
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struct mt7530_priv *priv = ds->priv;
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u32 ncpo1, ssc_delta, trgint, i;
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u32 ncpo1, ssc_delta, trgint, i, xtal;
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xtal = mt7530_read(priv, MT7530_MHWTRAP) & HWTRAP_XTAL_MASK;
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if (xtal == HWTRAP_XTAL_20MHZ) {
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dev_err(priv->dev,
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"%s: MT7530 with a 20MHz XTAL is not supported!\n",
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__func__);
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return -EINVAL;
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}
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switch (mode) {
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case PHY_INTERFACE_MODE_RGMII:
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trgint = 0;
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/* PLL frequency: 125MHz */
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ncpo1 = 0x0c80;
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ssc_delta = 0x87;
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break;
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case PHY_INTERFACE_MODE_TRGMII:
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trgint = 1;
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ncpo1 = 0x1400;
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ssc_delta = 0x57;
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if (priv->id == ID_MT7621) {
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/* PLL frequency: 150MHz: 1.2GBit */
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if (xtal == HWTRAP_XTAL_40MHZ)
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ncpo1 = 0x0780;
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if (xtal == HWTRAP_XTAL_25MHZ)
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ncpo1 = 0x0a00;
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} else { /* PLL frequency: 250MHz: 2.0Gbit */
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if (xtal == HWTRAP_XTAL_40MHZ)
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ncpo1 = 0x0c80;
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if (xtal == HWTRAP_XTAL_25MHZ)
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ncpo1 = 0x1400;
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}
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break;
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default:
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dev_err(priv->dev, "xMII mode %d not supported\n", mode);
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return -EINVAL;
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}
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if (xtal == HWTRAP_XTAL_25MHZ)
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ssc_delta = 0x57;
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else
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ssc_delta = 0x87;
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mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK,
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P6_INTF_MODE(trgint));
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@ -507,7 +531,9 @@ mt7530_pad_clk_setup(struct dsa_switch *ds, int mode)
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mt7530_rmw(priv, MT7530_TRGMII_RD(i),
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RD_TAP_MASK, RD_TAP(16));
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else
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mt7623_trgmii_set(priv, GSW_INTF_MODE, INTF_MODE_TRGMII);
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if (priv->id != ID_MT7621)
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mt7623_trgmii_set(priv, GSW_INTF_MODE,
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INTF_MODE_TRGMII);
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return 0;
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}
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@ -613,13 +639,13 @@ static void mt7530_adjust_link(struct dsa_switch *ds, int port,
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struct mt7530_priv *priv = ds->priv;
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if (phy_is_pseudo_fixed_link(phydev)) {
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dev_dbg(priv->dev, "phy-mode for master device = %x\n",
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phydev->interface);
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/* Setup TX circuit incluing relevant PAD and driving */
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mt7530_pad_clk_setup(ds, phydev->interface);
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if (priv->id == ID_MT7530) {
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dev_dbg(priv->dev, "phy-mode for master device = %x\n",
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phydev->interface);
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/* Setup TX circuit incluing relevant PAD and driving */
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mt7530_pad_clk_setup(ds, phydev->interface);
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/* Setup RX circuit, relevant PAD and driving on the
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* host which must be placed after the setup on the
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* device side is all finished.
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@ -244,6 +244,10 @@ enum mt7530_vlan_port_attr {
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/* Register for hw trap status */
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#define MT7530_HWTRAP 0x7800
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#define HWTRAP_XTAL_MASK (BIT(10) | BIT(9))
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#define HWTRAP_XTAL_25MHZ (BIT(10) | BIT(9))
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#define HWTRAP_XTAL_40MHZ (BIT(10))
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#define HWTRAP_XTAL_20MHZ (BIT(9))
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/* Register for hw trap modification */
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#define MT7530_MHWTRAP 0x7804
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@ -134,6 +134,28 @@ static int mtk_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)
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return _mtk_mdio_read(eth, phy_addr, phy_reg);
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}
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static int mt7621_gmac0_rgmii_adjust(struct mtk_eth *eth,
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phy_interface_t interface)
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{
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u32 val;
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/* Check DDR memory type. Currently DDR2 is not supported. */
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regmap_read(eth->ethsys, ETHSYS_SYSCFG, &val);
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if (val & SYSCFG_DRAM_TYPE_DDR2) {
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dev_err(eth->dev,
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"TRGMII mode with DDR2 memory is not supported!\n");
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return -EOPNOTSUPP;
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}
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val = (interface == PHY_INTERFACE_MODE_TRGMII) ?
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ETHSYS_TRGMII_MT7621_DDR_PLL : 0;
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regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0,
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ETHSYS_TRGMII_MT7621_MASK, val);
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return 0;
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}
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static void mtk_gmac0_rgmii_adjust(struct mtk_eth *eth, int speed)
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{
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u32 val;
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@ -183,9 +205,17 @@ static void mtk_phy_link_adjust(struct net_device *dev)
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break;
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}
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if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_GMAC1_TRGMII) &&
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!mac->id && !mac->trgmii)
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mtk_gmac0_rgmii_adjust(mac->hw, dev->phydev->speed);
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if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_GMAC1_TRGMII) && !mac->id) {
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if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_TRGMII_MT7621_CLK)) {
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if (mt7621_gmac0_rgmii_adjust(mac->hw,
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dev->phydev->interface))
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return;
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} else {
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if (!mac->trgmii)
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mtk_gmac0_rgmii_adjust(mac->hw,
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dev->phydev->speed);
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}
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}
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if (dev->phydev->link)
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mcr |= MAC_MCR_FORCE_LINK;
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@ -2607,7 +2637,7 @@ static const struct mtk_soc_data mt2701_data = {
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};
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static const struct mtk_soc_data mt7621_data = {
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.caps = MTK_SHARED_INT,
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.caps = MT7621_CAPS,
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.required_clks = MT7621_CLKS_BITMAP,
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.required_pctl = false,
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};
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@ -363,6 +363,10 @@
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#define MT7622_ETH 7622
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#define MT7621_ETH 7621
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/* ethernet system control register */
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#define ETHSYS_SYSCFG 0x10
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#define SYSCFG_DRAM_TYPE_DDR2 BIT(4)
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/* ethernet subsystem config register */
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#define ETHSYS_SYSCFG0 0x14
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#define SYSCFG0_GE_MASK 0x3
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@ -377,6 +381,9 @@
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/* ethernet subsystem clock register */
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#define ETHSYS_CLKCFG0 0x2c
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#define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11)
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#define ETHSYS_TRGMII_MT7621_MASK (BIT(5) | BIT(6))
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#define ETHSYS_TRGMII_MT7621_APLL BIT(6)
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#define ETHSYS_TRGMII_MT7621_DDR_PLL BIT(5)
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/* ethernet reset control register */
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#define ETHSYS_RSTCTRL 0x34
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@ -616,6 +623,7 @@ enum mtk_eth_path {
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#define MTK_SHARED_SGMII BIT(7)
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#define MTK_HWLRO BIT(8)
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#define MTK_SHARED_INT BIT(9)
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#define MTK_TRGMII_MT7621_CLK BIT(10)
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/* Supported path present on SoCs */
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#define MTK_PATH_BIT(x) BIT((x) + 10)
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@ -667,6 +675,9 @@ enum mtk_eth_path {
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#define MTK_HAS_CAPS(caps, _x) (((caps) & (_x)) == (_x))
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#define MT7621_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | \
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MTK_GMAC2_RGMII | MTK_SHARED_INT | MTK_TRGMII_MT7621_CLK)
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#define MT7622_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_SGMII | MTK_GMAC2_RGMII | \
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MTK_GMAC2_SGMII | MTK_GDM1_ESW | \
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MTK_MUX_GDM1_TO_GMAC1_ESW | \
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