Basic PWM driver for AVR32 and AT91
PWM device setup, and a simple PWM driver exposing a programming interface giving access to each channel's full capabilities. Note that this doesn't support starting several channels in synch. [hskinnemoen@atmel.com: allocate platform device dynamically] [hskinnemoen@atmel.com: Kconfig fix] Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com> Cc: Andrew Victor <linux@maxim.org.za> Cc: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
This commit is contained in:
David Brownell
Linus Torvalds
parent
c8cece84c9
commit
9a1e8eb1f0
6 changed files with 546 additions and 0 deletions
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@ -1185,6 +1185,59 @@ err_dup_modedb:
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}
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#endif
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/* --------------------------------------------------------------------
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* PWM
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* -------------------------------------------------------------------- */
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static struct resource atmel_pwm0_resource[] __initdata = {
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PBMEM(0xfff01400),
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IRQ(24),
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};
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static struct clk atmel_pwm0_mck = {
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.name = "mck",
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.parent = &pbb_clk,
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.mode = pbb_clk_mode,
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.get_rate = pbb_clk_get_rate,
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.index = 5,
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};
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struct platform_device *__init at32_add_device_pwm(u32 mask)
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{
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struct platform_device *pdev;
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if (!mask)
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return NULL;
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pdev = platform_device_alloc("atmel_pwm", 0);
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if (!pdev)
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return NULL;
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if (platform_device_add_resources(pdev, atmel_pwm0_resource,
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ARRAY_SIZE(atmel_pwm0_resource)))
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goto out_free_pdev;
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if (platform_device_add_data(pdev, &mask, sizeof(mask)))
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goto out_free_pdev;
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if (mask & (1 << 0))
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select_peripheral(PA(28), PERIPH_A, 0);
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if (mask & (1 << 1))
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select_peripheral(PA(29), PERIPH_A, 0);
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if (mask & (1 << 2))
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select_peripheral(PA(21), PERIPH_B, 0);
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if (mask & (1 << 3))
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select_peripheral(PA(22), PERIPH_B, 0);
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atmel_pwm0_mck.dev = &pdev->dev;
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platform_device_add(pdev);
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return pdev;
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out_free_pdev:
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platform_device_put(pdev);
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return NULL;
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}
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/* --------------------------------------------------------------------
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* SSC
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* -------------------------------------------------------------------- */
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@ -1646,6 +1699,7 @@ struct clk *at32_clock_list[] = {
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&atmel_usart1_usart,
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&atmel_usart2_usart,
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&atmel_usart3_usart,
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&atmel_pwm0_mck,
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#if defined(CONFIG_CPU_AT32AP7000)
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&macb0_hclk,
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&macb0_pclk,
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@ -13,6 +13,15 @@ menuconfig MISC_DEVICES
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if MISC_DEVICES
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config ATMEL_PWM
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tristate "Atmel AT32/AT91 PWM support"
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depends on AVR32 || ARCH_AT91
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help
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This option enables device driver support for the PWM channels
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on certain Atmel prcoessors. Pulse Width Modulation is used for
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purposes including software controlled power-efficent backlights
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on LCD displays, motor control, and waveform generation.
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config IBM_ASM
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tristate "Device driver for IBM RSA service processor"
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depends on X86 && PCI && INPUT && EXPERIMENTAL
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@ -8,6 +8,7 @@ obj-$(CONFIG_HDPU_FEATURES) += hdpuftrs/
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obj-$(CONFIG_MSI_LAPTOP) += msi-laptop.o
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obj-$(CONFIG_ACER_WMI) += acer-wmi.o
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obj-$(CONFIG_ASUS_LAPTOP) += asus-laptop.o
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obj-$(CONFIG_ATMEL_PWM) += atmel_pwm.o
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obj-$(CONFIG_ATMEL_SSC) += atmel-ssc.o
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obj-$(CONFIG_TC1100_WMI) += tc1100-wmi.o
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obj-$(CONFIG_LKDTM) += lkdtm.o
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409
drivers/misc/atmel_pwm.c
Normal file
409
drivers/misc/atmel_pwm.c
Normal file
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@ -0,0 +1,409 @@
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#include <linux/module.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/interrupt.h>
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#include <linux/platform_device.h>
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#include <linux/atmel_pwm.h>
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/*
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* This is a simple driver for the PWM controller found in various newer
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* Atmel SOCs, including the AVR32 series and the AT91sam9263.
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*
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* Chips with current Linux ports have only 4 PWM channels, out of max 32.
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* AT32UC3A and AT32UC3B chips have 7 channels (but currently no Linux).
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* Docs are inconsistent about the width of the channel counter registers;
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* it's at least 16 bits, but several places say 20 bits.
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*/
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#define PWM_NCHAN 4 /* max 32 */
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struct pwm {
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spinlock_t lock;
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struct platform_device *pdev;
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u32 mask;
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int irq;
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void __iomem *base;
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struct clk *clk;
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struct pwm_channel *channel[PWM_NCHAN];
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void (*handler[PWM_NCHAN])(struct pwm_channel *);
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};
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/* global PWM controller registers */
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#define PWM_MR 0x00
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#define PWM_ENA 0x04
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#define PWM_DIS 0x08
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#define PWM_SR 0x0c
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#define PWM_IER 0x10
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#define PWM_IDR 0x14
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#define PWM_IMR 0x18
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#define PWM_ISR 0x1c
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static inline void pwm_writel(const struct pwm *p, unsigned offset, u32 val)
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{
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__raw_writel(val, p->base + offset);
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}
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static inline u32 pwm_readl(const struct pwm *p, unsigned offset)
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{
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return __raw_readl(p->base + offset);
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}
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static inline void __iomem *pwmc_regs(const struct pwm *p, int index)
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{
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return p->base + 0x200 + index * 0x20;
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}
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static struct pwm *pwm;
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static void pwm_dumpregs(struct pwm_channel *ch, char *tag)
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{
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struct device *dev = &pwm->pdev->dev;
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dev_dbg(dev, "%s: mr %08x, sr %08x, imr %08x\n",
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tag,
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pwm_readl(pwm, PWM_MR),
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pwm_readl(pwm, PWM_SR),
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pwm_readl(pwm, PWM_IMR));
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dev_dbg(dev,
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"pwm ch%d - mr %08x, dty %u, prd %u, cnt %u\n",
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ch->index,
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pwm_channel_readl(ch, PWM_CMR),
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pwm_channel_readl(ch, PWM_CDTY),
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pwm_channel_readl(ch, PWM_CPRD),
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pwm_channel_readl(ch, PWM_CCNT));
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}
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/**
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* pwm_channel_alloc - allocate an unused PWM channel
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* @index: identifies the channel
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* @ch: structure to be initialized
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*
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* Drivers allocate PWM channels according to the board's wiring, and
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* matching board-specific setup code. Returns zero or negative errno.
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*/
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int pwm_channel_alloc(int index, struct pwm_channel *ch)
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{
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unsigned long flags;
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int status = 0;
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/* insist on PWM init, with this signal pinned out */
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if (!pwm || !(pwm->mask & 1 << index))
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return -ENODEV;
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if (index < 0 || index >= PWM_NCHAN || !ch)
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return -EINVAL;
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memset(ch, 0, sizeof *ch);
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spin_lock_irqsave(&pwm->lock, flags);
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if (pwm->channel[index])
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status = -EBUSY;
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else {
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clk_enable(pwm->clk);
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ch->regs = pwmc_regs(pwm, index);
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ch->index = index;
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/* REVISIT: ap7000 seems to go 2x as fast as we expect!! */
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ch->mck = clk_get_rate(pwm->clk);
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pwm->channel[index] = ch;
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pwm->handler[index] = NULL;
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/* channel and irq are always disabled when we return */
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pwm_writel(pwm, PWM_DIS, 1 << index);
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pwm_writel(pwm, PWM_IDR, 1 << index);
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}
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spin_unlock_irqrestore(&pwm->lock, flags);
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return status;
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}
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EXPORT_SYMBOL(pwm_channel_alloc);
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static int pwmcheck(struct pwm_channel *ch)
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{
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int index;
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if (!pwm)
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return -ENODEV;
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if (!ch)
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return -EINVAL;
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index = ch->index;
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if (index < 0 || index >= PWM_NCHAN || pwm->channel[index] != ch)
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return -EINVAL;
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return index;
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}
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/**
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* pwm_channel_free - release a previously allocated channel
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* @ch: the channel being released
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*
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* The channel is completely shut down (counter and IRQ disabled),
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* and made available for re-use. Returns zero, or negative errno.
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*/
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int pwm_channel_free(struct pwm_channel *ch)
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{
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unsigned long flags;
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int t;
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spin_lock_irqsave(&pwm->lock, flags);
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t = pwmcheck(ch);
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if (t >= 0) {
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pwm->channel[t] = NULL;
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pwm->handler[t] = NULL;
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/* channel and irq are always disabled when we return */
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pwm_writel(pwm, PWM_DIS, 1 << t);
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pwm_writel(pwm, PWM_IDR, 1 << t);
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clk_disable(pwm->clk);
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t = 0;
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}
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spin_unlock_irqrestore(&pwm->lock, flags);
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return t;
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}
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EXPORT_SYMBOL(pwm_channel_free);
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int __pwm_channel_onoff(struct pwm_channel *ch, int enabled)
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{
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unsigned long flags;
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int t;
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/* OMITTED FUNCTIONALITY: starting several channels in synch */
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spin_lock_irqsave(&pwm->lock, flags);
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t = pwmcheck(ch);
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if (t >= 0) {
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pwm_writel(pwm, enabled ? PWM_ENA : PWM_DIS, 1 << t);
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t = 0;
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pwm_dumpregs(ch, enabled ? "enable" : "disable");
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}
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spin_unlock_irqrestore(&pwm->lock, flags);
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return t;
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}
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EXPORT_SYMBOL(__pwm_channel_onoff);
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/**
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* pwm_clk_alloc - allocate and configure CLKA or CLKB
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* @prescale: from 0..10, the power of two used to divide MCK
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* @div: from 1..255, the linear divisor to use
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*
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* Returns PWM_CPR_CLKA, PWM_CPR_CLKB, or negative errno. The allocated
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* clock will run with a period of (2^prescale * div) / MCK, or twice as
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* long if center aligned PWM output is used. The clock must later be
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* deconfigured using pwm_clk_free().
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*/
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int pwm_clk_alloc(unsigned prescale, unsigned div)
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{
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unsigned long flags;
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u32 mr;
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u32 val = (prescale << 8) | div;
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int ret = -EBUSY;
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if (prescale >= 10 || div == 0 || div > 255)
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return -EINVAL;
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spin_lock_irqsave(&pwm->lock, flags);
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mr = pwm_readl(pwm, PWM_MR);
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if ((mr & 0xffff) == 0) {
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mr |= val;
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ret = PWM_CPR_CLKA;
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}
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if ((mr & (0xffff << 16)) == 0) {
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mr |= val << 16;
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ret = PWM_CPR_CLKB;
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}
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if (ret > 0)
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pwm_writel(pwm, PWM_MR, mr);
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spin_unlock_irqrestore(&pwm->lock, flags);
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return ret;
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}
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EXPORT_SYMBOL(pwm_clk_alloc);
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/**
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* pwm_clk_free - deconfigure and release CLKA or CLKB
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*
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* Reverses the effect of pwm_clk_alloc().
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*/
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void pwm_clk_free(unsigned clk)
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{
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unsigned long flags;
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u32 mr;
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spin_lock_irqsave(&pwm->lock, flags);
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mr = pwm_readl(pwm, PWM_MR);
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if (clk == PWM_CPR_CLKA)
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pwm_writel(pwm, PWM_MR, mr & ~(0xffff << 0));
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if (clk == PWM_CPR_CLKB)
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pwm_writel(pwm, PWM_MR, mr & ~(0xffff << 16));
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spin_unlock_irqrestore(&pwm->lock, flags);
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}
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EXPORT_SYMBOL(pwm_clk_free);
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/**
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* pwm_channel_handler - manage channel's IRQ handler
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* @ch: the channel
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* @handler: the handler to use, possibly NULL
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*
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* If the handler is non-null, the handler will be called after every
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* period of this PWM channel. If the handler is null, this channel
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* won't generate an IRQ.
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*/
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int pwm_channel_handler(struct pwm_channel *ch,
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void (*handler)(struct pwm_channel *ch))
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{
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unsigned long flags;
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int t;
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spin_lock_irqsave(&pwm->lock, flags);
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t = pwmcheck(ch);
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if (t >= 0) {
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pwm->handler[t] = handler;
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pwm_writel(pwm, handler ? PWM_IER : PWM_IDR, 1 << t);
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t = 0;
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}
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spin_unlock_irqrestore(&pwm->lock, flags);
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return t;
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}
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EXPORT_SYMBOL(pwm_channel_handler);
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static irqreturn_t pwm_irq(int id, void *_pwm)
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{
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struct pwm *p = _pwm;
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irqreturn_t handled = IRQ_NONE;
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u32 irqstat;
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int index;
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spin_lock(&p->lock);
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/* ack irqs, then handle them */
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irqstat = pwm_readl(pwm, PWM_ISR);
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while (irqstat) {
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struct pwm_channel *ch;
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void (*handler)(struct pwm_channel *ch);
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index = ffs(irqstat) - 1;
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irqstat &= ~(1 << index);
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ch = pwm->channel[index];
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handler = pwm->handler[index];
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if (handler && ch) {
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spin_unlock(&p->lock);
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handler(ch);
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spin_lock(&p->lock);
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handled = IRQ_HANDLED;
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}
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}
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spin_unlock(&p->lock);
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return handled;
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}
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static int __init pwm_probe(struct platform_device *pdev)
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{
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struct resource *r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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int irq = platform_get_irq(pdev, 0);
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u32 *mp = pdev->dev.platform_data;
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struct pwm *p;
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int status = -EIO;
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if (pwm)
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return -EBUSY;
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if (!r || irq < 0 || !mp || !*mp)
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return -ENODEV;
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if (*mp & ~((1<<PWM_NCHAN)-1)) {
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dev_warn(&pdev->dev, "mask 0x%x ... more than %d channels\n",
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*mp, PWM_NCHAN);
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return -EINVAL;
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}
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p = kzalloc(sizeof(*p), GFP_KERNEL);
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if (!p)
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return -ENOMEM;
|
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|
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spin_lock_init(&p->lock);
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p->pdev = pdev;
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p->mask = *mp;
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p->irq = irq;
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p->base = ioremap(r->start, r->end - r->start + 1);
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if (!p->base)
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goto fail;
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p->clk = clk_get(&pdev->dev, "mck");
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if (IS_ERR(p->clk)) {
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status = PTR_ERR(p->clk);
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p->clk = NULL;
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goto fail;
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}
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status = request_irq(irq, pwm_irq, 0, pdev->name, p);
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if (status < 0)
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goto fail;
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pwm = p;
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platform_set_drvdata(pdev, p);
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return 0;
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fail:
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if (p->clk)
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clk_put(p->clk);
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if (p->base)
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iounmap(p->base);
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kfree(p);
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return status;
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}
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static int __exit pwm_remove(struct platform_device *pdev)
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{
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struct pwm *p = platform_get_drvdata(pdev);
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if (p != pwm)
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return -EINVAL;
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clk_enable(pwm->clk);
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pwm_writel(pwm, PWM_DIS, (1 << PWM_NCHAN) - 1);
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pwm_writel(pwm, PWM_IDR, (1 << PWM_NCHAN) - 1);
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clk_disable(pwm->clk);
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pwm = NULL;
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free_irq(p->irq, p);
|
||||
clk_put(p->clk);
|
||||
iounmap(p->base);
|
||||
kfree(p);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver atmel_pwm_driver = {
|
||||
.driver = {
|
||||
.name = "atmel_pwm",
|
||||
.owner = THIS_MODULE,
|
||||
},
|
||||
.remove = __exit_p(pwm_remove),
|
||||
|
||||
/* NOTE: PWM can keep running in AVR32 "idle" and "frozen" states;
|
||||
* and all AT91sam9263 states, albeit at reduced clock rate if
|
||||
* MCK becomes the slow clock (i.e. what Linux labels STR).
|
||||
*/
|
||||
};
|
||||
|
||||
static int __init pwm_init(void)
|
||||
{
|
||||
return platform_driver_probe(&atmel_pwm_driver, pwm_probe);
|
||||
}
|
||||
module_init(pwm_init);
|
||||
|
||||
static void __exit pwm_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&atmel_pwm_driver);
|
||||
}
|
||||
module_exit(pwm_exit);
|
||||
|
||||
MODULE_DESCRIPTION("Driver for AT32/AT91 PWM module");
|
||||
MODULE_LICENSE("GPL");
|
||||
|
|
@ -51,6 +51,9 @@ struct platform_device *
|
|||
at32_add_device_ide(unsigned int id, unsigned int extint,
|
||||
struct ide_platform_data *data);
|
||||
|
||||
/* mask says which PWM channels to mux */
|
||||
struct platform_device *at32_add_device_pwm(u32 mask);
|
||||
|
||||
/* depending on what's hooked up, not all SSC pins will be used */
|
||||
#define ATMEL_SSC_TK 0x01
|
||||
#define ATMEL_SSC_TF 0x02
|
||||
|
|
|
|||
70
include/linux/atmel_pwm.h
Normal file
70
include/linux/atmel_pwm.h
Normal file
|
|
@ -0,0 +1,70 @@
|
|||
#ifndef __LINUX_ATMEL_PWM_H
|
||||
#define __LINUX_ATMEL_PWM_H
|
||||
|
||||
/**
|
||||
* struct pwm_channel - driver handle to a PWM channel
|
||||
* @regs: base of this channel's registers
|
||||
* @index: number of this channel (0..31)
|
||||
* @mck: base clock rate, which can be prescaled and maybe subdivided
|
||||
*
|
||||
* Drivers initialize a pwm_channel structure using pwm_channel_alloc().
|
||||
* Then they configure its clock rate (derived from MCK), alignment,
|
||||
* polarity, and duty cycle by writing directly to the channel registers,
|
||||
* before enabling the channel by calling pwm_channel_enable().
|
||||
*
|
||||
* After emitting a PWM signal for the desired length of time, drivers
|
||||
* may then pwm_channel_disable() or pwm_channel_free(). Both of these
|
||||
* disable the channel, but when it's freed the IRQ is deconfigured and
|
||||
* the channel must later be re-allocated and reconfigured.
|
||||
*
|
||||
* Note that if the period or duty cycle need to be changed while the
|
||||
* PWM channel is operating, drivers must use the PWM_CUPD double buffer
|
||||
* mechanism, either polling until they change or getting implicitly
|
||||
* notified through a once-per-period interrupt handler.
|
||||
*/
|
||||
struct pwm_channel {
|
||||
void __iomem *regs;
|
||||
unsigned index;
|
||||
unsigned long mck;
|
||||
};
|
||||
|
||||
extern int pwm_channel_alloc(int index, struct pwm_channel *ch);
|
||||
extern int pwm_channel_free(struct pwm_channel *ch);
|
||||
|
||||
extern int pwm_clk_alloc(unsigned prescale, unsigned div);
|
||||
extern void pwm_clk_free(unsigned clk);
|
||||
|
||||
extern int __pwm_channel_onoff(struct pwm_channel *ch, int enabled);
|
||||
|
||||
#define pwm_channel_enable(ch) __pwm_channel_onoff((ch), 1)
|
||||
#define pwm_channel_disable(ch) __pwm_channel_onoff((ch), 0)
|
||||
|
||||
/* periodic interrupts, mostly for CUPD changes to period or cycle */
|
||||
extern int pwm_channel_handler(struct pwm_channel *ch,
|
||||
void (*handler)(struct pwm_channel *ch));
|
||||
|
||||
/* per-channel registers (banked at pwm_channel->regs) */
|
||||
#define PWM_CMR 0x00 /* mode register */
|
||||
#define PWM_CPR_CPD (1 << 10) /* set: CUPD modifies period */
|
||||
#define PWM_CPR_CPOL (1 << 9) /* set: idle high */
|
||||
#define PWM_CPR_CALG (1 << 8) /* set: center align */
|
||||
#define PWM_CPR_CPRE (0xf << 0) /* mask: rate is mck/(2^pre) */
|
||||
#define PWM_CPR_CLKA (0xb << 0) /* rate CLKA */
|
||||
#define PWM_CPR_CLKB (0xc << 0) /* rate CLKB */
|
||||
#define PWM_CDTY 0x04 /* duty cycle (max of CPRD) */
|
||||
#define PWM_CPRD 0x08 /* period (count up from zero) */
|
||||
#define PWM_CCNT 0x0c /* counter (20 bits?) */
|
||||
#define PWM_CUPD 0x10 /* update CPRD (or CDTY) next period */
|
||||
|
||||
static inline void
|
||||
pwm_channel_writel(struct pwm_channel *pwmc, unsigned offset, u32 val)
|
||||
{
|
||||
__raw_writel(val, pwmc->regs + offset);
|
||||
}
|
||||
|
||||
static inline u32 pwm_channel_readl(struct pwm_channel *pwmc, unsigned offset)
|
||||
{
|
||||
return __raw_readl(pwmc->regs + offset);
|
||||
}
|
||||
|
||||
#endif /* __LINUX_ATMEL_PWM_H */
|
||||
Loading…
Reference in a new issue