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Merge commit '9f12600fe425bc28f0ccba034a77783c09c15af4' into for-linus

Browse source 
Backmerge of dcache.c changes from mainline.  It's that, or complete
rebase...

Conflicts:
	fs/splice.c

Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
This commit is contained in:
Al Viro 2014-06-12 00:27:11 -04:00
commit 9c1d5284c7
599 changed files with 7376 additions and 3792 deletions
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2
Documentation/ABI/testing/sysfs-bus-pci
View file

@ -117,7 +117,7 @@ Description:
What: /sys/bus/pci/devices/.../vpd
Date: February 2008
Contact: Ben Hutchings <bhutchings@solarflare.com>
Contact: Ben Hutchings <bwh@kernel.org>
Description:
A file named vpd in a device directory will be a
binary file containing the Vital Product Data for the

12
Documentation/DocBook/drm.tmpl
View file

@ -79,7 +79,7 @@
<partintro>
<para>
This first part of the DRM Developer's Guide documents core DRM code,
helper libraries for writting drivers and generic userspace interfaces
helper libraries for writing drivers and generic userspace interfaces
exposed by DRM drivers.
</para>
</partintro>
@ -459,7 +459,7 @@ char *date;</synopsis>
providing a solution to every graphics memory-related problems, GEM
identified common code between drivers and created a support library to
share it. GEM has simpler initialization and execution requirements than
TTM, but has no video RAM management capabitilies and is thus limited to
TTM, but has no video RAM management capabilities and is thus limited to
UMA devices.
</para>
<sect2>
@ -889,7 +889,7 @@ int (*prime_fd_to_handle)(struct drm_device *dev,
vice versa. Drivers must use the kernel dma-buf buffer sharing framework
to manage the PRIME file descriptors. Similar to the mode setting
API PRIME is agnostic to the underlying buffer object manager, as
long as handles are 32bit unsinged integers.
long as handles are 32bit unsigned integers.
</para>
<para>
While non-GEM drivers must implement the operations themselves, GEM
@ -2356,7 +2356,7 @@ void intel_crt_init(struct drm_device *dev)
first create properties and then create and associate individual instances
of those properties to objects. A property can be instantiated multiple
times and associated with different objects. Values are stored in property
instances, and all other property information are stored in the propery
instances, and all other property information are stored in the property
and shared between all instances of the property.
</para>
<para>
@ -2697,10 +2697,10 @@ int num_ioctls;</synopsis>
<sect1>
<title>Legacy Support Code</title>
<para>
The section very brievely covers some of the old legacy support code which
The section very briefly covers some of the old legacy support code which
is only used by old DRM drivers which have done a so-called shadow-attach
to the underlying device instead of registering as a real driver. This
also includes some of the old generic buffer mangement and command
also includes some of the old generic buffer management and command
submission code. Do not use any of this in new and modern drivers.
</para>

2
Documentation/DocBook/media/Makefile
View file

@ -195,7 +195,7 @@ DVB_DOCUMENTED = \
#
install_media_images = \
$(Q)cp $(OBJIMGFILES) $(MEDIA_SRC_DIR)/v4l/*.svg $(MEDIA_OBJ_DIR)/media_api
$(Q)-cp $(OBJIMGFILES) $(MEDIA_SRC_DIR)/v4l/*.svg $(MEDIA_OBJ_DIR)/media_api
$(MEDIA_OBJ_DIR)/%: $(MEDIA_SRC_DIR)/%.b64
$(Q)base64 -d $< >$@

13
Documentation/debugging-via-ohci1394.txt
View file

@ -25,9 +25,11 @@ using data transfer rates in the order of 10MB/s or more.
With most FireWire controllers, memory access is limited to the low 4 GB
of physical address space. This can be a problem on IA64 machines where
memory is located mostly above that limit, but it is rarely a problem on
more common hardware such as x86, x86-64 and PowerPC. However, at least
Agere/LSI FW643e and FW643e2 controllers are known to support access to
physical addresses above 4 GB.
more common hardware such as x86, x86-64 and PowerPC.
At least LSI FW643e and FW643e2 controllers are known to support access to
physical addresses above 4 GB, but this feature is currently not enabled by
Linux.
Together with a early initialization of the OHCI-1394 controller for debugging,
this facility proved most useful for examining long debugs logs in the printk
@ -101,8 +103,9 @@ Step-by-step instructions for using firescope with early OHCI initialization:
compliant, they are based on TI PCILynx chips and require drivers for Win-
dows operating systems.
The mentioned kernel log message contains ">4 GB phys DMA" in case of
OHCI-1394 controllers which support accesses above this limit.
The mentioned kernel log message contains the string "physUB" if the
controller implements a writable Physical Upper Bound register. This is
required for physical DMA above 4 GB (but not utilized by Linux yet).
2) Establish a working FireWire cable connection:

5
Documentation/device-mapper/thin-provisioning.txt
View file

@ -309,7 +309,10 @@ ii) Status
error_if_no_space|queue_if_no_space
If the pool runs out of data or metadata space, the pool will
either queue or error the IO destined to the data device. The
default is to queue the IO until more space is added.
default is to queue the IO until more space is added or the
'no_space_timeout' expires. The 'no_space_timeout' dm-thin-pool
module parameter can be used to change this timeout -- it
defaults to 60 seconds but may be disabled using a value of 0.
iii) Messages

2
Documentation/devicetree/bindings/clock/at91-clock.txt
View file

@ -62,7 +62,7 @@ Required properties for PMC node:
- interrupt-controller : tell that the PMC is an interrupt controller.
- #interrupt-cells : must be set to 1. The first cell encodes the interrupt id,
and reflect the bit position in the PMC_ER/DR/SR registers.
You can use the dt macros defined in dt-bindings/clk/at91.h.
You can use the dt macros defined in dt-bindings/clock/at91.h.
0 (AT91_PMC_MOSCS) -> main oscillator ready
1 (AT91_PMC_LOCKA) -> PLL A ready
2 (AT91_PMC_LOCKB) -> PLL B ready

2
Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt
View file

@ -43,7 +43,7 @@ Example
clock-output-names =
"tpu0", "mmcif1", "sdhi3", "sdhi2",
"sdhi1", "sdhi0", "mmcif0";
renesas,clock-indices = <
clock-indices = <
R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3
R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0
R8A7790_CLK_MMCIF0

4
Documentation/devicetree/bindings/dma/ti-edma.txt
View file

@ -29,6 +29,6 @@ edma: edma@49000000 {
dma-channels = <64>;
ti,edma-regions = <4>;
ti,edma-slots = <256>;
ti,edma-xbar-event-map = <1 12
2 13>;
ti,edma-xbar-event-map = /bits/ 16 <1 12
2 13>;
};

2
Documentation/devicetree/bindings/net/mdio-gpio.txt
View file

@ -14,7 +14,7 @@ node.
Example:
aliases {
mdio-gpio0 = <&mdio0>;
mdio-gpio0 = &mdio0;
};
mdio0: mdio {

15
Documentation/email-clients.txt
View file

@ -201,20 +201,15 @@ To beat some sense out of the internal editor, do this:
- Edit your Thunderbird config settings so that it won't use format=flowed.
Go to "edit->preferences->advanced->config editor" to bring up the
thunderbird's registry editor, and set "mailnews.send_plaintext_flowed" to
"false".
thunderbird's registry editor.
- Disable HTML Format: Set "mail.identity.id1.compose_html" to "false".
- Set "mailnews.send_plaintext_flowed" to "false"
- Enable "preformat" mode: Set "editor.quotesPreformatted" to "true".
- Set "mailnews.wraplength" from "72" to "0"
- Enable UTF8: Set "prefs.converted-to-utf8" to "true".
- "View" > "Message Body As" > "Plain Text"
- Install the "toggle wordwrap" extension. Download the file from:
https://addons.mozilla.org/thunderbird/addon/2351/
Then go to "tools->add ons", select "install" at the bottom of the screen,
and browse to where you saved the .xul file. This adds an "Enable
Wordwrap" entry under the Options menu of the message composer.
- "View" > "Character Encoding" > "Unicode (UTF-8)"
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
TkRat (GUI)

5
Documentation/filesystems/proc.txt
View file

@ -1245,8 +1245,9 @@ second). The meanings of the columns are as follows, from left to right:
The "intr" line gives counts of interrupts serviced since boot time, for each
of the possible system interrupts. The first column is the total of all
interrupts serviced; each subsequent column is the total for that particular
interrupt.
interrupts serviced including unnumbered architecture specific interrupts;
each subsequent column is the total for that particular numbered interrupt.
Unnumbered interrupts are not shown, only summed into the total.
The "ctxt" line gives the total number of context switches across all CPUs.

14
Documentation/hwmon/sysfs-interface
View file

@ -327,6 +327,13 @@ temp[1-*]_max_hyst
from the max value.
RW
temp[1-*]_min_hyst
Temperature hysteresis value for min limit.
Unit: millidegree Celsius
Must be reported as an absolute temperature, NOT a delta
from the min value.
RW
temp[1-*]_input Temperature input value.
Unit: millidegree Celsius
RO
@ -362,6 +369,13 @@ temp[1-*]_lcrit Temperature critical min value, typically lower than
Unit: millidegree Celsius
RW
temp[1-*]_lcrit_hyst
Temperature hysteresis value for critical min limit.
Unit: millidegree Celsius
Must be reported as an absolute temperature, NOT a delta
from the critical min value.
RW
temp[1-*]_offset
Temperature offset which is added to the temperature reading
by the chip.

5
Documentation/input/elantech.txt
View file

@ -504,9 +504,12 @@ byte 5:
* reg_10
bit 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 A
0 0 0 0 R F T A
A: 1 = enable absolute tracking
T: 1 = enable two finger mode auto correct
F: 1 = disable ABS Position Filter
R: 1 = enable real hardware resolution
6.2 Native absolute mode 6 byte packet format
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

8
Documentation/java.txt
View file

@ -188,6 +188,9 @@ shift
#define CP_METHODREF 10
#define CP_INTERFACEMETHODREF 11
#define CP_NAMEANDTYPE 12
#define CP_METHODHANDLE 15
#define CP_METHODTYPE 16
#define CP_INVOKEDYNAMIC 18
/* Define some commonly used error messages */
@ -242,14 +245,19 @@ void skip_constant(FILE *classfile, u_int16_t *cur)
break;
case CP_CLASS:
case CP_STRING:
case CP_METHODTYPE:
seekerr = fseek(classfile, 2, SEEK_CUR);
break;
case CP_METHODHANDLE:
seekerr = fseek(classfile, 3, SEEK_CUR);
break;
case CP_INTEGER:
case CP_FLOAT:
case CP_FIELDREF:
case CP_METHODREF:
case CP_INTERFACEMETHODREF:
case CP_NAMEANDTYPE:
case CP_INVOKEDYNAMIC:
seekerr = fseek(classfile, 4, SEEK_CUR);
break;
case CP_LONG:

8
Documentation/kernel-parameters.txt
View file

@ -2218,10 +2218,10 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
noreplace-smp [X86-32,SMP] Don't replace SMP instructions
with UP alternatives
nordrand [X86] Disable the direct use of the RDRAND
instruction even if it is supported by the
processor. RDRAND is still available to user
space applications.
nordrand [X86] Disable kernel use of the RDRAND and
RDSEED instructions even if they are supported
by the processor. RDRAND and RDSEED are still
available to user space applications.
noresume [SWSUSP] Disables resume and restores original swap
space.

2
Documentation/networking/filter.txt
View file

@ -277,7 +277,7 @@ Possible BPF extensions are shown in the following table:
mark skb->mark
queue skb->queue_mapping
hatype skb->dev->type
rxhash skb->rxhash
rxhash skb->hash
cpu raw_smp_processor_id()
vlan_tci vlan_tx_tag_get(skb)
vlan_pr vlan_tx_tag_present(skb)

2
Documentation/networking/packet_mmap.txt
View file

@ -578,7 +578,7 @@ processes. This also works in combination with mmap(2) on packet sockets.
Currently implemented fanout policies are:
- PACKET_FANOUT_HASH: schedule to socket by skb's rxhash
- PACKET_FANOUT_HASH: schedule to socket by skb's packet hash
- PACKET_FANOUT_LB: schedule to socket by round-robin
- PACKET_FANOUT_CPU: schedule to socket by CPU packet arrives on
- PACKET_FANOUT_RND: schedule to socket by random selection

2
Documentation/virtual/kvm/api.txt
View file

@ -2126,7 +2126,7 @@ into the hash PTE second double word).
4.75 KVM_IRQFD
Capability: KVM_CAP_IRQFD
Architectures: x86
Architectures: x86 s390
Type: vm ioctl
Parameters: struct kvm_irqfd (in)
Returns: 0 on success, -1 on error

44
MAINTAINERS
View file

@ -537,7 +537,7 @@ L: linux-alpha@vger.kernel.org
F: arch/alpha/
ALTERA TRIPLE SPEED ETHERNET DRIVER
M: Vince Bridgers <vbridgers2013@gmail.com
M: Vince Bridgers <vbridgers2013@gmail.com>
L: netdev@vger.kernel.org
L: nios2-dev@lists.rocketboards.org (moderated for non-subscribers)
S: Maintained
@ -1893,14 +1893,15 @@ L: netdev@vger.kernel.org
S: Supported
F: drivers/net/ethernet/broadcom/bnx2x/
BROADCOM BCM281XX/BCM11XXX ARM ARCHITECTURE
BROADCOM BCM281XX/BCM11XXX/BCM216XX ARM ARCHITECTURE
M: Christian Daudt <bcm@fixthebug.org>
M: Matt Porter <mporter@linaro.org>
L: bcm-kernel-feedback-list@broadcom.com
T: git git://git.github.com/broadcom/bcm11351
T: git git://github.com/broadcom/mach-bcm
S: Maintained
F: arch/arm/mach-bcm/
F: arch/arm/boot/dts/bcm113*
F: arch/arm/boot/dts/bcm216*
F: arch/arm/boot/dts/bcm281*
F: arch/arm/configs/bcm_defconfig
F: drivers/mmc/host/sdhci_bcm_kona.c
@ -2245,12 +2246,6 @@ L: linux-usb@vger.kernel.org
S: Maintained
F: drivers/usb/host/ohci-ep93xx.c
CIRRUS LOGIC CS4270 SOUND DRIVER
M: Timur Tabi <timur@tabi.org>
L: alsa-devel@alsa-project.org (moderated for non-subscribers)
S: Odd Fixes
F: sound/soc/codecs/cs4270*
CIRRUS LOGIC AUDIO CODEC DRIVERS
M: Brian Austin <brian.austin@cirrus.com>
M: Paul Handrigan <Paul.Handrigan@cirrus.com>
@ -4818,6 +4813,14 @@ L: linux-kernel@vger.kernel.org
S: Maintained
T: git git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git irq/core
F: kernel/irq/
IRQCHIP DRIVERS
M: Thomas Gleixner <tglx@linutronix.de>
M: Jason Cooper <jason@lakedaemon.net>
L: linux-kernel@vger.kernel.org
S: Maintained
T: git git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git irq/core
T: git git://git.infradead.org/users/jcooper/linux.git irqchip/core
F: drivers/irqchip/
IRQ DOMAINS (IRQ NUMBER MAPPING LIBRARY)
@ -5490,15 +5493,15 @@ F: Documentation/hwmon/ltc4261
F: drivers/hwmon/ltc4261.c
LTP (Linux Test Project)
M: Shubham Goyal <shubham@linux.vnet.ibm.com>
M: Mike Frysinger <vapier@gentoo.org>
M: Cyril Hrubis <chrubis@suse.cz>
M: Caspar Zhang <caspar@casparzhang.com>
M: Wanlong Gao <gaowanlong@cn.fujitsu.com>
M: Jan Stancek <jstancek@redhat.com>
M: Stanislav Kholmanskikh <stanislav.kholmanskikh@oracle.com>
M: Alexey Kodanev <alexey.kodanev@oracle.com>
L: ltp-list@lists.sourceforge.net (subscribers-only)
W: http://ltp.sourceforge.net/
W: http://linux-test-project.github.io/
T: git git://github.com/linux-test-project/ltp.git
T: git git://ltp.git.sourceforge.net/gitroot/ltp/ltp-dev
S: Maintained
M32R ARCHITECTURE
@ -6511,10 +6514,10 @@ T: git git://openrisc.net/~jonas/linux
F: arch/openrisc/
OPENVSWITCH
M: Jesse Gross <jesse@nicira.com>
M: Pravin Shelar <pshelar@nicira.com>
L: dev@openvswitch.org
W: http://openvswitch.org
T: git git://git.kernel.org/pub/scm/linux/kernel/git/jesse/openvswitch.git
T: git git://git.kernel.org/pub/scm/linux/kernel/git/pshelar/openvswitch.git
S: Maintained
F: net/openvswitch/
@ -7402,6 +7405,14 @@ F: drivers/rpmsg/
F: Documentation/rpmsg.txt
F: include/linux/rpmsg.h
RESET CONTROLLER FRAMEWORK
M: Philipp Zabel <p.zabel@pengutronix.de>
S: Maintained
F: drivers/reset/
F: Documentation/devicetree/bindings/reset/
F: include/linux/reset.h
F: include/linux/reset-controller.h
RFKILL
M: Johannes Berg <johannes@sipsolutions.net>
L: linux-wireless@vger.kernel.org
@ -9107,6 +9118,9 @@ F: arch/um/os-Linux/drivers/
TURBOCHANNEL SUBSYSTEM
M: "Maciej W. Rozycki" <macro@linux-mips.org>
M: Ralf Baechle <ralf@linux-mips.org>
L: linux-mips@linux-mips.org
Q: http://patchwork.linux-mips.org/project/linux-mips/list/
S: Maintained
F: drivers/tc/
F: include/linux/tc.h

2
Makefile
View file

@ -1,7 +1,7 @@
VERSION = 3
PATCHLEVEL = 15
SUBLEVEL = 0
EXTRAVERSION = -rc4
EXTRAVERSION = -rc7
NAME = Shuffling Zombie Juror
# *DOCUMENTATION*

2
arch/arm/boot/dts/am33xx.dtsi
View file

@ -144,7 +144,7 @@
compatible = "ti,edma3";
ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2";
reg = <0x49000000 0x10000>,
<0x44e10f90 0x10>;
<0x44e10f90 0x40>;
interrupts = <12 13 14>;
#dma-cells = <1>;
dma-channels = <64>;

16
arch/arm/boot/dts/am3517.dtsi
View file

@ -62,5 +62,21 @@
};
};
&iva {
status = "disabled";
};
&mailbox {
status = "disabled";
};
&mmu_isp {
status = "disabled";
};
&smartreflex_mpu_iva {
status = "disabled";
};
/include/ "am35xx-clocks.dtsi"
/include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"

5
arch/arm/boot/dts/am437x-gp-evm.dts
View file

@ -117,6 +117,11 @@
status = "okay";
};
&gpio5 {
status = "okay";
ti,no-reset-on-init;
};
&mmc1 {
status = "okay";
vmmc-supply = <&vmmcsd_fixed>;

1
arch/arm/boot/dts/armada-370-db.dts
View file

@ -67,6 +67,7 @@
i2c@11000 {
pinctrl-0 = <&i2c0_pins>;
pinctrl-names = "default";
clock-frequency = <100000>;
status = "okay";
audio_codec: audio-codec@4a {
compatible = "cirrus,cs42l51";

5
arch/arm/boot/dts/armada-375-db.dts
View file

@ -79,6 +79,11 @@
};
};
sata@a0000 {
status = "okay";
nr-ports = <2>;
};
nand: nand@d0000 {
pinctrl-0 = <&nand_pins>;
pinctrl-names = "default";

2
arch/arm/boot/dts/armada-380.dtsi
View file

@ -99,7 +99,7 @@
pcie@3,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
reg = <0x1000 0 0 0 0>;
reg = <0x1800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;

4
arch/arm/boot/dts/armada-385.dtsi
View file

@ -110,7 +110,7 @@
pcie@3,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
reg = <0x1000 0 0 0 0>;
reg = <0x1800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
@ -131,7 +131,7 @@
pcie@4,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
reg = <0x1000 0 0 0 0>;
reg = <0x2000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;

2
arch/arm/boot/dts/armada-xp-db.dts
View file

@ -49,7 +49,7 @@
/* Device Bus parameters are required */
/* Read parameters */
devbus,bus-width = <8>;
devbus,bus-width = <16>;
devbus,turn-off-ps = <60000>;
devbus,badr-skew-ps = <0>;
devbus,acc-first-ps = <124000>;

10
arch/arm/boot/dts/armada-xp-gp.dts
View file

@ -59,7 +59,7 @@
/* Device Bus parameters are required */
/* Read parameters */
devbus,bus-width = <8>;
devbus,bus-width = <16>;
devbus,turn-off-ps = <60000>;
devbus,badr-skew-ps = <0>;
devbus,acc-first-ps = <124000>;
@ -146,22 +146,22 @@
ethernet@70000 {
status = "okay";
phy = <&phy0>;
phy-mode = "rgmii-id";
phy-mode = "qsgmii";
};
ethernet@74000 {
status = "okay";
phy = <&phy1>;
phy-mode = "rgmii-id";
phy-mode = "qsgmii";
};
ethernet@30000 {
status = "okay";
phy = <&phy2>;
phy-mode = "rgmii-id";
phy-mode = "qsgmii";
};
ethernet@34000 {
status = "okay";
phy = <&phy3>;
phy-mode = "rgmii-id";
phy-mode = "qsgmii";
};
/* Front-side USB slot */

2
arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
View file

@ -39,7 +39,7 @@
/* Device Bus parameters are required */
/* Read parameters */
devbus,bus-width = <8>;
devbus,bus-width = <16>;
devbus,turn-off-ps = <60000>;
devbus,badr-skew-ps = <0>;
devbus,acc-first-ps = <124000>;

4
arch/arm/boot/dts/at91-sama5d3_xplained.dts
View file

@ -34,7 +34,7 @@
};
spi0: spi@f0004000 {
cs-gpios = <&pioD 13 0>;
cs-gpios = <&pioD 13 0>, <0>, <0>, <&pioD 16 0>;
status = "okay";
};
@ -79,7 +79,7 @@
};
spi1: spi@f8008000 {
cs-gpios = <&pioC 25 0>, <0>, <0>, <&pioD 16 0>;
cs-gpios = <&pioC 25 0>;
status = "okay";
};

2
arch/arm/boot/dts/at91sam9260.dtsi
View file

@ -641,7 +641,7 @@
trigger@3 {
reg = <3>;
trigger-name = "external";
trigger-value = <0x13>;
trigger-value = <0xd>;
trigger-external;
};
};

2
arch/arm/boot/dts/at91sam9261.dtsi
View file

@ -10,7 +10,7 @@
#include <dt-bindings/pinctrl/at91.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clk/at91.h>
#include <dt-bindings/clock/at91.h>
/ {
model = "Atmel AT91SAM9261 family SoC";

2
arch/arm/boot/dts/at91sam9rl.dtsi
View file

@ -8,7 +8,7 @@
#include "skeleton.dtsi"
#include <dt-bindings/pinctrl/at91.h>
#include <dt-bindings/clk/at91.h>
#include <dt-bindings/clock/at91.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>

2
arch/arm/boot/dts/exynos4412-trats2.dts
View file

@ -503,7 +503,7 @@
status = "okay";
ak8975@0c {
compatible = "ak,ak8975";
compatible = "asahi-kasei,ak8975";
reg = <0x0c>;
gpios = <&gpj0 7 0>;
};

1
arch/arm/boot/dts/exynos5250-arndale.dts
View file

@ -107,6 +107,7 @@
regulator-name = "VDD_IOPERI_1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
op_mode = <1>;
};

12
arch/arm/boot/dts/exynos5420-arndale-octa.dts
View file

@ -364,16 +364,4 @@
gpio-key,wakeup;
};
};
amba {
mdma1: mdma@11C10000 {
/*
* MDMA1 can support both secure and non-secure
* AXI transactions. When this is enabled in the kernel
* for boards that run in secure mode, we are getting
* imprecise external aborts causing the kernel to oops.
*/
status = "disabled";
};
};
};

24
arch/arm/boot/dts/exynos5420.dtsi
View file

@ -219,16 +219,6 @@
reg = <0x100440C0 0x20>;
};
mau_pd: power-domain@100440E0 {
compatible = "samsung,exynos4210-pd";
reg = <0x100440E0 0x20>;
};
g2d_pd: power-domain@10044100 {
compatible = "samsung,exynos4210-pd";
reg = <0x10044100 0x20>;
};
msc_pd: power-domain@10044120 {
compatible = "samsung,exynos4210-pd";
reg = <0x10044120 0x20>;
@ -336,6 +326,13 @@
#dma-cells = <1>;
#dma-channels = <8>;
#dma-requests = <1>;
/*
* MDMA1 can support both secure and non-secure
* AXI transactions. When this is enabled in the kernel
* for boards that run in secure mode, we are getting
* imprecise external aborts causing the kernel to oops.
*/
status = "disabled";
};
};
@ -385,7 +382,7 @@
spi_0: spi@12d20000 {
compatible = "samsung,exynos4210-spi";
reg = <0x12d20000 0x100>;
interrupts = <0 66 0>;
interrupts = <0 68 0>;
dmas = <&pdma0 5
&pdma0 4>;
dma-names = "tx", "rx";
@ -401,7 +398,7 @@
spi_1: spi@12d30000 {
compatible = "samsung,exynos4210-spi";
reg = <0x12d30000 0x100>;
interrupts = <0 67 0>;
interrupts = <0 69 0>;
dmas = <&pdma1 5
&pdma1 4>;
dma-names = "tx", "rx";
@ -417,7 +414,7 @@
spi_2: spi@12d40000 {
compatible = "samsung,exynos4210-spi";
reg = <0x12d40000 0x100>;
interrupts = <0 68 0>;
interrupts = <0 70 0>;
dmas = <&pdma0 7
&pdma0 6>;
dma-names = "tx", "rx";
@ -730,6 +727,5 @@
interrupts = <0 112 0>;
clocks = <&clock 471>;
clock-names = "secss";
samsung,power-domain = <&g2d_pd>;
};
};

2
arch/arm/boot/dts/imx53-mba53.dts
View file

@ -244,7 +244,7 @@
&tve {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_vga_sync_1>;
i2c-ddc-bus = <&i2c3>;
ddc-i2c-bus = <&i2c3>;
fsl,tve-mode = "vga";
fsl,hsync-pin = <4>;
fsl,vsync-pin = <6>;

2
arch/arm/boot/dts/imx53.dtsi
View file

@ -115,7 +115,7 @@
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx53-ipu";
reg = <0x18000000 0x080000000>;
reg = <0x18000000 0x08000000>;
interrupts = <11 10>;
clocks = <&clks IMX5_CLK_IPU_GATE>,
<&clks IMX5_CLK_IPU_DI0_GATE>,

18
arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts
View file

@ -30,6 +30,16 @@
bootargs = "console=ttyS0,115200n8 earlyprintk";
};
mbus {
pcie-controller {
status = "okay";
pcie@1,0 {
status = "okay";
};
};
};
ocp@f1000000 {
pinctrl@10000 {
pmx_usb_led: pmx-usb-led {
@ -73,14 +83,6 @@
ehci@50000 {
status = "okay";
};
pcie-controller {
status = "okay";
pcie@1,0 {
status = "okay";
};
};
};
gpio-leds {

18
arch/arm/boot/dts/kirkwood-nsa310-common.dtsi
View file

@ -4,6 +4,16 @@
/ {
model = "ZyXEL NSA310";
mbus {
pcie-controller {
status = "okay";
pcie@1,0 {
status = "okay";
};
};
};
ocp@f1000000 {
pinctrl: pinctrl@10000 {
@ -26,14 +36,6 @@
status = "okay";
nr-ports = <2>;
};
pcie-controller {
status = "okay";
pcie@1,0 {
status = "okay";
};
};
};
gpio_poweroff {

5
arch/arm/boot/dts/kirkwood-t5325.dts
View file

@ -127,11 +127,6 @@
i2c@11000 {
status = "okay";
alc5621: alc5621@1a {
compatible = "realtek,alc5621";
reg = <0x1a>;
};
};
serial@12000 {

19
arch/arm/boot/dts/omap-gpmc-smsc911x.dtsi
View file

@ -24,11 +24,10 @@
compatible = "smsc,lan9221", "smsc,lan9115";
bank-width = <2>;
gpmc,mux-add-data;
gpmc,cs-on-ns = <0>;
gpmc,cs-rd-off-ns = <186>;
gpmc,cs-wr-off-ns = <186>;
gpmc,adv-on-ns = <12>;
gpmc,adv-rd-off-ns = <48>;
gpmc,cs-on-ns = <1>;
gpmc,cs-rd-off-ns = <180>;
gpmc,cs-wr-off-ns = <180>;
gpmc,adv-rd-off-ns = <18>;
gpmc,adv-wr-off-ns = <48>;
gpmc,oe-on-ns = <54>;
gpmc,oe-off-ns = <168>;
@ -36,12 +35,10 @@
gpmc,we-off-ns = <168>;
gpmc,rd-cycle-ns = <186>;
gpmc,wr-cycle-ns = <186>;
gpmc,access-ns = <114>;
gpmc,page-burst-access-ns = <6>;
gpmc,bus-turnaround-ns = <12>;
gpmc,cycle2cycle-delay-ns = <18>;
gpmc,wr-data-mux-bus-ns = <90>;
gpmc,wr-access-ns = <186>;
gpmc,access-ns = <144>;
gpmc,page-burst-access-ns = <24>;
gpmc,bus-turnaround-ns = <90>;
gpmc,cycle2cycle-delay-ns = <90>;
gpmc,cycle2cycle-samecsen;
gpmc,cycle2cycle-diffcsen;
vddvario-supply = <&vddvario>;

7
arch/arm/boot/dts/omap2.dtsi
View file

@ -71,13 +71,6 @@
interrupts = <58>;
};
mailbox: mailbox@48094000 {
compatible = "ti,omap2-mailbox";
ti,hwmods = "mailbox";
reg = <0x48094000 0x200>;
interrupts = <26>;
};
intc: interrupt-controller@1 {
compatible = "ti,omap2-intc";
interrupt-controller;

8
arch/arm/boot/dts/omap2420.dtsi
View file

@ -125,6 +125,14 @@
dma-names = "tx", "rx";
};
mailbox: mailbox@48094000 {
compatible = "ti,omap2-mailbox";
reg = <0x48094000 0x200>;
interrupts = <26>, <34>;
interrupt-names = "dsp", "iva";
ti,hwmods = "mailbox";
};
timer1: timer@48028000 {
compatible = "ti,omap2420-timer";
reg = <0x48028000 0x400>;

7
arch/arm/boot/dts/omap2430.dtsi
View file

@ -216,6 +216,13 @@
dma-names = "tx", "rx";
};
mailbox: mailbox@48094000 {
compatible = "ti,omap2-mailbox";
reg = <0x48094000 0x200>;
interrupts = <26>;
ti,hwmods = "mailbox";
};
timer1: timer@49018000 {
compatible = "ti,omap2420-timer";
reg = <0x49018000 0x400>;

66
arch/arm/boot/dts/omap3-cm-t3x30.dtsi
View file

@ -10,18 +10,6 @@
cpu0-supply = <&vcc>;
};
};
vddvario: regulator-vddvario {
compatible = "regulator-fixed";
regulator-name = "vddvario";
regulator-always-on;
};
vdd33a: regulator-vdd33a {
compatible = "regulator-fixed";
regulator-name = "vdd33a";
regulator-always-on;
};
};
&omap3_pmx_core {
@ -35,58 +23,34 @@
hsusb0_pins: pinmux_hsusb0_pins {
pinctrl-single,pins = <
OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* hsusb0_clk.hsusb0_clk */
OMAP3_CORE1_IOPAD(0x21a2, PIN_OUTPUT | MUX_MODE0) /* hsusb0_stp.hsusb0_stp */
OMAP3_CORE1_IOPAD(0x21a4, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_dir.hsusb0_dir */
OMAP3_CORE1_IOPAD(0x21a6, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_nxt.hsusb0_nxt */
OMAP3_CORE1_IOPAD(0x21a8, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data0.hsusb2_data0 */
OMAP3_CORE1_IOPAD(0x21aa, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data1.hsusb0_data1 */
OMAP3_CORE1_IOPAD(0x21ac, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data2.hsusb0_data2 */
OMAP3_CORE1_IOPAD(0x21ae, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data7.hsusb0_data3 */
OMAP3_CORE1_IOPAD(0x21b0, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data7.hsusb0_data4 */
OMAP3_CORE1_IOPAD(0x21b2, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data7.hsusb0_data5 */
OMAP3_CORE1_IOPAD(0x21b4, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data7.hsusb0_data6 */
OMAP3_CORE1_IOPAD(0x21b6, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data7.hsusb0_data7 */
OMAP3_CORE1_IOPAD(0x21a2, PIN_OUTPUT | MUX_MODE0) /* hsusb0_clk.hsusb0_clk */
OMAP3_CORE1_IOPAD(0x21a4, PIN_OUTPUT | MUX_MODE0) /* hsusb0_stp.hsusb0_stp */
OMAP3_CORE1_IOPAD(0x21a6, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_dir.hsusb0_dir */
OMAP3_CORE1_IOPAD(0x21a8, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_nxt.hsusb0_nxt */
OMAP3_CORE1_IOPAD(0x21aa, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data0.hsusb2_data0 */
OMAP3_CORE1_IOPAD(0x21ac, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data1.hsusb0_data1 */
OMAP3_CORE1_IOPAD(0x21ae, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data2.hsusb0_data2 */
OMAP3_CORE1_IOPAD(0x21b0, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data7.hsusb0_data3 */
OMAP3_CORE1_IOPAD(0x21b2, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data7.hsusb0_data4 */
OMAP3_CORE1_IOPAD(0x21b4, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data7.hsusb0_data5 */
OMAP3_CORE1_IOPAD(0x21b6, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data7.hsusb0_data6 */
OMAP3_CORE1_IOPAD(0x21b8, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data7.hsusb0_data7 */
>;
};
};
#include "omap-gpmc-smsc911x.dtsi"
&gpmc {
ranges = <5 0 0x2c000000 0x01000000>;
smsc1: ethernet@5,0 {
smsc1: ethernet@gpmc {
compatible = "smsc,lan9221", "smsc,lan9115";
pinctrl-names = "default";
pinctrl-0 = <&smsc1_pins>;
interrupt-parent = <&gpio6>;
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
reg = <5 0 0xff>;
bank-width = <2>;
gpmc,mux-add-data;
gpmc,cs-on-ns = <0>;
gpmc,cs-rd-off-ns = <186>;
gpmc,cs-wr-off-ns = <186>;
gpmc,adv-on-ns = <12>;
gpmc,adv-rd-off-ns = <48>;
gpmc,adv-wr-off-ns = <48>;
gpmc,oe-on-ns = <54>;
gpmc,oe-off-ns = <168>;
gpmc,we-on-ns = <54>;
gpmc,we-off-ns = <168>;
gpmc,rd-cycle-ns = <186>;
gpmc,wr-cycle-ns = <186>;
gpmc,access-ns = <114>;
gpmc,page-burst-access-ns = <6>;
gpmc,bus-turnaround-ns = <12>;
gpmc,cycle2cycle-delay-ns = <18>;
gpmc,wr-data-mux-bus-ns = <90>;
gpmc,wr-access-ns = <186>;
gpmc,cycle2cycle-samecsen;
gpmc,cycle2cycle-diffcsen;
vddvario-supply = <&vddvario>;
vdd33a-supply = <&vdd33a>;
reg-io-width = <4>;
smsc,save-mac-address;
};
};

2
arch/arm/boot/dts/omap3-igep.dtsi
View file

@ -107,7 +107,7 @@
>;
};
smsc911x_pins: pinmux_smsc911x_pins {
smsc9221_pins: pinmux_smsc9221_pins {
pinctrl-single,pins = <
0x1a2 (PIN_INPUT | MUX_MODE4) /* mcspi1_cs2.gpio_176 */
>;

4
arch/arm/boot/dts/omap3-igep0020.dts
View file

@ -10,7 +10,7 @@
*/
#include "omap3-igep.dtsi"
#include "omap-gpmc-smsc911x.dtsi"
#include "omap-gpmc-smsc9221.dtsi"
/ {
model = "IGEPv2 (TI OMAP AM/DM37x)";
@ -248,7 +248,7 @@
ethernet@gpmc {
pinctrl-names = "default";
pinctrl-0 = <&smsc911x_pins>;
pinctrl-0 = <&smsc9221_pins>;
reg = <5 0 0xff>;
interrupt-parent = <&gpio6>;
interrupts = <16 IRQ_TYPE_LEVEL_LOW>;

37
arch/arm/boot/dts/omap3-sb-t35.dtsi
View file

@ -2,20 +2,6 @@
* Common support for CompuLab SB-T35 used on SBC-T3530, SBC-T3517 and SBC-T3730
*/
/ {
vddvario_sb_t35: regulator-vddvario-sb-t35 {
compatible = "regulator-fixed";
regulator-name = "vddvario";
regulator-always-on;
};
vdd33a_sb_t35: regulator-vdd33a-sb-t35 {
compatible = "regulator-fixed";
regulator-name = "vdd33a";
regulator-always-on;
};
};
&omap3_pmx_core {
smsc2_pins: pinmux_smsc2_pins {
pinctrl-single,pins = <
@ -37,11 +23,10 @@
reg = <4 0 0xff>;
bank-width = <2>;
gpmc,mux-add-data;
gpmc,cs-on-ns = <0>;
gpmc,cs-rd-off-ns = <186>;
gpmc,cs-wr-off-ns = <186>;
gpmc,adv-on-ns = <12>;
gpmc,adv-rd-off-ns = <48>;
gpmc,cs-on-ns = <1>;
gpmc,cs-rd-off-ns = <180>;
gpmc,cs-wr-off-ns = <180>;
gpmc,adv-rd-off-ns = <18>;
gpmc,adv-wr-off-ns = <48>;
gpmc,oe-on-ns = <54>;
gpmc,oe-off-ns = <168>;
@ -49,16 +34,14 @@
gpmc,we-off-ns = <168>;
gpmc,rd-cycle-ns = <186>;
gpmc,wr-cycle-ns = <186>;
gpmc,access-ns = <114>;
gpmc,page-burst-access-ns = <6>;
gpmc,bus-turnaround-ns = <12>;
gpmc,cycle2cycle-delay-ns = <18>;
gpmc,wr-data-mux-bus-ns = <90>;
gpmc,wr-access-ns = <186>;
gpmc,access-ns = <144>;
gpmc,page-burst-access-ns = <24>;
gpmc,bus-turnaround-ns = <90>;
gpmc,cycle2cycle-delay-ns = <90>;
gpmc,cycle2cycle-samecsen;
gpmc,cycle2cycle-diffcsen;
vddvario-supply = <&vddvario_sb_t35>;
vdd33a-supply = <&vdd33a_sb_t35>;
vddvario-supply = <&vddvario>;
vdd33a-supply = <&vdd33a>;
reg-io-width = <4>;
smsc,save-mac-address;
};

13
arch/arm/boot/dts/omap3-sbc-t3517.dts
View file

@ -8,6 +8,19 @@
/ {
model = "CompuLab SBC-T3517 with CM-T3517";
compatible = "compulab,omap3-sbc-t3517", "compulab,omap3-cm-t3517", "ti,am3517", "ti,omap3";
/* Only one GPMC smsc9220 on SBC-T3517, CM-T3517 uses am35x Ethernet */
vddvario: regulator-vddvario-sb-t35 {
compatible = "regulator-fixed";
regulator-name = "vddvario";
regulator-always-on;
};
vdd33a: regulator-vdd33a-sb-t35 {
compatible = "regulator-fixed";
regulator-name = "vdd33a";
regulator-always-on;
};
};
&omap3_pmx_core {

2
arch/arm/boot/dts/omap3.dtsi
View file

@ -61,7 +61,7 @@
ti,hwmods = "mpu";
};
iva {
iva: iva {
compatible = "ti,iva2.2";
ti,hwmods = "iva";

7
arch/arm/boot/dts/omap5.dtsi
View file

@ -630,6 +630,13 @@
status = "disabled";
};
mailbox: mailbox@4a0f4000 {
compatible = "ti,omap4-mailbox";
reg = <0x4a0f4000 0x200>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mailbox";
};
timer1: timer@4ae18000 {
compatible = "ti,omap5430-timer";
reg = <0x4ae18000 0x80>;

2
arch/arm/boot/dts/sama5d3.dtsi
View file

@ -13,7 +13,7 @@
#include <dt-bindings/pinctrl/at91.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clk/at91.h>
#include <dt-bindings/clock/at91.h>
/ {
model = "Atmel SAMA5D3 family SoC";

2
arch/arm/boot/dts/sama5d3_mci2.dtsi
View file

@ -9,7 +9,7 @@
#include <dt-bindings/pinctrl/at91.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/clk/at91.h>
#include <dt-bindings/clock/at91.h>
/ {
ahb {

2
arch/arm/boot/dts/sama5d3_tcb1.dtsi
View file

@ -9,7 +9,7 @@
#include <dt-bindings/pinctrl/at91.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/clk/at91.h>
#include <dt-bindings/clock/at91.h>
/ {
aliases {

2
arch/arm/boot/dts/sama5d3_uart.dtsi
View file

@ -9,7 +9,7 @@
#include <dt-bindings/pinctrl/at91.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/clk/at91.h>
#include <dt-bindings/clock/at91.h>
/ {
aliases {

1
arch/arm/boot/dts/ste-ccu8540.dts
View file

@ -18,6 +18,7 @@
compatible = "st-ericsson,ccu8540", "st-ericsson,u8540";
memory@0 {
device_type = "memory";
reg = <0x20000000 0x1f000000>, <0xc0000000 0x3f000000>;
};

14
arch/arm/boot/dts/sun7i-a20.dtsi
View file

@ -87,7 +87,7 @@
pll4: clk@01c20018 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-pll1-clk";
compatible = "allwinner,sun7i-a20-pll4-clk";
reg = <0x01c20018 0x4>;
clocks = <&osc24M>;
clock-output-names = "pll4";
@ -109,6 +109,14 @@
clock-output-names = "pll6_sata", "pll6_other", "pll6";
};
pll8: clk@01c20040 {
#clock-cells = <0>;
compatible = "allwinner,sun7i-a20-pll4-clk";
reg = <0x01c20040 0x4>;
clocks = <&osc24M>;
clock-output-names = "pll8";
};
cpu: cpu@01c20054 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-cpu-clk";
@ -805,9 +813,9 @@
status = "disabled";
};
i2c4: i2c@01c2bc00 {
i2c4: i2c@01c2c000 {
compatible = "allwinner,sun4i-i2c";
reg = <0x01c2bc00 0x400>;
reg = <0x01c2c000 0x400>;
interrupts = <0 89 4>;
clocks = <&apb1_gates 15>;
clock-frequency = <100000>;

10
arch/arm/common/bL_switcher.c
View file

@ -433,8 +433,12 @@ static void bL_switcher_restore_cpus(void)
{
int i;
for_each_cpu(i, &bL_switcher_removed_logical_cpus)
cpu_up(i);
for_each_cpu(i, &bL_switcher_removed_logical_cpus) {
struct device *cpu_dev = get_cpu_device(i);
int ret = device_online(cpu_dev);
if (ret)
dev_err(cpu_dev, "switcher: unable to restore CPU\n");
}
}
static int bL_switcher_halve_cpus(void)
@ -521,7 +525,7 @@ static int bL_switcher_halve_cpus(void)
continue;
}
ret = cpu_down(i);
ret = device_offline(get_cpu_device(i));
if (ret) {
bL_switcher_restore_cpus();
return ret;

48
arch/arm/common/edma.c
View file

@ -1423,55 +1423,38 @@ EXPORT_SYMBOL(edma_clear_event);
#if IS_ENABLED(CONFIG_OF) && IS_ENABLED(CONFIG_DMADEVICES)
static int edma_of_read_u32_to_s16_array(const struct device_node *np,
const char *propname, s16 *out_values,
size_t sz)
static int edma_xbar_event_map(struct device *dev, struct device_node *node,
struct edma_soc_info *pdata, size_t sz)
{
int ret;
ret = of_property_read_u16_array(np, propname, out_values, sz);
if (ret)
return ret;
/* Terminate it */
*out_values++ = -1;
*out_values++ = -1;
return 0;
}
static int edma_xbar_event_map(struct device *dev,
struct device_node *node,
struct edma_soc_info *pdata, int len)
{
int ret, i;
const char pname[] = "ti,edma-xbar-event-map";
struct resource res;
void __iomem *xbar;
const s16 (*xbar_chans)[2];
s16 (*xbar_chans)[2];
size_t nelm = sz / sizeof(s16);
u32 shift, offset, mux;
int ret, i;
xbar_chans = devm_kzalloc(dev,
len/sizeof(s16) + 2*sizeof(s16),
GFP_KERNEL);
xbar_chans = devm_kzalloc(dev, (nelm + 2) * sizeof(s16), GFP_KERNEL);
if (!xbar_chans)
return -ENOMEM;
ret = of_address_to_resource(node, 1, &res);
if (ret)
return -EIO;
return -ENOMEM;
xbar = devm_ioremap(dev, res.start, resource_size(&res));
if (!xbar)
return -ENOMEM;
ret = edma_of_read_u32_to_s16_array(node,
"ti,edma-xbar-event-map",
(s16 *)xbar_chans,
len/sizeof(u32));
ret = of_property_read_u16_array(node, pname, (u16 *)xbar_chans, nelm);
if (ret)
return -EIO;
for (i = 0; xbar_chans[i][0] != -1; i++) {
/* Invalidate last entry for the other user of this mess */
nelm >>= 1;
xbar_chans[nelm][0] = xbar_chans[nelm][1] = -1;
for (i = 0; i < nelm; i++) {
shift = (xbar_chans[i][1] & 0x03) << 3;
offset = xbar_chans[i][1] & 0xfffffffc;
mux = readl(xbar + offset);
@ -1480,8 +1463,7 @@ static int edma_xbar_event_map(struct device *dev,
writel(mux, (xbar + offset));
}
pdata->xbar_chans = xbar_chans;
pdata->xbar_chans = (const s16 (*)[2]) xbar_chans;
return 0;
}

1
arch/arm/configs/exynos_defconfig
View file

@ -65,6 +65,7 @@ CONFIG_TCG_TIS_I2C_INFINEON=y
CONFIG_I2C=y
CONFIG_I2C_MUX=y
CONFIG_I2C_ARB_GPIO_CHALLENGE=y
CONFIG_I2C_EXYNOS5=y
CONFIG_I2C_S3C2410=y
CONFIG_DEBUG_GPIO=y
# CONFIG_HWMON is not set

2
arch/arm/configs/sunxi_defconfig
View file

@ -37,7 +37,7 @@ CONFIG_SUN4I_EMAC=y
# CONFIG_NET_VENDOR_NATSEMI is not set
# CONFIG_NET_VENDOR_SEEQ is not set
# CONFIG_NET_VENDOR_SMSC is not set
# CONFIG_NET_VENDOR_STMICRO is not set
CONFIG_STMMAC_ETH=y
# CONFIG_NET_VENDOR_WIZNET is not set
# CONFIG_WLAN is not set
CONFIG_SERIAL_8250=y

2
arch/arm/include/asm/trusted_foundations.h
View file

@ -54,7 +54,9 @@ static inline void register_trusted_foundations(
*/
pr_err("No support for Trusted Foundations, continuing in degraded mode.\n");
pr_err("Secondary processors as well as CPU PM will be disabled.\n");
#if IS_ENABLED(CONFIG_SMP)
setup_max_cpus = 0;
#endif
cpu_idle_poll_ctrl(true);
}

3
arch/arm/include/asm/uaccess.h
View file

@ -171,8 +171,9 @@ extern int __put_user_8(void *, unsigned long long);
#define __put_user_check(x,p) \
({ \
unsigned long __limit = current_thread_info()->addr_limit - 1; \
const typeof(*(p)) __user *__tmp_p = (p); \
register const typeof(*(p)) __r2 asm("r2") = (x); \
register const typeof(*(p)) __user *__p asm("r0") = (p);\
register const typeof(*(p)) __user *__p asm("r0") = __tmp_p; \
register unsigned long __l asm("r1") = __limit; \
register int __e asm("r0"); \
switch (sizeof(*(__p))) { \

1
arch/arm/include/asm/xen/page.h
View file

@ -77,7 +77,6 @@ static inline xpaddr_t machine_to_phys(xmaddr_t machine)
}
/* VIRT <-> MACHINE conversion */
#define virt_to_machine(v) (phys_to_machine(XPADDR(__pa(v))))
#define virt_to_pfn(v) (PFN_DOWN(__pa(v)))
#define virt_to_mfn(v) (pfn_to_mfn(virt_to_pfn(v)))
#define mfn_to_virt(m) (__va(mfn_to_pfn(m) << PAGE_SHIFT))

4
arch/arm/kernel/entry-header.S
View file

@ -132,6 +132,10 @@
orrne r5, V7M_xPSR_FRAMEPTRALIGN
biceq r5, V7M_xPSR_FRAMEPTRALIGN
@ ensure bit 0 is cleared in the PC, otherwise behaviour is
@ unpredictable
bic r4, #1
@ write basic exception frame
stmdb r2!, {r1, r3-r5}
ldmia sp, {r1, r3-r5}

2
arch/arm/kernel/unwind.c
View file

@ -285,7 +285,7 @@ static int unwind_exec_pop_r4_to_rN(struct unwind_ctrl_block *ctrl,
if (unwind_pop_register(ctrl, &vsp, reg))
return -URC_FAILURE;
if (insn & 0x80)
if (insn & 0x8)
if (unwind_pop_register(ctrl, &vsp, 14))
return -URC_FAILURE;

8
arch/arm/mach-at91/at91sam9260_devices.c
View file

@ -1308,19 +1308,19 @@ static struct platform_device at91_adc_device = {
static struct at91_adc_trigger at91_adc_triggers[] = {
[0] = {
.name = "timer-counter-0",
.value = AT91_ADC_TRGSEL_TC0 | AT91_ADC_TRGEN,
.value = 0x1,
},
[1] = {
.name = "timer-counter-1",
.value = AT91_ADC_TRGSEL_TC1 | AT91_ADC_TRGEN,
.value = 0x3,
},
[2] = {
.name = "timer-counter-2",
.value = AT91_ADC_TRGSEL_TC2 | AT91_ADC_TRGEN,
.value = 0x5,
},
[3] = {
.name = "external",
.value = AT91_ADC_TRGSEL_EXTERNAL | AT91_ADC_TRGEN,
.value = 0xd,
.is_external = true,
},
};

15
arch/arm/mach-exynos/firmware.c
View file

@ -18,6 +18,8 @@
#include <mach/map.h>
#include <plat/cpu.h>
#include "smc.h"
static int exynos_do_idle(void)
@ -28,13 +30,24 @@ static int exynos_do_idle(void)
static int exynos_cpu_boot(int cpu)
{
/*
* The second parameter of SMC_CMD_CPU1BOOT command means CPU id.
* But, Exynos4212 has only one secondary CPU so second parameter
* isn't used for informing secure firmware about CPU id.
*/
if (soc_is_exynos4212())
cpu = 0;
exynos_smc(SMC_CMD_CPU1BOOT, cpu, 0, 0);
return 0;
}
static int exynos_set_cpu_boot_addr(int cpu, unsigned long boot_addr)
{
void __iomem *boot_reg = S5P_VA_SYSRAM_NS + 0x1c + 4*cpu;
void __iomem *boot_reg = S5P_VA_SYSRAM_NS + 0x1c;
if (!soc_is_exynos4212())
boot_reg += 4*cpu;
__raw_writel(boot_addr, boot_reg);
return 0;

2
arch/arm/mach-imx/devices/platform-ipu-core.c
View file

@ -77,7 +77,7 @@ struct platform_device *__init imx_alloc_mx3_camera(
pdev = platform_device_alloc("mx3-camera", 0);
if (!pdev)
goto err;
return ERR_PTR(-ENOMEM);
pdev->dev.dma_mask = kmalloc(sizeof(*pdev->dev.dma_mask), GFP_KERNEL);
if (!pdev->dev.dma_mask)

13
arch/arm/mach-mvebu/mvebu-soc-id.c
View file

@ -108,7 +108,18 @@ static int __init mvebu_soc_id_init(void)
iounmap(pci_base);
res_ioremap:
clk_disable_unprepare(clk);
/*
* If the PCIe unit is actually enabled and we have PCI
* support in the kernel, we intentionally do not release the
* reference to the clock. We want to keep it running since
* the bootloader does some PCIe link configuration that the
* kernel is for now unable to do, and gating the clock would
* make us loose this precious configuration.
*/
if (!of_device_is_available(child) || !IS_ENABLED(CONFIG_PCI_MVEBU)) {
clk_disable_unprepare(clk);
clk_put(clk);
}
clk_err:
of_node_put(child);

2
arch/arm/mach-omap2/board-flash.c
View file

@ -142,7 +142,7 @@ __init board_nand_init(struct mtd_partition *nand_parts, u8 nr_parts, u8 cs,
board_nand_data.nr_parts = nr_parts;
board_nand_data.devsize = nand_type;
board_nand_data.ecc_opt = OMAP_ECC_BCH8_CODE_HW;
board_nand_data.ecc_opt = OMAP_ECC_HAM1_CODE_HW;
gpmc_nand_init(&board_nand_data, gpmc_t);
}
#endif /* CONFIG_MTD_NAND_OMAP2 || CONFIG_MTD_NAND_OMAP2_MODULE */

3
arch/arm/mach-omap2/cclock3xxx_data.c
View file

@ -456,7 +456,8 @@ static struct clk_hw_omap dpll4_m5x2_ck_hw = {
.clkdm_name = "dpll4_clkdm",
};
DEFINE_STRUCT_CLK(dpll4_m5x2_ck, dpll4_m5x2_ck_parent_names, dpll4_m5x2_ck_ops);
DEFINE_STRUCT_CLK_FLAGS(dpll4_m5x2_ck, dpll4_m5x2_ck_parent_names,
dpll4_m5x2_ck_ops, CLK_SET_RATE_PARENT);
static struct clk dpll4_m5x2_ck_3630 = {
.name = "dpll4_m5x2_ck",

25
arch/arm/mach-omap2/cpuidle44xx.c
View file

@ -14,6 +14,7 @@
#include <linux/cpuidle.h>
#include <linux/cpu_pm.h>
#include <linux/export.h>
#include <linux/clockchips.h>
#include <asm/cpuidle.h>
#include <asm/proc-fns.h>
@ -83,6 +84,7 @@ static int omap_enter_idle_coupled(struct cpuidle_device *dev,
{
struct idle_statedata *cx = state_ptr + index;
u32 mpuss_can_lose_context = 0;
int cpu_id = smp_processor_id();
/*
* CPU0 has to wait and stay ON until CPU1 is OFF state.
@ -110,6 +112,8 @@ static int omap_enter_idle_coupled(struct cpuidle_device *dev,
mpuss_can_lose_context = (cx->mpu_state == PWRDM_POWER_RET) &&
(cx->mpu_logic_state == PWRDM_POWER_OFF);
clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu_id);
/*
* Call idle CPU PM enter notifier chain so that
* VFP and per CPU interrupt context is saved.
@ -165,6 +169,8 @@ static int omap_enter_idle_coupled(struct cpuidle_device *dev,
if (dev->cpu == 0 && mpuss_can_lose_context)
cpu_cluster_pm_exit();
clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu_id);
fail:
cpuidle_coupled_parallel_barrier(dev, &abort_barrier);
cpu_done[dev->cpu] = false;
@ -172,6 +178,16 @@ fail:
return index;
}
/*
* For each cpu, setup the broadcast timer because local timers
* stops for the states above C1.
*/
static void omap_setup_broadcast_timer(void *arg)
{
int cpu = smp_processor_id();
clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ON, &cpu);
}
static struct cpuidle_driver omap4_idle_driver = {
.name = "omap4_idle",
.owner = THIS_MODULE,
@ -189,8 +205,7 @@ static struct cpuidle_driver omap4_idle_driver = {
/* C2 - CPU0 OFF + CPU1 OFF + MPU CSWR */
.exit_latency = 328 + 440,
.target_residency = 960,
.flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_COUPLED |
CPUIDLE_FLAG_TIMER_STOP,
.flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_COUPLED,
.enter = omap_enter_idle_coupled,
.name = "C2",
.desc = "CPUx OFF, MPUSS CSWR",
@ -199,8 +214,7 @@ static struct cpuidle_driver omap4_idle_driver = {
/* C3 - CPU0 OFF + CPU1 OFF + MPU OSWR */
.exit_latency = 460 + 518,
.target_residency = 1100,
.flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_COUPLED |
CPUIDLE_FLAG_TIMER_STOP,
.flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_COUPLED,
.enter = omap_enter_idle_coupled,
.name = "C3",
.desc = "CPUx OFF, MPUSS OSWR",
@ -231,5 +245,8 @@ int __init omap4_idle_init(void)
if (!cpu_clkdm[0] || !cpu_clkdm[1])
return -ENODEV;
/* Configure the broadcast timer on each cpu */
on_each_cpu(omap_setup_broadcast_timer, NULL, 1);
return cpuidle_register(&omap4_idle_driver, cpu_online_mask);
}

8
arch/arm/mach-omap2/omap-headsmp.S
View file

@ -1,7 +1,7 @@
/*
* Secondary CPU startup routine source file.
*
* Copyright (C) 2009 Texas Instruments, Inc.
* Copyright (C) 2009-2014 Texas Instruments, Inc.
*
* Author:
* Santosh Shilimkar <santosh.shilimkar@ti.com>
@ -28,9 +28,13 @@
* code. This routine also provides a holding flag into which
* secondary core is held until we're ready for it to initialise.
* The primary core will update this flag using a hardware
+ * register AuxCoreBoot0.
* register AuxCoreBoot0.
*/
ENTRY(omap5_secondary_startup)
.arm
THUMB( adr r9, BSYM(wait) ) @ CPU may be entered in ARM mode.
THUMB( bx r9 ) @ If this is a Thumb-2 kernel,
THUMB( .thumb ) @ switch to Thumb now.
wait: ldr r2, =AUX_CORE_BOOT0_PA @ read from AuxCoreBoot0
ldr r0, [r2]
mov r0, r0, lsr #5

2
arch/arm/mach-omap2/omap_hwmod_54xx_data.c
View file

@ -895,7 +895,7 @@ static struct omap_hwmod omap54xx_mcpdm_hwmod = {
* current exception.
*/
.flags = HWMOD_EXT_OPT_MAIN_CLK,
.flags = HWMOD_EXT_OPT_MAIN_CLK | HWMOD_SWSUP_SIDLE,
.main_clk = "pad_clks_ck",
.prcm = {
.omap4 = {

2
arch/arm/mach-orion5x/common.h
View file

@ -21,7 +21,7 @@ struct mv_sata_platform_data;
#define ORION_MBUS_DEVBUS_BOOT_ATTR 0x0f
#define ORION_MBUS_DEVBUS_TARGET(cs) 0x01
#define ORION_MBUS_DEVBUS_ATTR(cs) (~(1 << cs))
#define ORION_MBUS_SRAM_TARGET 0x00
#define ORION_MBUS_SRAM_TARGET 0x09
#define ORION_MBUS_SRAM_ATTR 0x00
/*

8
arch/arm/mm/proc-v7m.S
View file

@ -123,6 +123,11 @@ __v7m_setup:
mov pc, lr
ENDPROC(__v7m_setup)
.align 2
__v7m_setup_stack:
.space 4 * 8 @ 8 registers
__v7m_setup_stack_top:
define_processor_functions v7m, dabort=nommu_early_abort, pabort=legacy_pabort, nommu=1
.section ".rodata"
@ -152,6 +157,3 @@ __v7m_proc_info:
.long nop_cache_fns @ proc_info_list.cache
.size __v7m_proc_info, . - __v7m_proc_info
__v7m_setup_stack:
.space 4 * 8 @ 8 registers
__v7m_setup_stack_top:

10
arch/arm/plat-omap/dma.c
View file

@ -70,6 +70,7 @@ static u32 errata;
static struct omap_dma_global_context_registers {
u32 dma_irqenable_l0;
u32 dma_irqenable_l1;
u32 dma_ocp_sysconfig;
u32 dma_gcr;
} omap_dma_global_context;
@ -1973,10 +1974,17 @@ static struct irqaction omap24xx_dma_irq;
/*----------------------------------------------------------------------------*/
/*
* Note that we are currently using only IRQENABLE_L0 and L1.
* As the DSP may be using IRQENABLE_L2 and L3, let's not
* touch those for now.
*/
void omap_dma_global_context_save(void)
{
omap_dma_global_context.dma_irqenable_l0 =
p->dma_read(IRQENABLE_L0, 0);
omap_dma_global_context.dma_irqenable_l1 =
p->dma_read(IRQENABLE_L1, 0);
omap_dma_global_context.dma_ocp_sysconfig =
p->dma_read(OCP_SYSCONFIG, 0);
omap_dma_global_context.dma_gcr = p->dma_read(GCR, 0);
@ -1991,6 +1999,8 @@ void omap_dma_global_context_restore(void)
OCP_SYSCONFIG, 0);
p->dma_write(omap_dma_global_context.dma_irqenable_l0,
IRQENABLE_L0, 0);
p->dma_write(omap_dma_global_context.dma_irqenable_l1,
IRQENABLE_L1, 0);
if (IS_DMA_ERRATA(DMA_ROMCODE_BUG))
p->dma_write(0x3 , IRQSTATUS_L0, 0);

1
arch/arm64/include/asm/memory.h
View file

@ -138,6 +138,7 @@ static inline void *phys_to_virt(phys_addr_t x)
#define __pa(x) __virt_to_phys((unsigned long)(x))
#define __va(x) ((void *)__phys_to_virt((phys_addr_t)(x)))
#define pfn_to_kaddr(pfn) __va((pfn) << PAGE_SHIFT)
#define virt_to_pfn(x) __phys_to_pfn(__virt_to_phys(x))
/*
* virt_to_page(k) convert a _valid_ virtual address to struct page *

2
arch/arm64/include/asm/pgtable.h
View file

@ -266,7 +266,7 @@ static inline pmd_t pte_pmd(pte_t pte)
#define pmd_page(pmd) pfn_to_page(__phys_to_pfn(pmd_val(pmd) & PHYS_MASK))
#define set_pmd_at(mm, addr, pmdp, pmd) set_pmd(pmdp, pmd)
#define set_pmd_at(mm, addr, pmdp, pmd) set_pte_at(mm, addr, (pte_t *)pmdp, pmd_pte(pmd))
static inline int has_transparent_hugepage(void)
{

10
arch/arm64/kernel/irq.c
View file

@ -97,11 +97,15 @@ static bool migrate_one_irq(struct irq_desc *desc)
if (irqd_is_per_cpu(d) || !cpumask_test_cpu(smp_processor_id(), affinity))
return false;
if (cpumask_any_and(affinity, cpu_online_mask) >= nr_cpu_ids) {
affinity = cpu_online_mask;
if (cpumask_any_and(affinity, cpu_online_mask) >= nr_cpu_ids)
ret = true;
}
/*
* when using forced irq_set_affinity we must ensure that the cpu
* being offlined is not present in the affinity mask, it may be
* selected as the target CPU otherwise
*/
affinity = cpu_online_mask;
c = irq_data_get_irq_chip(d);
if (!c->irq_set_affinity)
pr_debug("IRQ%u: unable to set affinity\n", d->irq);

4
arch/arm64/mm/hugetlbpage.c
View file

@ -51,7 +51,11 @@ int pmd_huge(pmd_t pmd)
int pud_huge(pud_t pud)
{
#ifndef __PAGETABLE_PMD_FOLDED
return !(pud_val(pud) & PUD_TABLE_BIT);
#else
return 0;
#endif
}
int pmd_huge_support(void)

2
arch/ia64/include/asm/unistd.h
View file

@ -11,7 +11,7 @@
#define NR_syscalls 314 /* length of syscall table */
#define NR_syscalls 315 /* length of syscall table */
/*
* The following defines stop scripts/checksyscalls.sh from complaining about

1
arch/ia64/include/uapi/asm/unistd.h
View file

@ -327,5 +327,6 @@
#define __NR_finit_module 1335
#define __NR_sched_setattr 1336
#define __NR_sched_getattr 1337
#define __NR_renameat2 1338
#endif /* _UAPI_ASM_IA64_UNISTD_H */

1
arch/ia64/kernel/entry.S
View file

@ -1775,6 +1775,7 @@ sys_call_table:
data8 sys_finit_module // 1335
data8 sys_sched_setattr
data8 sys_sched_getattr
data8 sys_renameat2
.org sys_call_table + 8*NR_syscalls // guard against failures to increase NR_syscalls
#endif /* __IA64_ASM_PARAVIRTUALIZED_NATIVE */

2
arch/m68k/include/asm/unistd.h
View file

@ -4,7 +4,7 @@
#include <uapi/asm/unistd.h>
#define NR_syscalls 351
#define NR_syscalls 352
#define __ARCH_WANT_OLD_READDIR
#define __ARCH_WANT_OLD_STAT

1
arch/m68k/include/uapi/asm/unistd.h
View file

@ -356,5 +356,6 @@
#define __NR_finit_module 348
#define __NR_sched_setattr 349
#define __NR_sched_getattr 350
#define __NR_renameat2 351
#endif /* _UAPI_ASM_M68K_UNISTD_H_ */

1
arch/m68k/kernel/syscalltable.S
View file

@ -371,4 +371,5 @@ ENTRY(sys_call_table)
.long sys_finit_module
.long sys_sched_setattr
.long sys_sched_getattr /* 350 */
.long sys_renameat2

3
arch/metag/include/asm/barrier.h
View file

@ -15,6 +15,7 @@ static inline void wr_fence(void)
volatile int *flushptr = (volatile int *) LINSYSEVENT_WR_FENCE;
barrier();
*flushptr = 0;
barrier();
}
#else /* CONFIG_METAG_META21 */
@ -35,6 +36,7 @@ static inline void wr_fence(void)
*flushptr = 0;
*flushptr = 0;
*flushptr = 0;
barrier();
}
#endif /* !CONFIG_METAG_META21 */
@ -68,6 +70,7 @@ static inline void fence(void)
volatile int *flushptr = (volatile int *) LINSYSEVENT_WR_ATOMIC_UNLOCK;
barrier();
*flushptr = 0;
barrier();
}
#define smp_mb() fence()
#define smp_rmb() fence()

2
arch/metag/include/asm/processor.h
View file

@ -22,6 +22,8 @@
/* Add an extra page of padding at the top of the stack for the guard page. */
#define STACK_TOP (TASK_SIZE - PAGE_SIZE)
#define STACK_TOP_MAX STACK_TOP
/* Maximum virtual space for stack */
#define STACK_SIZE_MAX (CONFIG_MAX_STACK_SIZE_MB*1024*1024)
/* This decides where the kernel will search for a free chunk of vm
* space during mmap's.

2
arch/metag/include/uapi/asm/Kbuild
View file

@ -4,11 +4,11 @@ include include/uapi/asm-generic/Kbuild.asm
header-y += byteorder.h
header-y += ech.h
header-y += ptrace.h
header-y += resource.h
header-y += sigcontext.h
header-y += siginfo.h
header-y += swab.h
header-y += unistd.h
generic-y += mman.h
generic-y += resource.h
generic-y += setup.h

7
arch/metag/include/uapi/asm/resource.h
View file

@ -1,7 +0,0 @@
#ifndef _UAPI_METAG_RESOURCE_H
#define _UAPI_METAG_RESOURCE_H
#define _STK_LIM_MAX (1 << 28)
#include <asm-generic/resource.h>
#endif /* _UAPI_METAG_RESOURCE_H */

1
arch/mips/dec/ecc-berr.c
View file

@ -21,6 +21,7 @@
#include <asm/addrspace.h>
#include <asm/bootinfo.h>
#include <asm/cpu.h>
#include <asm/cpu-type.h>
#include <asm/irq_regs.h>
#include <asm/processor.h>
#include <asm/ptrace.h>

1
arch/mips/dec/kn02xa-berr.c
View file

@ -19,6 +19,7 @@
#include <linux/types.h>
#include <asm/addrspace.h>
#include <asm/cpu-type.h>
#include <asm/irq_regs.h>
#include <asm/ptrace.h>
#include <asm/traps.h>

1
arch/mips/dec/prom/Makefile
View file

@ -6,4 +6,3 @@
lib-y += init.o memory.o cmdline.o identify.o console.o
lib-$(CONFIG_32BIT) += locore.o
lib-$(CONFIG_64BIT) += call_o32.o

89
arch/mips/dec/prom/call_o32.S
View file

@ -1,89 +0,0 @@
/*
* O32 interface for the 64 (or N32) ABI.
*
* Copyright (C) 2002 Maciej W. Rozycki
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*/
#include <asm/asm.h>
#include <asm/regdef.h>
/* Maximum number of arguments supported. Must be even! */
#define O32_ARGC 32
/* Number of static registers we save. */
#define O32_STATC 11
/* Frame size for both of the above. */
#define O32_FRAMESZ (4 * O32_ARGC + SZREG * O32_STATC)
.text
/*
* O32 function call dispatcher, for interfacing 32-bit ROM routines.
*
* The standard 64 (N32) calling sequence is supported, with a0
* holding a function pointer, a1-a7 -- its first seven arguments
* and the stack -- remaining ones (up to O32_ARGC, including a1-a7).
* Static registers, gp and fp are preserved, v0 holds a result.
* This code relies on the called o32 function for sp and ra
* restoration and thus both this dispatcher and the current stack
* have to be placed in a KSEGx (or KUSEG) address space. Any
* pointers passed have to point to addresses within one of these
* spaces as well.
*/
NESTED(call_o32, O32_FRAMESZ, ra)
REG_SUBU sp,O32_FRAMESZ
REG_S ra,O32_FRAMESZ-1*SZREG(sp)
REG_S fp,O32_FRAMESZ-2*SZREG(sp)
REG_S gp,O32_FRAMESZ-3*SZREG(sp)
REG_S s7,O32_FRAMESZ-4*SZREG(sp)
REG_S s6,O32_FRAMESZ-5*SZREG(sp)
REG_S s5,O32_FRAMESZ-6*SZREG(sp)
REG_S s4,O32_FRAMESZ-7*SZREG(sp)
REG_S s3,O32_FRAMESZ-8*SZREG(sp)
REG_S s2,O32_FRAMESZ-9*SZREG(sp)
REG_S s1,O32_FRAMESZ-10*SZREG(sp)
REG_S s0,O32_FRAMESZ-11*SZREG(sp)
move jp,a0
sll a0,a1,zero
sll a1,a2,zero
sll a2,a3,zero
sll a3,a4,zero
sw a5,0x10(sp)
sw a6,0x14(sp)
sw a7,0x18(sp)
PTR_LA t0,O32_FRAMESZ(sp)
PTR_LA t1,0x1c(sp)
li t2,O32_ARGC-7
1:
lw t3,(t0)
REG_ADDU t0,SZREG
sw t3,(t1)
REG_SUBU t2,1
REG_ADDU t1,4
bnez t2,1b
jalr jp
REG_L s0,O32_FRAMESZ-11*SZREG(sp)
REG_L s1,O32_FRAMESZ-10*SZREG(sp)
REG_L s2,O32_FRAMESZ-9*SZREG(sp)
REG_L s3,O32_FRAMESZ-8*SZREG(sp)
REG_L s4,O32_FRAMESZ-7*SZREG(sp)
REG_L s5,O32_FRAMESZ-6*SZREG(sp)
REG_L s6,O32_FRAMESZ-5*SZREG(sp)
REG_L s7,O32_FRAMESZ-4*SZREG(sp)
REG_L gp,O32_FRAMESZ-3*SZREG(sp)
REG_L fp,O32_FRAMESZ-2*SZREG(sp)
REG_L ra,O32_FRAMESZ-1*SZREG(sp)
REG_ADDU sp,O32_FRAMESZ
jr ra
END(call_o32)

57
arch/mips/fw/lib/call_o32.S
View file

@ -1,7 +1,7 @@
/*
* O32 interface for the 64 (or N32) ABI.
*
* Copyright (C) 2002 Maciej W. Rozycki
* Copyright (C) 2002, 2014 Maciej W. Rozycki
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
@ -12,28 +12,37 @@
#include <asm/asm.h>
#include <asm/regdef.h>
/* O32 register size. */
#define O32_SZREG 4
/* Maximum number of arguments supported. Must be even! */
#define O32_ARGC 32
/* Number of static registers we save. */
/* Number of static registers we save. */
#define O32_STATC 11
/* Frame size for static register */
#define O32_FRAMESZ (SZREG * O32_STATC)
/* Frame size on new stack */
#define O32_FRAMESZ_NEW (SZREG + 4 * O32_ARGC)
/* Argument area frame size. */
#define O32_ARGSZ (O32_SZREG * O32_ARGC)
/* Static register save area frame size. */
#define O32_STATSZ (SZREG * O32_STATC)
/* Stack pointer register save area frame size. */
#define O32_SPSZ SZREG
/* Combined area frame size. */
#define O32_FRAMESZ (O32_ARGSZ + O32_SPSZ + O32_STATSZ)
/* Switched stack frame size. */
#define O32_NFRAMESZ (O32_ARGSZ + O32_SPSZ)
.text
/*
* O32 function call dispatcher, for interfacing 32-bit ROM routines.
*
* The standard 64 (N32) calling sequence is supported, with a0
* holding a function pointer, a1 a new stack pointer, a2-a7 -- its
* first six arguments and the stack -- remaining ones (up to O32_ARGC,
* including a2-a7). Static registers, gp and fp are preserved, v0 holds
* a result. This code relies on the called o32 function for sp and ra
* restoration and this dispatcher has to be placed in a KSEGx (or KUSEG)
* address space. Any pointers passed have to point to addresses within
* one of these spaces as well.
* The standard 64 (N32) calling sequence is supported, with a0 holding
* a function pointer, a1 a pointer to the new stack to call the
* function with or 0 if no stack switching is requested, a2-a7 -- the
* function call's first six arguments, and the stack -- the remaining
* arguments (up to O32_ARGC, including a2-a7). Static registers, gp
* and fp are preserved, v0 holds the result. This code relies on the
* called o32 function for sp and ra restoration and this dispatcher has
* to be placed in a KSEGx (or KUSEG) address space. Any pointers
* passed have to point to addresses within one of these spaces as well.
*/
NESTED(call_o32, O32_FRAMESZ, ra)
REG_SUBU sp,O32_FRAMESZ
@ -51,32 +60,36 @@ NESTED(call_o32, O32_FRAMESZ, ra)
REG_S s0,O32_FRAMESZ-11*SZREG(sp)
move jp,a0
REG_SUBU s0,a1,O32_FRAMESZ_NEW
REG_S sp,O32_FRAMESZ_NEW-1*SZREG(s0)
move fp,sp
beqz a1,0f
REG_SUBU fp,a1,O32_NFRAMESZ
0:
REG_S sp,O32_NFRAMESZ-1*SZREG(fp)
sll a0,a2,zero
sll a1,a3,zero
sll a2,a4,zero
sll a3,a5,zero
sw a6,0x10(s0)
sw a7,0x14(s0)
sw a6,4*O32_SZREG(fp)
sw a7,5*O32_SZREG(fp)
PTR_LA t0,O32_FRAMESZ(sp)
PTR_LA t1,0x18(s0)
PTR_LA t1,6*O32_SZREG(fp)
li t2,O32_ARGC-6
1:
lw t3,(t0)
REG_ADDU t0,SZREG
sw t3,(t1)
REG_SUBU t2,1
REG_ADDU t1,4
REG_ADDU t1,O32_SZREG
bnez t2,1b
move sp,s0
move sp,fp
jalr jp
REG_L sp,O32_FRAMESZ_NEW-1*SZREG(sp)
REG_L sp,O32_NFRAMESZ-1*SZREG(sp)
REG_L s0,O32_FRAMESZ-11*SZREG(sp)
REG_L s1,O32_FRAMESZ-10*SZREG(sp)

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