ahci_imx: add ahci sata support on imx platforms
imx6q contains one Synopsys AHCI SATA controller, But it can't share ahci_platform driver with other controllers because there are some misalignments of the generic AHCI controller - the bits definitions of the HBA registers, the Vendor Specific registers, the AHCI PHY clock and the AHCI signals adjustment window(GPR13 register). - CAP_SSS(bit20) of the HOST_CAP is writable, default value is '0', should be configured to be '1' - bit0 (only one AHCI SATA port on imx6q) of the HOST_PORTS_IMPL should be set to be '1'.(default 0) - One Vendor Specific register HOST_TIMER1MS(offset:0xe0) should be configured regarding to the frequency of AHB bus clock. - Configurations of the AHCI PHY clock, and the signal parameters of the GPR13 Setup its own ahci sata driver, contained the imx6q specific initialized codes, re-use the generic ahci_platform driver, and keep the generic ahci_platform driver clean as much as possible. tj: patch description reformatted Signed-off-by: Richard Zhu <r65037@freescale.com> Reviewed-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Tejun Heo <tj@kernel.org>
This commit is contained in:
Richard Zhu
Tejun Heo
parent
6a6c21ef48
commit
9e54eae23b
3 changed files with 246 additions and 0 deletions
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@ -97,6 +97,15 @@ config SATA_AHCI_PLATFORM
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If unsure, say N.
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config AHCI_IMX
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tristate "Freescale i.MX AHCI SATA support"
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depends on SATA_AHCI_PLATFORM
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help
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This option enables support for the Freescale i.MX SoC's
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onboard AHCI SATA.
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If unsure, say N.
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config SATA_FSL
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tristate "Freescale 3.0Gbps SATA support"
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depends on FSL_SOC
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@ -10,6 +10,7 @@ obj-$(CONFIG_SATA_INIC162X) += sata_inic162x.o
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obj-$(CONFIG_SATA_SIL24) += sata_sil24.o
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obj-$(CONFIG_SATA_DWC) += sata_dwc_460ex.o
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obj-$(CONFIG_SATA_HIGHBANK) += sata_highbank.o libahci.o
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obj-$(CONFIG_AHCI_IMX) += ahci_imx.o
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# SFF w/ custom DMA
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obj-$(CONFIG_PDC_ADMA) += pdc_adma.o
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236
drivers/ata/ahci_imx.c
Normal file
236
drivers/ata/ahci_imx.c
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@ -0,0 +1,236 @@
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/*
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* Freescale IMX AHCI SATA platform driver
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* Copyright 2013 Freescale Semiconductor, Inc.
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*
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* based on the AHCI SATA platform driver by Jeff Garzik and Anton Vorontsov
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/ahci_platform.h>
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#include <linux/of_device.h>
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#include <linux/mfd/syscon.h>
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#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
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#include "ahci.h"
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enum {
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HOST_TIMER1MS = 0xe0, /* Timer 1-ms */
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};
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struct imx_ahci_priv {
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struct platform_device *ahci_pdev;
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struct clk *sata_ref_clk;
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struct clk *ahb_clk;
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struct regmap *gpr;
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};
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static int imx6q_sata_init(struct device *dev, void __iomem *mmio)
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{
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int ret = 0;
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unsigned int reg_val;
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struct imx_ahci_priv *imxpriv = dev_get_drvdata(dev->parent);
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imxpriv->gpr =
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syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
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if (IS_ERR(imxpriv->gpr)) {
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dev_err(dev, "failed to find fsl,imx6q-iomux-gpr regmap\n");
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return PTR_ERR(imxpriv->gpr);
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}
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ret = clk_prepare_enable(imxpriv->sata_ref_clk);
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if (ret < 0) {
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dev_err(dev, "prepare-enable sata_ref clock err:%d\n", ret);
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return ret;
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}
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/*
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* set PHY Paremeters, two steps to configure the GPR13,
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* one write for rest of parameters, mask of first write
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* is 0x07fffffd, and the other one write for setting
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* the mpll_clk_en.
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*/
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regmap_update_bits(imxpriv->gpr, 0x34, IMX6Q_GPR13_SATA_RX_EQ_VAL_MASK
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| IMX6Q_GPR13_SATA_RX_LOS_LVL_MASK
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| IMX6Q_GPR13_SATA_RX_DPLL_MODE_MASK
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| IMX6Q_GPR13_SATA_SPD_MODE_MASK
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| IMX6Q_GPR13_SATA_MPLL_SS_EN
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| IMX6Q_GPR13_SATA_TX_ATTEN_MASK
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| IMX6Q_GPR13_SATA_TX_BOOST_MASK
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| IMX6Q_GPR13_SATA_TX_LVL_MASK
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| IMX6Q_GPR13_SATA_TX_EDGE_RATE
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, IMX6Q_GPR13_SATA_RX_EQ_VAL_3_0_DB
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| IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA2M
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| IMX6Q_GPR13_SATA_RX_DPLL_MODE_2P_4F
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| IMX6Q_GPR13_SATA_SPD_MODE_3P0G
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| IMX6Q_GPR13_SATA_MPLL_SS_EN
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| IMX6Q_GPR13_SATA_TX_ATTEN_9_16
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| IMX6Q_GPR13_SATA_TX_BOOST_3_33_DB
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| IMX6Q_GPR13_SATA_TX_LVL_1_025_V);
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regmap_update_bits(imxpriv->gpr, 0x34, IMX6Q_GPR13_SATA_MPLL_CLK_EN,
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IMX6Q_GPR13_SATA_MPLL_CLK_EN);
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usleep_range(100, 200);
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/*
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* Configure the HWINIT bits of the HOST_CAP and HOST_PORTS_IMPL,
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* and IP vendor specific register HOST_TIMER1MS.
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* Configure CAP_SSS (support stagered spin up).
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* Implement the port0.
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* Get the ahb clock rate, and configure the TIMER1MS register.
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*/
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reg_val = readl(mmio + HOST_CAP);
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if (!(reg_val & HOST_CAP_SSS)) {
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reg_val |= HOST_CAP_SSS;
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writel(reg_val, mmio + HOST_CAP);
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}
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reg_val = readl(mmio + HOST_PORTS_IMPL);
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if (!(reg_val & 0x1)) {
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reg_val |= 0x1;
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writel(reg_val, mmio + HOST_PORTS_IMPL);
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}
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reg_val = clk_get_rate(imxpriv->ahb_clk) / 1000;
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writel(reg_val, mmio + HOST_TIMER1MS);
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return 0;
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}
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static void imx6q_sata_exit(struct device *dev)
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{
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struct imx_ahci_priv *imxpriv = dev_get_drvdata(dev->parent);
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regmap_update_bits(imxpriv->gpr, 0x34, IMX6Q_GPR13_SATA_MPLL_CLK_EN,
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!IMX6Q_GPR13_SATA_MPLL_CLK_EN);
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clk_disable_unprepare(imxpriv->sata_ref_clk);
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}
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static struct ahci_platform_data imx6q_sata_pdata = {
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.init = imx6q_sata_init,
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.exit = imx6q_sata_exit,
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};
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static const struct of_device_id imx_ahci_of_match[] = {
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{ .compatible = "fsl,imx6q-ahci", .data = &imx6q_sata_pdata},
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{},
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};
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MODULE_DEVICE_TABLE(of, imx_ahci_of_match);
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static int imx_ahci_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct resource *mem, *irq, res[2];
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const struct of_device_id *of_id;
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const struct ahci_platform_data *pdata = NULL;
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struct imx_ahci_priv *imxpriv;
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struct device *ahci_dev;
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struct platform_device *ahci_pdev;
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int ret;
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imxpriv = devm_kzalloc(dev, sizeof(*imxpriv), GFP_KERNEL);
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if (!imxpriv) {
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dev_err(dev, "can't alloc ahci_host_priv\n");
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return -ENOMEM;
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}
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ahci_pdev = platform_device_alloc("ahci", -1);
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if (!ahci_pdev)
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return -ENODEV;
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ahci_dev = &ahci_pdev->dev;
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ahci_dev->parent = dev;
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imxpriv->ahb_clk = devm_clk_get(dev, "ahb");
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if (IS_ERR(imxpriv->ahb_clk)) {
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dev_err(dev, "can't get ahb clock.\n");
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ret = PTR_ERR(imxpriv->ahb_clk);
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goto err_out;
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}
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imxpriv->sata_ref_clk = devm_clk_get(dev, "sata_ref");
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if (IS_ERR(imxpriv->sata_ref_clk)) {
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dev_err(dev, "can't get sata_ref clock.\n");
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ret = PTR_ERR(imxpriv->sata_ref_clk);
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goto err_out;
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}
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imxpriv->ahci_pdev = ahci_pdev;
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platform_set_drvdata(pdev, imxpriv);
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of_id = of_match_device(imx_ahci_of_match, dev);
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if (of_id) {
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pdata = of_id->data;
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} else {
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ret = -EINVAL;
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goto err_out;
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}
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mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
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if (!mem || !irq) {
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dev_err(dev, "no mmio/irq resource\n");
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ret = -ENOMEM;
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goto err_out;
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}
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res[0] = *mem;
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res[1] = *irq;
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ahci_dev->coherent_dma_mask = DMA_BIT_MASK(32);
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ahci_dev->dma_mask = &ahci_dev->coherent_dma_mask;
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ahci_dev->of_node = dev->of_node;
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ret = platform_device_add_resources(ahci_pdev, res, 2);
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if (ret)
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goto err_out;
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ret = platform_device_add_data(ahci_pdev, pdata, sizeof(*pdata));
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if (ret)
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goto err_out;
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ret = platform_device_add(ahci_pdev);
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if (ret) {
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err_out:
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platform_device_put(ahci_pdev);
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return ret;
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}
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return 0;
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}
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static int imx_ahci_remove(struct platform_device *pdev)
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{
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struct imx_ahci_priv *imxpriv = platform_get_drvdata(pdev);
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struct platform_device *ahci_pdev = imxpriv->ahci_pdev;
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platform_device_unregister(ahci_pdev);
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return 0;
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}
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static struct platform_driver imx_ahci_driver = {
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.probe = imx_ahci_probe,
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.remove = imx_ahci_remove,
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.driver = {
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.name = "ahci-imx",
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.owner = THIS_MODULE,
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.of_match_table = imx_ahci_of_match,
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},
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};
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module_platform_driver(imx_ahci_driver);
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MODULE_DESCRIPTION("Freescale i.MX AHCI SATA platform driver");
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MODULE_AUTHOR("Richard Zhu <Hong-Xing.Zhu@freescale.com>");
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MODULE_LICENSE("GPL");
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MODULE_ALIAS("ahci:imx");
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