Documentation: dt: reset: Add TI syscon reset binding
Add TI syscon reset controller binding. This will hook to the reset framework and use syscon/regmap to set reset bits. This allows reset control of individual SoC subsytems and devices with memory-mapped reset registers in a common register memory space. Signed-off-by: Andrew F. Davis <afd@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
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Andrew F. Davis
Philipp Zabel
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91
Documentation/devicetree/bindings/reset/ti-syscon-reset.txt
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Documentation/devicetree/bindings/reset/ti-syscon-reset.txt
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TI SysCon Reset Controller
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=======================
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Almost all SoCs have hardware modules that require reset control in addition
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to clock and power control for their functionality. The reset control is
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typically provided by means of memory-mapped I/O registers. These registers are
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sometimes a part of a larger register space region implementing various
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functionalities. This register range is best represented as a syscon node to
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allow multiple entities to access their relevant registers in the common
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register space.
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A SysCon Reset Controller node defines a device that uses a syscon node
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and provides reset management functionality for various hardware modules
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present on the SoC.
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SysCon Reset Controller Node
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============================
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Each of the reset provider/controller nodes should be a child of a syscon
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node and have the following properties.
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Required properties:
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--------------------
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- compatible : Should be,
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"ti,k2e-pscrst"
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"ti,k2l-pscrst"
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"ti,k2hk-pscrst"
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"ti,syscon-reset"
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- #reset-cells : Should be 1. Please see the reset consumer node below
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for usage details
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- ti,reset-bits : Contains the reset control register information
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Should contain 7 cells for each reset exposed to
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consumers, defined as:
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Cell #1 : offset of the reset assert control
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register from the syscon register base
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Cell #2 : bit position of the reset in the reset
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assert control register
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Cell #3 : offset of the reset deassert control
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register from the syscon register base
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Cell #4 : bit position of the reset in the reset
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deassert control register
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Cell #5 : offset of the reset status register
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from the syscon register base
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Cell #6 : bit position of the reset in the
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reset status register
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Cell #7 : Flags used to control reset behavior,
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availible flags defined in the DT include
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file <dt-bindings/reset/ti-syscon.h>
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SysCon Reset Consumer Nodes
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===========================
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Each of the reset consumer nodes should have the following properties,
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in addition to their own properties.
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Required properties:
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--------------------
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- resets : A phandle to the reset controller node and an index number
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to a reset specifier as defined above.
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Please also refer to Documentation/devicetree/bindings/reset/reset.txt for
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common reset controller usage by consumers.
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Example:
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--------
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The following example demonstrates a syscon node, the reset controller node
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using the syscon node, and a consumer (a DSP device) on the TI Keystone 2
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Edison SoC.
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/ {
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soc {
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psc: power-sleep-controller@02350000 {
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compatible = "syscon", "simple-mfd";
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reg = <0x02350000 0x1000>;
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pscrst: psc-reset {
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compatible = "ti,k2e-pscrst", "ti,syscon-reset";
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#reset-cells = <1>;
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ti,reset-bits = <
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0xa3c 8 0xa3c 8 0x83c 8 (ASSERT_SET|DEASSERT_CLEAR|STATUS_SET) /* 0: pcrst-dsp0 */
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0xa40 5 0xa44 3 0 0 (ASSERT_SET|DEASSERT_CLEAR|STATUS_NONE) /* 1: pcrst-example */
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>;
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};
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};
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dsp0: dsp0 {
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...
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resets = <&pscrst 0>;
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...
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};
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};
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};
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38
include/dt-bindings/reset/ti-syscon.h
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38
include/dt-bindings/reset/ti-syscon.h
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/*
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* TI Syscon Reset definitions
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*
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* Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __DT_BINDINGS_RESET_TI_SYSCON_H__
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#define __DT_BINDINGS_RESET_TI_SYSCON_H__
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/*
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* The reset does not support the feature and corresponding
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* values are not valid
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*/
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#define ASSERT_NONE (1 << 0)
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#define DEASSERT_NONE (1 << 1)
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#define STATUS_NONE (1 << 2)
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/* When set this function is activated by setting(vs clearing) this bit */
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#define ASSERT_SET (1 << 3)
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#define DEASSERT_SET (1 << 4)
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#define STATUS_SET (1 << 5)
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/* The following are the inverse of the above and are added for consistency */
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#define ASSERT_CLEAR (0 << 3)
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#define DEASSERT_CLEAR (0 << 4)
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#define STATUS_CLEAR (0 << 5)
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#endif
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